JPH0515069B2 - - Google Patents

Description

[Detailed description of the invention] (1) Technical field to which the invention pertains The present invention relates to an MIS type semiconductor integrated circuit device,
In particular, the present invention relates to an element isolation structure having radiation resistance that can be applied to semiconductor integrated circuit devices.

(2) Description of the prior art In general, device isolation in MIS type semiconductor integrated circuit devices is performed using a thick isolation oxide film. For example, in the case of the commonly used selective oxidation process using thermal oxidation, the transistor structure is as shown in Figure 1. It is arranged as shown in a to c. Here, FIG. 1a is a plan layout diagram of a transistor, 11 is a gate electrode, 12
are source/drain electrodes. The same figure b is the same figure a
Figure c is a cross-section taken along line A-A' in Figure b, showing the cross-sectional structure of the active transistor, and Figure c is a cross-section taken along B-B' in Figure b, which shows the cross-section of the field transistor connecting the source electrode and drain electrode of the active transistor. It shows the structure. Here, 13 is a silicon semiconductor substrate, 14 is a high concentration impurity layer for element isolation to prevent channel formation between the active region 12 and other active regions, 15 is a field oxide film providing an element isolation region, and 16 is a high concentration impurity layer for element isolation. is the gate oxide that provides the active area. In the transistor with the structure shown in Figure 1a, the threshold voltage of the field transistor is usually sufficiently higher than that of the active transistor, and when the gate electrode of the active transistor is set to zero, the subthreshold voltage flowing between the source and drain is The subthreshold current of a field transistor in parallel with an active transistor that deceives leakage currents is negligible, for example by more than 10 orders of magnitude smaller.

However, in a transistor with such a structure, γ
When irradiated with ionizing radiation such as X-rays, X-rays, electron beams, proton beams, etc., electron-hole pairs are generated in the gate oxide film 16 and field oxide film 15, and the holes among these are transferred to the oxide film. At the same time, a large number of hole traps exist in the oxide film near the interface between the silicon substrate and the hole trap, and a positive fixed charge is accumulated in the oxide film.
Formation of interface states due to accumulation of holes or positive charges occurs at the interface, and as the deceptive phenomenon occurs, a significant change occurs in the subthreshold characteristics of the transistor. In other words, the positive fixed charge in the oxide film changes the threshold voltage of the transistor in the negative direction, and the generation of interface states lowers the slope of the subthreshold characteristics of the transistor, but as a result, the subthreshold leakage current increases with irradiation. heading in the direction of increasing. Although the increase in deceptive leakage current occurs in both N-channel transistors and P-channel transistors, the increase in leakage current in N-channel transistors is significant as the threshold voltage changes in the negative direction. Further, the deception phenomenon becomes more serious as the oxide film on the silicon substrate becomes thicker, so when comparing active transistors and field transistors, the leakage current of the field transistor increases significantly. For example, as shown in FIG. 1d, when an active transistor is irradiated with radiation, the characteristics change from I to I', whereas in the case of a field transistor, the characteristics change greatly from to to'. Therefore, in the transistors with conventional structures shown in Figures 1a to 1c, radiation irradiation results in composite characteristics of the active transistor characteristics and the field transistor characteristics as shown in Figure 1d, giving the appearance of an active transistor. This has the disadvantage that leakage current increases, and in severe cases, it becomes unusable as a transistor. Of course, the leakage current of the field transistor can be reduced by increasing the concentration of the high concentration impurity layer for preventing the formation of the inversion layer 14 in Figure 1c, but when considering the reduction in the breakdown voltage of the junction with the source or drain electrode. The concentration of the deceptive high-concentration impurity layer cannot be raised above a certain value,
This determines the radiation tolerance. According to the author's study, a high concentration impurity layer that guarantees a junction breakdown voltage of 10V or more can only provide a radiation resistance of less than 1×10 ⁵ rods (Si), which is insufficient for a radiation-resistant device. That is, the conventional device structure has a drawback in that it cannot sufficiently suppress an increase in subthreshold leakage current of a field transistor due to radiation irradiation.

(3) Purpose of the Invention In view of the above points, the present invention solves the above-mentioned drawbacks by bringing a high concentration impurity region for element isolation, which was conventionally formed under the field oxide film, into the active region. The present invention provides a semiconductor integrated circuit device with excellent radiation resistance.

(4) Structure of the Invention According to the present invention, source and drain regions of a second conductivity type formed on a semiconductor substrate of a first conductivity type, and these source and drain regions via a gate oxide film. a thick element isolation oxide film formed on the semiconductor substrate surrounding the source and drain regions and the channel region, and the source and drain regions. and a first conductivity type impurity with a surface impurity concentration higher than the substrate concentration formed in the semiconductor substrate between the channel region and the element isolation oxide film and in contact with these and surrounding the source and drain regions and the channel region. MIS type in which the gate electrode extends over the channel stopper region through an insulating film having the same thickness as the gate oxide film, and extends onto the element isolation oxide film. A semiconductor integrated circuit device is obtained.

(5) Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 2 is an example of a specific embodiment according to the present invention.
Figure a is a plan layout, figure b is A- in figure a.
The cross-sectional structure of A', the figure c shows the cross-sectional structure of B-B', and the figure d shows the subthreshold characteristics after radiation irradiation. In FIG. 3A, reference numeral 21 denotes a high concentration impurity region of the substrate and conductivity type, which is located between the LOCOS region and the source and drain regions of the transistor, and plays the role of element isolation. That is, even if an operating voltage is applied to the gate electrode, the channel of the parasitic transistor shown by c in the figure is not inverted. When this structure is irradiated with radiation, the threshold voltage of the transistor changes due to the positive charges accumulated in the oxide film as described above, as can be seen by comparing Figures 1c and 2c. In the structure according to the present invention, the oxide film thickness in the element isolation region is thinner, and therefore the amount of change in threshold voltage is also smaller. Furthermore, the change in the slope of the subthreshold characteristic is smaller when the oxide film thickness is thinner, and in the case of the structure according to the present invention, the change in the slope of the subthreshold characteristic of the active transistor and the parasitic transistor is almost the same. . Therefore the active transistor (Fig. 2b) and the parasitic transistor (Fig. 2c)
After being irradiated with radiation, the subthreshold characteristics of are as shown in ′ and ′ in Figure 2 d, and the characteristics obtained by combining these are almost the same as ′, and leakage due to parasitic transistors is It can be seen that the current can be ignored. Comparing the composite characteristics of FIG. 2(d) and FIG. 1(d), it will be clear how superior the method of isolation between elements according to the present invention is in terms of radiation resistance.

FIG. 3 is a reference example for comparison with the element isolation structure according to the present invention. In the case of the same figure, a high concentration impurity region 31 for element isolation is formed only near the bottom of the gate electrode region, and in the deceptive structure, element isolation between the drain and source is LOCOS.
This is not done completely because a leakage current path remains through the oxide film. However, since the leakage current path becomes longer, the leakage current can be reduced by that much. In the case of FIG. 2, the element isolation region surrounds the source and drain regions, so element isolation is complete.

Next, an example of a method for manufacturing an element isolation structure according to the present invention will be described. As shown in FIG. 4A, after forming the selective oxide film 42, a mask material 44 such as photoresist is patterned over the active region, with the peripheral portion removed. Thereafter, impurities of the same conductivity type as the substrate are implanted into the periphery of the active region by ion implantation to form element isolation regions 45. For example, this is the board 41
When is P-type, impurities such as boron are ~10 ¹³ cm ^-2
It is enough to inject a certain amount. After removing the mask material (FIG. 4b), a gate electrode 46 is patterned, and then a material 47 such as aluminum, which will serve as a mask for ion implantation, is patterned on the selective oxide film 42 and the element isolation region 45. Then, ion implantation is performed to form source and drain regions. In the case of a P-type substrate, for example, impurities such as arsenic are added to 5×10 ¹⁵
It is sufficient to use a dose of about cm ^-2 . At this time, the source/drain region 48 and the element isolation region 45 are made to contact each other (FIG. 4c). Removal of the mask material results in the structure shown in FIG. 2b (FIG. 4d).

In such a structure, the element isolation region is formed not in the LOCOS oxide film region but in the periphery of the active region, so changes in characteristics due to radiation irradiation are small to begin with and are not easily affected by radiation. Therefore, this method is suitable as an element isolation method for radiation-resistant devices, and it is hoped that the radiation tolerance of semiconductor integrated circuit devices, which conventionally could not be guaranteed to operate due to the difficulty of element isolation, will be improved by applying the present invention. Is possible.

In addition, in the above explanation,
Although an NMOS transistor is taken as an example, the effectiveness of the present invention is not hindered in any way also for an NMOS transistor on a P-well formed on an N-type substrate. Further, the present invention may be applied to a complementary integrated circuit device formed on a P-type substrate or an N-type substrate, and the usefulness of the present invention is obvious.

(6) Effects of the Invention As explained above, the present invention suppresses variations in parasitic MOS characteristics when exposed to radiation by providing an element isolation region at the periphery of the active region, and provides a radiation-resistant MIS. This makes it possible to manufacture type semiconductor integrated circuit devices.

[Brief explanation of the drawing]

FIG. 1 is a planar layout a, cross-sectional views b and c, and subthreshold characteristic diagram d of a transistor with a conventional structure, and FIG. 2 is a planar layout a of an embodiment of a transistor with an element isolation structure according to the present invention. , cross-sectional views b and c, and a subthreshold characteristic diagram d, and FIG. 3 is a plan view of a reference example for comparison with a transistor having an element isolation structure according to the present invention. Further, FIG. 4 is a process cross-sectional view showing an example of the method for manufacturing the element isolation structure of the present invention. DESCRIPTION OF SYMBOLS 11... Gate electrode, 12... Source, drain region, 13... Silicon substrate, 14... High concentration impurity region for element isolation, 15... Oxide film by selective thermal oxidation, 16... Gate oxide film, 21... ... High concentration impurity region for element isolation, 22 ... Gate electrode,
23...Source, drain region, 24...Silicon substrate, 25...Oxide film by selective thermal oxidation, 26
... Gate oxide film, 31 ... High concentration impurity region for element isolation, 32 ... Gate electrode, 33 ... Source, drain region, 41 ... Silicon substrate, 42
... Oxide film by selective thermal oxidation, 43 ... Gate oxide film, 44 ... Mask material, 45 ... High concentration impurity region for element isolation, 46 ... Gate electrode, 47 ...
Mask material, 48... Source, drain diffusion layer.

Claims (1)

[Claims] 1 source and drain regions of a second conductivity type formed on a semiconductor substrate of a first conductivity type;
A gate electrode formed on the upper part of the channel region located between the source and drain regions via a gate oxide film, and a thickness formed on the semiconductor substrate surrounding the source and drain regions and the channel region. a thick element isolation oxide film, and a thick element isolation oxide film on the semiconductor substrate so as to be in contact with the source and drain regions, the channel region, and the element isolation oxide film, and to surround the source and drain regions and the channel region. a channel stopper region of the first conductivity type and having a surface impurity concentration higher than the substrate concentration; the gate electrode is connected to the channel stopper region through an insulating film having the same thickness as the gate oxide film; An MIS type semiconductor integrated circuit device, characterized in that the MIS type semiconductor integrated circuit device is formed so as to extend over the region and even onto the element isolation oxide film.