JPH0515346B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a signal processing device for converting an analog signal output from a charge transfer type image sensor, a charge transfer type delay line, etc. into a digital signal.

(Prior Art) The recent progress in digital technology, coupled with the development of semiconductor integrated circuit technology, has been remarkable.
This is because large-capacity digital memories such as 64K bits and 256K bits, A/D converters, D/A converters, etc. have become available on the market at relatively low prices and in large quantities. The rise of digital technology is no exception in the field of video equipment.
Devices that were difficult to implement using conventional analog systems, such as frame synchronizers and noise reducers, became easily possible through digitalization (Journal of the Television Society, April 1979 issue [No.
Volume 33, No. 4]). Furthermore, digital systems are superior in terms of equipment economy, stability, reduction of adjustment man-hours, and ease of connection with other equipment, so they have become more popular in television cameras and television receivers, where analog systems have traditionally been mainstream. (Nikkei Electronics, 1983 11-23, p.259-p.273).

(Problems with the Prior Art) When digitalizing the above-mentioned television camera, etc., the biggest problem is the circuit configuration of the part that converts the analog signal output from the image pickup tube or solid-state image sensor into a digital signal.
FIG. 4 is a block diagram showing a conventional example for obtaining digital signals from a charge transfer type image sensor, which can be said to be a typical solid-state image sensor. In the same figure,
Interline transfer charge transfer type image sensor 61
The photoelectric conversion units 62 are arranged in a matrix on the light incident surface to accumulate signal charges according to the amount of incident light, and the signal charges accumulated in the photoelectric conversion units 62 are transferred over one vertical scanning period (field or frame). ), a vertical register 63 for vertically transferring the read signal charge every horizontal scanning period (1H), and an electrical connection at one end of each vertical register 63. The horizontal register 64 is coupled to the horizontal register 64 to transfer signal charges in the horizontal direction, and a charge detection circuit 65 is configured to detect the signal charges from the horizontal register 64 and sequentially convert them into voltage signals. A buffer amplifier 66 which plays a role of impedance conversion is connected to the outside of the image pickup device 61 near the charge detection circuit 65 in order to prevent the mixing of external noise. After the amplitude modulation signal from the buffer amplifier 66 is set to a reference voltage in a clamp circuit 67, only the charge detection period is sampled in a sample-and-hold circuit 68, and then high-order sideband components are removed in a low-pass filter 69. is converted into an analog signal. The analog signal is amplified to a specified amplitude by an amplifier 70 and then input to an A/D converter 71, where it is converted into a digital signal for the first time.

According to the circuit configuration described above, it is possible to convert an analog quantity into a digital quantity, but there are some problems. The first problem is that because the amplitude modulation signal from the image sensor 61 is converted into an analog signal and then A/D converted, the reproduced image is affected by the characteristics of the clamp circuit 67, sample and hold circuit 68, and low-pass filter 69. This is a point that is easily affected by deterioration. Of course, if the amplitude modulation signal from the image sensor 61 is directly A/D converted, the influence of characteristic deterioration in the external circuit will be minimized, and this is also technically possible. However, in this case, after A/D converting both the reference voltage level and the charge detection period, it is necessary to perform an operation to calculate the difference between the two, which makes it difficult for television cameras to increase the circuit scale and the cost of parts used. It is unsuitable for application to small scale equipment.

The second problem is that since the image sensor 61 is originally an analog device, unique analog technology must be used for driving and signal processing, which is difficult for digital circuit engineers to understand. In order to solve this problem, if it is technically possible, it would be quick and easy to output a digital signal directly from the image sensor 61.

The third problem is that although recent A/D converters have become cheaper and faster, they still have problems in terms of power consumption, quantization accuracy, etc. This is difficult to apply to equipment.

(Object of the Invention) The present invention eliminates the above-mentioned conventional drawbacks, and its object is to provide a signal processing device that can be integrated with a charge transfer type image pickup device or the like on-chip.

(Structure of the Invention) A signal processing device of the present invention is a signal processing device that converts an output signal from a charge transfer element into a digital signal with a resolution of N bits (N: a positive integer). 2 ^M −1 (M: positive integer, M <
A charge transfer delay line with a first terminal having a first output means of N) is provided, and the output voltage from each output means is
2 ^M −1 first analog comparators, and supplying each analog comparator group with a different comparison voltage that is an integer multiple of 1/2 ^M of the reference voltage,
When these comparison voltages are larger than the output voltage from the first output means, a discrimination signal is obtained which becomes a low level, and when it is smaller, a discrimination signal becomes a high level, and these discrimination signals are transmitted to a first digital shift register group having different delay times. an upper M-bit conversion section configured to supply the signals to the first encoder to synchronize the signal outputs, and to supply the synchronized discrimination signals to the first encoder to obtain an M-bit binary number; The discrimination signals from the first analog comparator group are respectively supplied to charge generation means, and only when these discrimination signals are at a low level, a bias charge corresponding to a voltage of 1/2 ^M of the reference voltage is generated. None, and a bias charge generation section configured to add bias charges from the charge generation means, and an output signal charge from the first terminal-equipped charge transfer delay line and the bias charge from the bias charge generation section. a second terminal equipped with a charge synthesis section configured to synthesize the charge at a level, and 2 ^NM -1 second output means for non-destructively detecting the magnitude of charge from the charge synthesis section for each transfer; A charge transfer delay line is provided, and the output voltage from each output means is supplied to a second analog comparator group of 2 ^NM -1, and an integer of 1/2 ^N of the reference voltage is supplied to the analog comparator group. supplying different comparison voltages, each of which is equal to (1-1/2 ^M ) times the reference voltage, and when these comparison voltages are larger than the output voltage from the second output means, the level is low;
Discrimination signals that are at a high level when the signal is small are obtained, and these discrimination signals are supplied to a second digital shift register group each having a different delay time to synchronize the signal outputs, and these simultaneous discrimination signals are to the second encoder to obtain N−
It has a lower N-M bit converter for obtaining an M-bit binary number.

(Example) Next, an example of the present invention will be described using the drawings. The explanation here will be based on a signal generated by a charge transfer type A/D converter (hereinafter simply referred to as an A/D converter) that is integrated into a charge-coupled device (hereinafter referred to as CCD) that represents a charge transfer type image sensor. This is done for the processing equipment. In order to simplify the explanation, this A/D converter is composed of an upper 2-bit A/D converter and a lower 2-bit A/D converter, each having a level resolution of 2 bits/sample.
It is assumed that the total level resolution is 4 bits/sample.

FIG. 1 is a block diagram of an A/D converter showing one embodiment of the processing device according to the present invention, FIG. 2 is a diagram explaining the operational functions of FIG. 1, and FIG.
It is a circuit block diagram which shows a D converter more specifically.

In FIG. 1, the charge transfer type delay line 1 with terminals is
It is coupled to the output section of the CCD image sensor and delay line at the charge level. Here, the output signal charge transferred from the transfer direction 2 is transferred through the charge transfer type delay line 1 with a terminal, and at the same time, the magnitude of this signal charge is detected non-destructively for each transfer. The output means outputs the signal charge as a signal voltage from signal charge output terminals (hereinafter simply referred to as terminals) 3, 4, and 5.
Next, the signal voltages from the terminals 3, 4, and 5 are applied to the analog comparators 7, which constitute the analog comparator group 6.
It is applied to each of the signal terminals 8 and 9. On the other hand, the comparison voltage terminals of the analog comparators 7, 8, _and 9 are supplied with different comparison voltages 3V R /4, 3V _R /4,
V _R /2 and V _R /4 are applied. To explain the operation of the analog comparator 7 here, there is a relationship between the signal voltage V _S detected by the terminal-equipped charge transfer type delay line 1 and the comparison voltage 3V _R /4 such that V _S >3V _R /4. If this holds true, the determination signal C1 becomes high level "1". Further, when the relationship V _S <3V _R /4 holds true, the low level becomes "0". The operation of the other analog comparators 8 and 9 is such that the comparison voltage is V _R /2,
The only difference is that it is different from V _R /4, and the rest is exactly the same.
Therefore, the respective _{discrimination} signals C1, C2,
The state of C3 is V _S /3V _R / as shown in Figure 2.
4, all of C1, C2, and C3 are high level “1”, and when 3V _R /4>V _S >V _R /2, C2, C3
is high level "1", when V _R /2>V _S > V _R /4, only C3 is high level "1", when V _R /4> V _S , all C1, C2, and C3 are low level " 0”
becomes.

Next, the discrimination signal C from the analog comparator group 6
1, C2, and C3 are applied to digital shift registers 11, 12, and 13 having different delay times, respectively. This is because, as is clear from the operation of the charge transfer type delay line 1 with terminals, the detection of the same signal charge is delayed by one clock period in the order of terminals 3→4→5. Digital shift register 1
1, 12, and 13 are operated at the same clock cycle as the terminal-equipped charge transfer type delay line 1, and the delay times are selected to be 1, 2, and 3 clock cycles, respectively, thereby compensating for the above-mentioned delay. Finally, the discrimination signals C1, C2, and C3 synchronized by the digital shift registers 11, 12, and 13 are input to the encoder 14, where they are converted into two bits as shown in FIG.
It is converted into base numbers D1 and D2. As is clear from the above explanation, the upper two bits A are /D conversion section is configured.

Next, the discrimination signal C from the analog comparator group 6
1, C2, and C3 are also applied to the bias charge generation section 15. The bias charge generation unit 15 generates a bias charge corresponding to a voltage of 1/4 of the reference voltage _VR only when the discrimination signal is low level "0" according to the respective states of the discrimination signals C1, C2, and C3. , it's starting to add up. That is, in FIG. 2, when all of the discrimination signals C1, C2, and C3 are at high level "1", the bias charge is zero, but only C1 is at low level "0", which corresponds to V _R /4. Bias charges are generated and added, and then when both C1 and C2 are at low level "0", the bias charge corresponding to V _R /2 is
Further, when all of C1, C2, and C3 are at low level "0", bias charges corresponding to 3V _R /4 are generated and added to each.

Next, the output signal charge from the terminal-attached charge transfer type delay line 1 and the bias charge from the bias charge generation section 15 are combined at a charge level in a charge synthesis section 16. This is the lower 2 bits of A/
This is to prepare for D conversion, and as is clear from FIG. 2, the combined charge (hereinafter referred to as combined charge) is always larger than the charge corresponding to 3V _R /4. Therefore, by dividing the range of V _R >V _S >3V _R /4 into four levels and examining the magnitude relationship, A/D conversion of the lower two bits becomes possible.

Finally, the combined charge from the charge combining unit 16 is transferred through the charge transfer type delay line 17 with a terminal, and at the same time is detected non-destructively for each transfer, and is detected non-destructively at the terminal 1.
8, 19, and 20 are output as a composite signal voltage. The combined signal voltages from the terminals 18, 19, and 20 are applied to respective signal terminals of analog comparators 22, 23, and 24 constituting the analog comparator group 21. On the other hand, analog comparators 22, 23,
A comparison voltage generation circuit 25 is connected to the comparison voltage terminal 24.
Each different comparison voltage from 15V _R /16,
14V _R /16 and 13V _R /16 are applied. Therefore, when the composite signal voltage is V _C , the states of the respective discrimination signals C4, C5, and C6 of the analog comparators 22, 23, and 24 with respect to the change thereof are V _C >15V _R /16
If C4, C5, C6 are all high level "1", if 15V _R /16 > V _C > 14V _R /16, C5, C
6 is high level “1”, 14V _R /16>V _C >13V _R /
In case of 16, only C6 is high level “1”, 13V _R /16
>V _C >12V _R /16, all of C4, C5, and C6 become low level "0". Here, as mentioned above, there are four types of bias charges included in the composite signal voltage V _C : 0, V _R /4, V _R /2, and 3V _R /4, so the discrimination condition for the signal voltage V _S is ,
As shown in Figure 2, there are 16 types. Next, the discrimination signals C1, C2, and C3 from the analog comparator group 21 are applied to digital filters 26, 27, and 28 having different delay times and are synchronized, and then input to the encoder 29, where the As shown in Figure 2, 2-bit binary numbers D3 and D4
is converted to That is, a charge transfer type delay line 17 with a terminal, an analog comparator group 21, a comparison voltage generation circuit 25, digital shift registers 26, 27,
28 and encoder 29, the lower two bits A/
This means that the D conversion section has been configured. Therefore, including the upper 2-bit A/D conversion section mentioned above, the total level resolution is 4 bits/sample.
This means that a converter has been realized.

As is clear from the above description, the A/D converter according to this embodiment operates with the same clock as the CCD, so it is very fast. Furthermore, the circuit scale is significantly reduced compared to the type in which the comparison between the signal voltage and the reference voltage is performed using only one terminal-equipped charge transfer type delay line. For example, the number of comparators required for 4-bit A/D conversion is normally 15, but can be reduced to 6 according to this embodiment. Furthermore, since analog comparators, digital shift registers, encoders, etc. can be manufactured using the same semiconductor process technology as the CCD, there are many advantages such as ease of on-chip integration with the CCD.

Next, FIG. 3 will be explained. In the figure, the same reference numerals as in FIG. 1 indicate the same components. In this embodiment, floating electrodes 30 to 35 are used for non-destructive detection of signal charges. These floating electrodes 30 to 35 receive transfer pulses φ ₁ and φ ₂
is provided between the pair of transfer electrodes to which DC bias voltage is applied. Therefore, charge transfer in the charge transfer type delay lines 1 and 17 with terminals is performed by so-called 2 1/2 phase drive. A drain 36 for absorbing transferred charges is provided at the terminal end of the charge transfer type delay line 17 with terminals. Here, the signal voltages detected at the floating electrodes 30 to 35 are applied to the analog comparators 7, 8, 9 and 22, 23, 2 that constitute the analog comparator groups 6 and 21.
4 is applied to each of the signal terminals. On the other hand, the comparison voltage generation circuit 37 is constructed by connecting resistors 38 to 44 in series. Here resistance 38
By selecting resistors 41 to 44 to have the same resistance value R, and selecting resistors 41 to 44 to have a resistance value 1/4 of R, comparators 7,
Different comparison voltages 3V _R /4, V _R /2,
V _R /4, 15 V _R /16, 14 V _R /16, and 13 V _R /16 are applied. Therefore, the analog comparators 6 and 21 operate in exactly the same manner as described with reference to FIG.

Next, the charge input sections 45, 46, and 47 constituting the bias charge generation section 15 input a reference voltage using a potential balance input method well known to those skilled in the art.
A bias charge corresponding to 1/4 voltage of V _R is generated. Furthermore, gate electrodes 48, 49, and 50 are provided adjacent to the charge input sections 45, 46, and 47. These gate electrodes 48, 49, 50 include
Discrimination signals C1, C2, C from analog comparator group 6
3 is applied via inverters 51, 52, and 53, respectively. Therefore, the discrimination signals C1, C
Only when C2 and C3 are at low level "0", bias charges are injected into the CCD channel from the charge input sections 45, 46, and 47. Bias charge generation section 1
The charge transfer at 5 is driven in 2 1/2 phase with the same clock cycle as the charge transfer type delay lines 1 and 17 with terminals by transfer pulses φ ₁ and φ ₂ and bias voltage V _B . Further, the charge input sections 45, 46, 47 and the gate electrodes 48, 49, 50 are arranged to be shifted by one clock period. This is to compensate for the delay in detection of the same signal charge at the floating electrodes 30, 31, 32.

Next, the output signal charge from the terminal-attached charge transfer type delay line 1 and the bias charge from the bias charge generation section 15 are transferred to the addition electrode 5 forming the charge combining section 16.
By turning on 4, charge levels are combined. Since the subsequent operation is exactly the same as that described with reference to FIG. 1, the description will be omitted here.

In this example, the level resolution is 4 bits/
Although we have described a sample A/D converter, generally an N bit/sample A/D converter is also 2 ^M -
By providing an upper M-bit A/D conversion section using one analog comparator (N>M, M: a positive integer) and a lower N-M bit A/D conversion section using 2 ^NM analog comparators. , can be realized with a similar configuration.

(Effects of the Invention) As described above, according to the present invention, there are two charge transfer delay lines with terminals, two analog comparator groups,
By the bias charge generation section and the charge synthesis section,
By configuring the upper A/D converter and the lower A/D converter, a signal processing device that can be integrated with a charge transfer type image sensor or the like on a chip and that can operate at high speed can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an A/D converter showing one embodiment of a signal processing device according to the present invention, and FIG.
FIG. 3 is a circuit configuration diagram showing the A/D converter of this embodiment in more detail, and FIG. 4 is a block diagram showing a conventional signal processing device. . 1, 17...Charge transfer type delay line with terminal, 2...
Transfer direction, 3, 4, 5, 18, 19, 20... Signal charge output terminal, 6, 21... Analog comparator group, 7, 8, 9, 22, 23, 24... Analog comparator, 10, 25, 37... Comparison voltage generation circuit, 11, 12, 13, 26, 27, 28... Digital shift register, 14, 29... Encoder, 15... Bias charge generation section, 16... Charge synthesis section, 30-35...Floating electrode, 3
6...Drain, 38-44...Resistance, 45,4
6, 47... Charge input section, 48, 49, 50...
Gate electrode, 51, 52, 53... Inverter, 54... Addition electrode, 61... Charge transfer type image sensor, 62... Photoelectric conversion section, 63... Vertical register, 64... Horizontal register, 65... Charge Detection circuit, 66... Buffer amplifier, 67... Clamp circuit, 68... Sample hold circuit, 69...
...Low pass filter, 70...Amplifier, 71...
A/D converter.

Claims (1)

[Claims] 1 In a signal processing device that converts the output signal from a charge transfer element into a digital signal with a resolution of N bits (N: a positive integer), the size of the output signal charge is detected non-destructively for each transfer.2 ^M A charge transfer delay line with a first terminal having -1 (M: positive integer, M<N) first output means is provided, and the output voltage from each output means is set to 2 ^M -1 first output means. 1 analog comparator group, and each analog comparator group is supplied with different comparison voltages that are an integral multiple of 1/2 ^M of the reference voltage, so that these comparison voltages are equal to the first analog comparator group.
A discrimination signal is obtained which becomes a low level when the output voltage is larger than the output voltage from the output means, and a high level when it is smaller than the output voltage from the output means. an upper M-bit converter which performs synchronization and supplies these simultaneous discrimination signals to a first encoder to obtain an M-bit binary number; and from the first analog comparator group. , respectively, by supplying the discrimination signals to the charge generation means,
A bias charge generation section configured to generate a bias charge corresponding to a voltage of 1/2 ^M of the reference voltage only when these discrimination signals are at a low level, and to add the bias charge from the charge generation means. and a charge combining unit configured to combine the output signal charge from the first terminal-attached charge transfer delay line and the bias charge from the bias charge generating unit at a charge level, and the magnitude of the charge from the charge combining unit. A second terminal-equipped charge transfer delay line with 2 ^NM -1 second output means is provided to non-destructively detect the voltage for each transfer, and the output voltage from each output means is set to 2 ^NM .
- one second analog comparator group, and the analog comparator group is supplied with an integer multiple of 1/2 ^N of the reference voltage plus (1-1/2 ^M ) times the reference voltage; Different comparison voltages are supplied to obtain discrimination signals that are low level when these comparison voltages are larger than the output voltage from the second output means, and high level when they are smaller, and these discrimination signals are respectively delayed by delay times. The signals are supplied to a second group of digital shift registers having different numbers to synchronize the signal outputs, and these synchronized discrimination signals are supplied to a second encoder to obtain a binary number of N-M bits. 1. A signal processing device comprising: a lower N-M bit converting section.