JPH0620274B2 - Signal processing circuit - Google Patents

Description

The present invention relates to a signal processing circuit for converting an analog signal output from a charge transfer type image pickup device, a charge transfer type delay line or the like into a digital signal.

(Prior Art) Recent advances in digital technology have been remarkable along with the development of semiconductor integrated circuit technology. This is a large-capacity digital memory such as 64K bits and 256K bits,
This is because A / D converters, D / A converters, etc. have been supplied to the market relatively inexpensively and in large quantities. The rise of this digital technology is no exception in the field of video equipment, and even devices such as frame synchronizers and noise reducers, which were difficult to realize with conventional analog systems, can be easily realized by digitization ("TV Journal of the Society of John ", April 1979 issue [Vol. 33, No. 4]). Furthermore, this digital system is excellent in terms of device economy, stabilization, reduction of adjustment man-hours, and ease of connection with other devices. Is about to be applied to (“Nikkei Electronics” 1983 November 23, 1983)
259-273).

(Problems of Prior Art) The biggest problem in digitizing this television camera is a circuit configuration of a portion for converting an analog signal output from the image pickup tube or the solid-state image pickup element into a digital signal. FIG. 6 shows an example of a conventional circuit configuration for obtaining a digital signal from a charge-coupled image pickup device which is a typical solid-state image pickup device. In the figure, an interline transfer type charge-coupled image pickup device 61 has photoelectric conversion units 62 arranged in a matrix on a light incident surface for accumulating signal charges according to the amount of incident light, and the photoelectric conversion units 62. One vertical scanning cycle (field or frame)
A transfer gate (not shown) for reading each signal, a vertical register 63 for vertically transferring the read signal charges in each horizontal scanning period (1H), and an electrical connection to one end of each vertical register And a horizontal register 64 for transferring the signal charges in the horizontal direction, and the horizontal register 64
And a charge detection circuit 65 for sequentially converting the signal charges from the above into a voltage signal. A buffer amplifier 66 that performs impedance conversion is connected to the outside of the image sensor 61 in the vicinity of the charge detection circuit 65 to prevent external noise from entering. The amplitude modulation signal from the buffer amplifier 66 is set to the reference voltage by the clamp circuit 67, then only the charge detection period is sampled by the sample hold circuit 68, and then the high-order sideband component is removed by the low-pass filter 69. Converted to a normal analog signal. The analog signal is amplified by the amplifier 70 to have a specified amplitude and then input to the A / D converter 71 to be converted into a digital signal.

According to this circuit configuration, conversion from analog quantity to digital quantity is possible, but there are some problems. One of them is that the amplitude-modulated signal from the image sensor 61 is once converted into an analog signal and then A / D-converted, so that the reproduced image is affected by the clamp circuit 67, the sample hold circuit 68, and the low-pass filter 69. This is a point that is easy to be done. Of course, if the amplitude modulation signal from the image pickup device 61 is directly A / D converted, the influence of the characteristic deterioration in the external circuit is the least, and this is technically possible. In this case, since both the reference voltage level and the charge detection period have to be A / D converted, an operation of taking the difference between the two must be performed, resulting in an increase in circuit scale and an increase in the price of parts used, resulting in a television camera or the like. It is not suitable for small-scale devices.

The second problem is that since the image pickup device 61 is an analog device, a unique analog technology must be used for driving and signal processing, which is difficult for a digital circuit engineer to be familiar with. In order to solve this problem, it is desirable that the image pickup device 61 directly outputs a digital signal.

The third problem is that although recent A / D converters have been reduced in price and increased in speed, there are still problems such as power consumption and quantization accuracy, and they are applied to small-scale devices such as TV cameras. This is a difficult point to do.

(Object of the Invention) An object of the present invention is to solve the above-mentioned conventional problems and to realize a charge transfer type A which can be integrated with a charge transfer image pickup device or the like.
The purpose is to provide a / D converter.

(Structure of the Invention) According to the structure of the present invention, in the signal processing circuit for converting the output signal from the charge transfer element into a digital signal with N-bit resolution, the signal charge from the charge transfer element is transferred in one direction and A charge transfer delay line with a terminal having 2 ^N -1 stages of output means for nondestructively detecting a signal from each stage in the transfer direction, and 2 connected to each of the output means.
^N −1 analog comparator groups, reference voltage generating circuits for supplying different reference voltages to the analog comparator groups, and 2 ^N − for giving different delays to the output signals from the analog comparator groups. It is characterized by including one digital shift register group and an encoder for converting an output signal from each digital shift register group into an N-bit binary number.

(Example) Next, this invention is demonstrated using drawing. For simplicity of explanation, an A / D converter with a level resolution of 2 bits / sample which is integrated into a charge-coupled device will be described here.

FIG. 1 is a block diagram of a first embodiment of an A / D converter according to the present invention. In the figure, reference numerals 1 and 2 denote transfer electrodes of the charge-coupled device, to which transfer pulses φ ₁ and φ ₂ are applied, respectively. Floating electrodes 3, 4, 5 are installed between these transfer electrode pairs. Further, a drain 6 for absorbing a signal charge is provided at the end of each transfer electrode pair, and constitutes a delay line 7 with a terminal as a whole. The delay line 7 with terminals is coupled at a charge level to the charge-coupled image sensor and the output section of the delay line. Therefore, the signal charges transferred from the direction of the arrow 8 are transferred through the delay line with terminal 7 and, at the same time, are nondestructively detected by the floating electrodes 3, 4 and 5, and the analog comparators 9 and 10 are detected. , 11 are applied as signal voltages to the respective signal terminals.

On the other hand, different reference voltages divided by the resistors 12, 13, 14, 15 having the same resistance value are applied to the reference voltage terminals of the analog comparators 9, 10, 11. That is, the main reference voltage applied to the terminal 16 is 3V _R / 4, V _R /
Voltage of 2, V _R / 4 is applied.

Here, the operation of the analog comparator 9 will be described. If V _S> 3V _R / 4 the relationship between the signal voltage V _S and the reference voltage 3V _R / 4, which is detected by the floating electrode 3 is satisfied, the output C1 becomes high level "1". Also V
_{When the} relationship of _S <3V _R / 4 is established, the low level becomes "0". Operation of other analog comparators 10, 11 also differ only reference voltages _{V R / 2, V R /} 4, is exactly the same in later. Therefore, the respective outputs C1, C of the analog comparators 9, 10, 11 with respect to changes in the signal voltage V _s
The states of 2 and C3 are as shown in FIG. That is, when V _S > 3V _R / 4, all of C1, C2 and C3 are high level “1”, and when 3V _R / 4> V _S > V _R / 2, C2 and C3 are high level “1”, V _R / 2> V _S > V _R /
4 when C3 only a high level "1", all V _R / 4> V For _S C1, C2, C3 is at low level "0".

Next, the digital signals output from the analog comparators 9, 10, 11 are applied to the digital shift registers 17, 18, 19 having different delay times, respectively. This is because the detection of the same signal charge is delayed by one clock cycle in the order of the floating electrodes 3 → 4 → 5, as is apparent from the operation of the delay line with terminal 7. By operating the digital shift registers 17, 18 and 19 in the same clock cycle as the terminal-equipped delay line 7 and selecting the respective delay times of 3, 2, and 1 clock cycle, the above-mentioned delay is compensated. Finally, the digital signal whose time has been adjusted by the digital shift registers 17, 18 and 19 is input to the encoder 20 where it is converted into a binary number of 2 bits D1 and D2 as shown in FIG.

As is clear from the above description, the A / D according to the present invention
The converter is very fast because it operates with the same clock as the charge coupled device. Also, the analog comparators 9, 10, 1
Since the 1, digital shift registers 17, 18, and 19 and the encoder 20 can be manufactured by the same semiconductor process technology as that of the charge-coupled device, the charge-coupled device can be easily integrated on-chip.

FIG. 3 shows a circuit diagram of an example of the analog comparator used in FIG. In the figure, 21, 22, 23, 24,
Reference numeral 25 is a MOS transistor manufactured by the same process as that of the charge coupled device, and reference numeral 26 is a buffer amplifier composed of a MOS transistor. Transistor 2 here
The signal voltage V _S and the reference voltage V _S are applied to the gates 2 and 23, respectively.
_r is applied, and the comparison pulse φ ₀ is applied to the gate of the transistor 21. The operation of this circuit is V _S > V
_In the case of _r , when the transistor 21 is turned on by the comparison pulse φ ₀ , the transistor 22 is turned on and the node 2
The voltage of 7 goes up. At this time, since the node 27 is connected to the gate of the transistor 25, 25 is turned on and the voltage of the node 28 drops. Node 28 is transistor 24
Since it is connected to the gate of the transistor 24, the transistor 24 is turned off and the voltage of the node 27 further rises. Due to this positive feedback action, the voltage of the node 27 is instantaneously changed to the power supply voltage V _D.
Therefore, the buffer amplifier 26 outputs a high level. Also in the case of V _S <V _r , the voltage of the node 27 instantaneously becomes a value close to the ground potential due to the similar positive feedback action, and the buffer amplifier 26 outputs a low level.

FIG. 4 is a block diagram of a second embodiment of the present invention, in which the same numbers as in FIG. 1 indicate the same components. The feature of this embodiment is that the reference voltage applied to the analog comparators 9, 10, 11 is generated by the terminal weighting circuits 30, 31, 32 composed of MNOS transistors or the like.
If the weighting factors of the terminal weighting circuits 30, 31, and 32 are selected to be 3/4, 1/2, and 1/4, the reference voltage terminals of the analog comparators 9, 10, and 11 are 3 V _R /, respectively.
4, the voltage of _{V R / 2, V R /} 4 is applied. Therefore, the same operation as that of the embodiment shown in FIG. 1 is possible.

FIG. 5 is a block diagram of a third embodiment of the present invention, in which the same numbers as in FIG. 1 indicate the same components. A feature of the present embodiment is that the reference voltage applied to the analog comparators 9, 10, 11 is generated by the split electrode type charge coupled device 40. In the figure, reference numerals 41 and 42 denote transfer electrodes, to which the same transfer pulses φ ₁ and φ _{2 as} those of the delay line with terminal 7 are applied. Further, split electrodes 43, 44, 45 are installed between the transfer electrode pairs and connected to the reference voltage terminals of the analog comparators 9, 10, 11, respectively. At one end of these transfer electrode pairs, an input diode 46 and an input gate 47.
48 is provided, and the drain 49 for absorbing the reference charge is provided at the other end. In addition, the transfer electrode 4
The electrode areas of 1, 42 and the electrode areas of the divided electrodes 43, 44, 45 before division are selected to be equal to the electrode areas of the transfer electrodes 1, 2 and the floating electrodes 3, 4, 5, respectively. Further, the electrode area of the divided electrodes 43, 44, 45 is
They are selected to be 3/4, 1/2, and 1/4, respectively, before division.

In the operation of this A / D converter, first, the reference charge is injected using the input diode 46 and the input gates 47 and 48. The size of this reference charge is usually selected to be equal to the maximum charge amount handled by the delay line 7 with a terminal. Therefore, split electrode 4
The magnitudes of the charges nondestructively detected by 3, 44, and 45 are 3/4, 1/2, and 1/4 of the maximum charges detected by the floating electrodes 3, 4, and 5, respectively. An appropriate reference voltage can be applied to the devices 9, 10, 11. As described above, in this embodiment, since the signal charge in the charge coupled device is directly compared with the reference charge, the quantization error due to the change of the dark current is the smallest.

(Effects of the Invention) As described above, according to the present invention, it is possible to obtain a charge transfer type A / D converter which can be integrated with a charge transfer image pickup device or the like and can be operated at high speed.

In the embodiment of the present invention, the level resolution is 2 bits /
Although only the sample A / D converter has been described, the N bit / sample A / D converter also includes an analog comparator or the like.
By preparing ^N- 1 pieces, it is possible to realize with a similar configuration.

[Brief description of drawings]

1 is a block diagram of a first embodiment of a charge transfer type A / D converter according to the present invention, FIG. 2 is an output level diagram for explaining the operation of the A / D converter of FIG. 1, and FIG. Is a circuit diagram of an example of an analog comparator which is made on-chip in FIG. 1, FIG.
FIG. 5 is a block diagram of second and third embodiments of the present invention, and FIG. 6 is a block diagram showing a conventional A / D conversion circuit configuration. In the figure, 1, 2, 47, 48 ... Transfer electrodes, 3-5 ... Floating electrodes, 7 ... Delay lines with terminals, 9-11 ... Analog comparators, 17-19 ... Digital shift registers,
20 ... Encoder, 30-32 ... Terminal weighting circuit, 43-
45 ... Divided electrodes, 61 ... Charge-coupled imaging device, 71
... A / D converter.

Claims (1)

[Claims] 1. A signal processing circuit for converting an output signal from a charge transfer element into a digital signal with N-bit resolution, transferring the signal charge from the charge transfer element in one direction and from each stage in this transfer direction. 2 ^N −1 stage output means for non-destructively detecting the signal of N.sub.1 and a charge transfer delay line with a terminal, and 2 ^N − connected to each of the output means.
One analog comparator group, a reference voltage generating circuit for supplying a different reference voltage to each analog comparator group, and 2 ^N -1 units for giving different delays to the output signals from each analog comparator group. An encoder for converting an output signal from the group of digital shift registers of the above into an N-bit binary number.