JPH0516204B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a low-cost FM detection circuit used in, for example, FM receivers and audio multiplex televisions.

Conventional configuration and its problems Conventional FM detection circuits include quatrachia detection,
There are methods such as PLL detection, but all of these are analog detection methods and have a filter section that occupies a relatively large volume, and because they are analog, there is a limit to the degree of integration even if the circuit section is integrated into an IC. Ta. Furthermore, there were problems such as a large number of adjustment points and an increase in cost.

Purpose of the Invention The present invention solves the above-mentioned conventional drawbacks, and uses digital processing to eliminate filters, etc.
The purpose is to provide an FM detection circuit that can be integrated into an IC, reduce costs, and easily connect to other digital equipment.

Structure of the Invention In order to achieve the above object, the FM detection circuit of the present invention detects a rough zero crossing point by reversing the polarity of data obtained by sampling a frequency modulated signal at a sampling frequency s. s> between two adjacent data including a zero crossing detected by the detector and the zero crossing detector.
An arithmetic circuit that calculates a more accurate zero-crossing time by reversing the polarity of data obtained by linear interpolation at an interpolation frequency i, and a unit that outputs a pulse of a constant width from the zero-crossing time determined by this arithmetic circuit. This configuration includes a stable oscillator and a low-pass filter that filters the output of this monostable oscillator.

DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, 1 is an input terminal for sampled data, 2 is a first delay device that delays data by the sampling period, and 3 is data input from input terminal 1 from the output data of the first delay device 2. 4 is the first subtractor 3
A divider that divides the output of the divider 4 by the ratio of the interpolation frequency to the sampling frequency, 5 and 6 are adders and a second delay device that add the output of the divider 4 every interpolation period, and 7 is a circuit other than zero crossings. 8 is a second subtracter that subtracts the output of the adder 5 from the output of the first delay device 2; 9 is the second a third delay device 1 that delays the output data of the subtracter 8 by an interpolation period;
0 is a second zero-crossing detector that detects polarity reversal, that is, zero-crossing, by the outputs of the second subtracter 8 and third delay device 9, and 11 is the output of the second zero-crossing detector 10. 12 is a digital low-pass filter that low-pass filters the output of the monostable oscillator 11, and 13 is an output terminal.

Next, the operation will be explained with reference to FIG. The first zero crossing detection is performed by checking the data Xn input from the input terminal 1 and the most significant (sign) bit of the previous data Xn-1 delayed by one sampling period by the first delay device 2. The zero crossing is detected by the device 7. At the same time, the first subtractor 3 obtains new data Y such that Y=Xn-1-Xn. Next, the data Y is divided by the ratio m between the interpolation frequency and the sampling frequency by the divider 4 to obtain data Y' such that Y'=(Xn-1-Xn)/m. Next, data Y′ is added to adder 5
and the second delay device 6 in order at the interpolation period to obtain data Y'' of Y''=(Xn-1-Xn)t/m. Here, t is the number of additions of data Y'. Next, the data is
Subtract data Y'' from Xn-1 to obtain (t) = Xn-1-(Xn-1-Xn)t/m. Output data (t) is data Xn, Xn
-1 is obtained by linear interpolation, and by checking the polarity of data (t), a more accurate zero-crossing time can be obtained. From the zero-crossing time determined as above, the monostable oscillator 11 outputs a pulse for a certain period of time, the low-pass filter (integrator) 12 performs low-pass filtering, and the output terminal 13 outputs a demodulated signal. Take out. Note that a specific circuit example is shown in FIG. In FIG. 3, i is the interpolation frequency and s is the sampling frequency.

In this way, FM detection can be configured entirely with digital circuits, making it possible to use highly integrated ICs, reducing the number of adjustment points, simplifying the adjustment method, etc., and reducing costs. can.

Effects of the Invention As explained above, according to the present invention, it is possible to digitize the FM detection circuit, increase the integration level of the IC, improve reliability, and reduce the number of adjustment points.
It is possible to reduce the cost of the detection circuit.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an FM detection circuit according to an embodiment of the present invention, Fig. 2 is an explanatory diagram of the operation of the FM detection circuit, and Fig. 3 is a circuit block diagram showing a specific example of the configuration of the FM detection circuit. be. 2, 6, 9... Delay device, 3, 8... Subtractor, 4... Divider, 5... Adder, 7, 10... Zero crossing detector, 1
1... Monostable oscillator, 12... Low pass filter.

Claims (1)

[Claims] 1. A zero-crossing detector that detects rough zero-crossing points by reversing the polarity of data obtained by sampling a frequency-modulated signal at a sampling frequency s; An arithmetic circuit that calculates a more accurate zero-crossing time by reversing the polarity of the data obtained by performing linear interpolation between two adjacent data including the detected zero-crossing at an interpolation frequency i such that s>i. and a monostable oscillator that outputs a pulse of a constant width from the zero-crossing time determined by the arithmetic circuit, and a low-pass filter that filters the output data of the monostable oscillator. FM detection circuit.