JPH0518290B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a source follower type MOS analog amplifier circuit with a sample and hold function.

Prior Art and Problems When an output signal contains various types of noise, a sample hold is often used to extract the signal components. An example is shown in FIG. This circuit is
It is used in the output stage of a CCD (charge-coupled device), and the diode mark D indicates the output section of the CCD. This output section is the source of the MOS transistor.
It is a diffusion layer similar to the drain, and has a conductivity type opposite to that of the semiconductor substrate, so the substrate and the diffusion layer constitute a junction diode. This diffusion layer is connected to the power supply V _DD through a depletion type MOS transistor Q ₁ which normally has a high resistance and is turned on when the reset gate φ _R is input, thus making the diode reverse biased. Charges (electrons) transferred through the CCD channel, that is, the surface of the semiconductor substrate under the transfer electrode, enter the diffusion layer D, and change the potential of the diffusion layer (lower in this example). transistor
The connection part T between Q ₁ and CCD output part D becomes the output end,
The above potential change is taken out from the output terminal T.

The waveform of the voltage taken out from the output terminal T is shown in Figure 3a.
It has a shape like. The peak part of this waveform P ₁
is the transistor that receives the reset clock _φR .
This is because _Q1 is turned on, and at this time, the output section D is fixed to the potential of the power supply _VDD . When the reset clock φ _R leaves, that is, returns from the H (high) level to the L (low) level, the output terminal T is pulled down by the gate-source capacitance of the transistor _Q1 , and the potential of the output terminal T becomes a portion P. Slightly lower like ₂ .
Next, when the transferred charge enters the output section D, the potential at the output terminal T drops as shown in the section _P3 . These P ₂ ,
The level difference of P ₃ indicates the amount of charge transferred and therefore the magnitude of the signal.

The voltage at the output terminal T is outputted via a two-stage source follower circuit. Enhancement type MOS transistors Q ₂ and Q ₃ constitute a first source follower circuit, and transistors Q ₅ and Q ₇ constitute a second source follower circuit. Transistors Q ₃ and Q ₇ serve as load resistances for the source follower, and their resistance values are determined by the bias voltage generation circuit.
It is determined appropriately by the voltage given by Q ₈ and Q ₉ . The MOS transistors Q ₈ and Q ₉ of the bias voltage generation circuit are enhancement type, and have their gates connected to their drains, and generate a voltage by dividing the voltage of the power supply V _DD from the series connection point C (V _SS is the ground level). is applied to the gates of transistors Q ₃ and Q ₇ . Q ₄ connects the output terminal A of the first source follower to the input terminal of the second source follower, that is, the transistor
This is a coupling MOS transistor connected to the gate of _Q6 , and has a signal sampling function. _Q5 is also MOS
The transistor is inserted into the modulation circuit of transistors _Q3 and _Q7 , but this is added in the present invention, and in the conventional circuit, this part is directly connected. The output end of this two-stage source follower is B.

As is well known, a source follower circuit has a gain of 1 or less, but is often used for impedance conversion, and this is also the case in this example. Output end A of the first source follower
The voltage is similar to the voltage at the output terminal T of the CCD (slightly lower in level), and therefore has a waveform as shown in FIG. 3a. When a sample and hold signal S/H as shown in Fig. 3d is applied to the gate of transistor _Q4 , the potential of part _P3 of the output waveform (the potential of output terminal T when the transferred charge is input to CCD output section D) ) is applied to the next-stage source follower, and the voltage Vout at the output terminal B becomes as shown in FIG. 3b. That is, when the sample and hold signal S/H, which is a narrow pulse, is applied, the transistor _Q4 is turned on for a period corresponding to the pulse width, transmitting the potential of the output terminal A to the gate of the transistor _Q6 , and when the signal S/H disappears. Transistor Q ₄ is turned off, and the gate of transistor Q ₆ becomes floating and maintains a potential when signal S/H is applied. Therefore, the output voltage Vout becomes a concatenation of each of the input signal portions _P3 as shown.

However, there is a problem in that this output voltage Vout contains noise as shown by the dotted line. transistor
When a sample and hold signal S/H is applied to _Q4 as shown in Figure 3d, a voltage is applied to the signal circuit connecting the output terminal A and the gate of transistor _Q6 via the gate and source-drain capacitance of the transistor. This results in noise. Transistor _Q4 to avoid the generation of this noise voltage is as shown in the figure.
Gate electrodes for shielding on both sides of gate electrode G1
G ₂ and G ₃ are provided. The shielding gate electrodes G ₂ and G ₃ are actually integrated as shown in FIG. 2, and are connected to the power supply V _DD . In this way, the gate electrode G1 will be electrostatically shielded from the source region SR and drain region DR of the transistor, and a change in gate electrode potential will induce noise voltage in the source and drain regions SR and DR. Never. However, when the sample and hold signal S/H is applied to the gate electrode G1, charges are collected on the semiconductor substrate below the electrode to form a channel (the transistor is turned on), and when the signal S/H disappears, the channel is closed. The constituent charges are dispersed and the channel disappears (the transistor turns off),
In this way, the application and disappearance of the signal S/H causes movement of charges, and this movement of charges causes the generation of noise voltage. The voltage generated by this inflow and outflow of charges is the voltage shown by the dotted line in FIG. 3b, and is called feed-through noise. Eliminating feedthrough noise is extremely difficult. For example, since this voltage is generated by the inflow and outflow of charge, it is possible to reduce the amount of charge by reducing the channel width, but this would reduce the gm of the transistor, so the sample and hold signal S/ There is a problem that the H pulse width margin deteriorates.

Purpose of the Invention The present invention has been made in view of the above points, and it can be used without causing problems such as the GM of the transistor.
This is intended to reduce feedthrough noise.

Structure of the Invention The present invention provides an analog amplifier circuit provided with a MOS source follower that receives an input signal through a first MOS transistor that is turned on and off by a sample and hold signal, and has a second MOS transistor as a load resistance. Provide a third MOS transistor that can add
This third MOS transistor is connected to the second MOS transistor.
Connecting the gates of the transistors to the first
The present invention is characterized in that the same type of voltage as the noise voltage generated when the MOS transistor is turned on and off by the sample-and-hold signal is applied to the gate of the second MOS transistor, and this will be explained next with reference to examples. .

Embodiments of the Invention In the present invention, as shown in FIG. 1, a transistor _{Q5 having the same structure as the sampling transistor Q4 is} inserted into the gate circuit of _the source follower load transistors Q3 and _Q7 . A sample and hold signal S/H is also applied to the gate electrode G5 of this transistor _Q5 , and a power supply _VDD is applied to the shielding gate electrodes _G6 and _G7 .
Apply voltage. In this way, the charge inflow and outflow caused by the application and disappearance of the sample hold signal S/H also occurs in the transistor _Q5 , and the voltage generated thereby increases the gate voltages of the transistors _Q3 and _Q7 . Figure 3c shows transistors Q ₃ and Q ₇
Indicates the gate voltage of When the gate voltage increases, the resistance of transistors Q ₃ and Q ₇ decreases, and the dotted line portion of the output Vout, that is, the feed-through noise is removed. Of course,
To completely eliminate the gain of transistors Q ₃ and Q ₇ ,
It is necessary to appropriately select the size of transistor _Q5 , taking into account the size of transistor _Q4 , etc.

Feedthrough noise reduction using this method is independent of the size of transistor _Q4 ,
Since the same thing as the generation source is used as the cancellation source, reliable noise reduction can be expected.

Note that transistor _Q5 for feed-through noise cancellation is inserted in the circuit connecting the gate of transistor _Q3 to the gate of transistor _Q7 in the drawing, but the point is that the same noise voltage as _Q4 is generated in _Q5 . This can be added to the gate of transistor _Q7 , and the insertion point of _Q5 can be changed as appropriate as long as this function is not lost. The illustrated insertion position of Q ₅ is advantageous in terms of pattern layout. In addition, at the illustrated insertion position, the sample hold signal S/
When transistor Q ₅ is turned on and off by H, the gate of transistor Q ₃ is connected to bias voltage generating circuit Q ₈ ,
The output voltage of Q ₉ is sometimes applied and sometimes not, but since the gate has parasitic capacitance, it is held by this and the gate voltage of Q ₃ does not fluctuate greatly. Furthermore, the resistance of the transistors in the bias voltage generation circuits Q ₆ and Q ₉ is high, so even if the transistor Q ₅ generates feedthrough noise, it will be suppressed by the bias voltage generation circuits Q ₈ and Q ₉ . Never.

Effects of the Invention As explained above, according to the present invention, there is an advantage that feed-through noise can be reliably reduced without adversely affecting the GM of the sample-and-hold transistor.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is an explanatory diagram showing the main structure of a transistor, and FIG. 3 is a waveform diagram for explaining operation. In the drawing, S/H is a sample and hold signal, Q ₄ is a first MOS transistor, Q ₇ is a second MOS transistor, and Q ₅ is a third MOS transistor.

Claims (1)

[Claims] 1. A third MOS transistor is provided with an input signal through a first MOS transistor that is turned on and off by a sample-and-hold signal, and has a MOS source follower with a second MOS transistor as a load resistance, and to which the sample-and-hold signal is applied. and connecting this third MOS transistor to the gate of the second MOS transistor,
A MOS analog amplifier circuit characterized in that a voltage of the same type as a noise voltage generated when the first MOS transistor is turned on and off by a sample-and-hold signal is applied to the gate of the second MOS transistor.