JPH0518461B2 - - Google Patents
Info
- Publication number
- JPH0518461B2 JPH0518461B2 JP7697886A JP7697886A JPH0518461B2 JP H0518461 B2 JPH0518461 B2 JP H0518461B2 JP 7697886 A JP7697886 A JP 7697886A JP 7697886 A JP7697886 A JP 7697886A JP H0518461 B2 JPH0518461 B2 JP H0518461B2
- Authority
- JP
- Japan
- Prior art keywords
- pellet
- sheet
- pellets
- semiconductor
- present
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/40—Encapsulations, e.g. protective coatings characterised by their materials
- H10W74/47—Encapsulations, e.g. protective coatings characterised by their materials comprising organic materials, e.g. plastics or resins
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/015—Manufacture or treatment of bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07511—Treating the bonding area before connecting, e.g. by applying flux or cleaning
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/551—Materials of bond wires
- H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/931—Shapes of bond pads
- H10W72/932—Plan-view shape, i.e. in top view
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Wire Bonding (AREA)
- Die Bonding (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法に関し、特に半
導体ペレツト分離後の組立工程中におけるペレツ
トの表面保護方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for protecting the surface of semiconductor pellets during an assembly process after separation.
一般に半導体装置の製造は、ウエーハをダイシ
ングしてペレツトに分離後、ペレツト表面の外観
チエツクを行ない、不良ペレツトを除去し、良品
ペレツトをリードフレームのダイスステージにダ
イボンドし、電極部とリードフレームのインナー
リードの間を金属細線で接続したのち、樹脂ある
いはガラス等で封止している。
Generally, in the manufacture of semiconductor devices, after dicing a wafer and separating it into pellets, the appearance of the pellet surface is checked, defective pellets are removed, and the good pellets are die-bonded to the die stage of the lead frame, and the electrode parts and the inner surface of the lead frame are bonded. The leads are connected with thin metal wires and then sealed with resin or glass.
しかしながら、上記工程中、ペレツト表面は作
業環境中のごみや汚れ、あるいは機械からのご
み、汚れ、人間からのごみ、汚れのために、素子
に不具合が生じ、歩留の低下が恒常的に発生して
いる。
However, during the above process, the pellet surface is exposed to dust and dirt in the working environment, dust and dirt from machines, and dust and dirt from humans, which causes defects in the elements and a constant drop in yield. are doing.
本発明はこのような問題点に解決するためにな
されたもので、半導体ウエーハからペレツトに分
離後、ペレツトの電極パツド以外の表面に耐熱性
シートを貼り付け、ダイボンデイング及びワイヤ
ボンデイングを行なう。
The present invention was made to solve these problems, and after separating a semiconductor wafer into pellets, a heat-resistant sheet is attached to the surface of the pellets other than the electrode pads, and die bonding and wire bonding are performed.
次に本発明の実施例を図面を用いて説明する。 Next, embodiments of the present invention will be described using the drawings.
第１図ないし第４図は、本発明の一実施例を説
明するための工程順の側面図（第１図と第２図に
部分拡大平面図を含む）である。まず、第１図の
ように、ウエーハから個々の半導体ペレツトに分
離されたペレツト１は、エレクトロンシート３上
に適当な間隔で並べられている。各ペレツト１に
は、同図ｂの部分拡大平面図に示すように、ボン
デイングパツド２を有する。次に第２図ａ，ｂで
示すように、ペレツトサイズに応じて個片に切断
された耐熱性シート、例えばポリイミドフイルム
４を、シート押さえステージ５にて貼り付け治具
６により、ペレツト上の電極パツド部２を除く表
面に貼り付ける。次に第３図に示すように、ペレ
ツトをリードフレームのダイステージ８上に固着
する。さらに、第４図に示すように、電極パツド
部とリードフレームのインナーリード部９を金属
細線１０でボンデイングする。その後適当なシー
ト剥離機にてシートを剥離し、樹脂封止を行う。 1 to 4 are side views (partially enlarged plan views are included in FIGS. 1 and 2) of steps for explaining an embodiment of the present invention. First, as shown in FIG. 1, individual semiconductor pellets 1 separated from a wafer are arranged on an electron sheet 3 at appropriate intervals. Each pellet 1 has a bonding pad 2, as shown in the partially enlarged plan view of FIG. Next, as shown in FIGS. 2a and 2b, a heat-resistant sheet such as a polyimide film 4 cut into individual pieces according to the pellet size is attached to the electrodes on the pellet using a pasting jig 6 on a sheet holding stage 5. Paste it on the surface excluding the pad part 2. Next, as shown in FIG. 3, the pellet is fixed onto the die stage 8 of the lead frame. Furthermore, as shown in FIG. 4, the electrode pad portion and the inner lead portion 9 of the lead frame are bonded with a thin metal wire 10. Thereafter, the sheet is peeled off using a suitable sheet peeling machine, and resin sealing is performed.
本発明によれば、ペレツトは組立工程中、表面
の主要部分が保護されているため、作業環境中の
ごみや汚れの付着がなく、作業者による汚染もな
くなるため、素子の不具合は極端に減少する。又
シートとしてダイボンデイングやボンデイング温
度に耐え得る耐熱性シートを使用するので、シー
トによる不具合は生じない。なお、本発明の実施
例としてリードフレームを使用する場合を説明し
たが、ガラスケースあるいはセラミツクケースを
使用する場合も同様である。
According to the present invention, the main part of the surface of the pellet is protected during the assembly process, so there is no adhesion of dust or dirt in the working environment, and there is no contamination by workers, resulting in an extreme reduction in device defects. do. Furthermore, since a heat-resistant sheet that can withstand die bonding and bonding temperatures is used as the sheet, no defects will occur due to the sheet. Although the case where a lead frame is used has been described as an embodiment of the present invention, the same applies when a glass case or a ceramic case is used.
第１図ａ、第２図ａ、第３図および第４図は本
発明の一実施例を説明するための工程順の側面
図、第１図ｂおよび第２図ｂはそれぞれ、第１図
ａ、第２図ａに示す半導体ペレツトの部分拡大平
面図である。
１……半導体ペレツト、２……ボンデイングパ
ツド、３……エレクトロンシート、４……表面保
護シート、５……押さえステージ、６……押さえ
治具、８……ダイステージ、９……インナーリー
ド、１０……金属細線。
1a, 2a, 3 and 4 are side views of the process order for explaining one embodiment of the present invention, and FIGS. 1b and 2b are respectively the same as those shown in FIG. 2a is a partially enlarged plan view of the semiconductor pellet shown in FIG. 2a; FIG. 1... Semiconductor pellet, 2... Bonding pad, 3... Electron sheet, 4... Surface protection sheet, 5... Holding stage, 6... Holding jig, 8... Die stage, 9... Inner lead , 10... Fine metal wire.
Claims (1)
ペレツトの電極パツド以外の表面に耐熱性シート
を貼り付けた後、ダイボンデイング及びワイヤボ
ンデイングを行なうことを特徴とする半導体装置
の製造方法。1. A method for manufacturing a semiconductor device, which comprises separating a semiconductor wafer into pellets, pasting a heat-resistant sheet on the surface of each pellet other than the electrode pads, and then performing die bonding and wire bonding.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61076978A JPS62232934A (en) | 1986-04-02 | 1986-04-02 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61076978A JPS62232934A (en) | 1986-04-02 | 1986-04-02 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62232934A JPS62232934A (en) | 1987-10-13 |
| JPH0518461B2 true JPH0518461B2 (en) | 1993-03-12 |
Family
ID=13620870
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61076978A Granted JPS62232934A (en) | 1986-04-02 | 1986-04-02 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62232934A (en) |
-
1986
- 1986-04-02 JP JP61076978A patent/JPS62232934A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62232934A (en) | 1987-10-13 |
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