JPH0518512B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a synchronization separation circuit, and in particular to a synchronization separation circuit suitable for detecting only correct synchronization signals from among synchronization signals that have been incorrectly separated due to noise or the like. Regarding.

[Background of the invention]

Video signal processing devices such as television receivers and magnetic recording/reproducing devices perform signal processing based on synchronization signals included in video signals. Therefore, it is necessary to correctly separate the synchronization signal from the video signal.

Conventional synchronous separation circuits have been devised to reduce synchronous separation errors when separating synchronous signals, and such a circuit is disclosed in, for example, Japanese Patent Laid-Open No. 187078/1983. However, the S/N of the transmission signal
If an erroneous signal is separated from the synchronization signal due to noise due to deterioration or switching noise when switching heads in a helical scan type magnetic recording/playback device, it will cause a large disturbance to the signal processing using the synchronization signal. First, there is no mention of a method for removing erroneous signals.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a synchronization signal separation circuit that removes signals that are erroneously separated together with the synchronization signal due to noise, etc., and separates and outputs only the proper synchronization signal.

[Summary of the invention]

In order to achieve the above object, the present invention removes signals shorter than the regular synchronization signal time width τ ₀ . The leading edge of the separated synchronization signal containing the erroneous signal is delayed by a time τ ₁ which is a time Δτ shorter than the normal synchronization signal time width τ ₀ . Then, the separated synchronization signal is latched with the delayed synchronization signal. If a signal shorter than the time width τ ₁ among the separated signals is input, the signal is not output from the Ratsu circuit, and a synchronization signal with a regular time width τ ₀ longer than the time width τ ₁ is input. In this case, a signal is output from the Ratsu circuit. In the manner described above, erroneously separated signals are removed and only normal synchronization signals are detected.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 is a waveform diagram of each part.

In FIG. 1, 10 is the input terminal 20 of the video signal V, and the output terminal 30 is the output terminal of the regular synchronization signal SY which has been synchronously separated according to the present invention, and 30 is the output terminal for comparing the amplitudes using a conventionally known predetermined threshold value Vr to separate the synchronization signals. A synchronous separation circuit, 40 is a synchronous separation circuit of the present invention, 41, 4
3 is a rising edge operation monostable multicircuit, 42 is a D flip-flop, and 44 is an AND circuit.

The video signal V input from the terminal 10 contains noise N as shown in FIG. 2a. The noise is set to a predetermined threshold value Vr of the synchronous separation circuit 30 (Vr in FIG. 2a)
If the signal exceeds HS, it is mistakenly recognized as a synchronizing signal, and as shown in FIG.
The noise I mixed in and separated is output. The output signal of the synchronization separation circuit 30 is assumed to be SY'.

The signal SY' is input to the trigger input terminal T ₊₀ of the monostable multicircuit 41 and the data input terminal D of the D flip-flop 42.

The time width of the normal synchronized HS in the signal SY′ is τ ₀
The delay time of the monostable multicircuit 41 is also assumed to be τ ₁ . Then, the time constant of the monostable multicircuit 41 is set so that τ ₁ <τ ₀ . Monostable multi circuit 4
The output signal ' from output terminal ₀ of 1 is shown in Figure 2 c.
It becomes a negative polarity signal with a time width τ ₁ synchronized with the rising edge of the signal SY′ as shown in FIG. Signal ' is the clock input terminal CK of the D flip-flop circuit 42.
and is input to the T ₊₂ terminal of the monostable multicircuit 43.

On the other hand, a signal SY' is input to the terminal D of the D flip-flop circuit 42. Introduction regular synchronization
The case where HS (HS in FIG. 2b) is output from the synchronization separation circuit 30 will be explained. When the signal ' rises, SY' is still at a high level (hereinafter referred to as "H"), and the D flip-flop 42
Output signal SYG from output terminal Q ₁ (d in Figure 2)
continues or the state is reversed and becomes "H". Furthermore, the output signal G from the terminal _Q2 of the monostable multi-circuit 43 is as shown in FIG. 2e.
The signal is synchronized with the rising edge of DSY' and delayed by an arbitrary time. The signals SYG and G are input to the AND circuit 44, and the signal SY shown in FIG.
It is output from the AND circuit 44. The signal SY is the second
As can be seen from the waveform diagrams in Figures c and e, regular synchronization
HS is detected and delayed. and synchronous HS
is detected as synchronous HS′.

Next, a case where the noise N is mistakenly separated by the synchronization separation circuit 30 will be explained. The noise I mistakenly separated by the synchronization separation circuit 30 is generally the normal synchronization HS.
shorter than the time span. When the monostable multicircuit 41 is triggered by the separated noise I, as shown in FIG. ”, and the output signal of the D flip-flop 42
SYG reverses state or continues to be “L”. Therefore, the signal SY becomes "L", the AND circuit 44 is closed, and the erroneously separated noise I is removed.

In the above manner, signals shorter than the time τ ₁ are removed, and only the synchronized HS′ based on the regular synchronized HS can be separated, and the synchronized signals can be separated without being disturbed by noise. It is possible.

Next, another embodiment of the present invention will be described with reference to FIG. FIGS. 4 and 5 are waveform diagrams of each part.
Note that FIG. 3 has some parts common to FIG. 1, and the common parts are given the same reference numerals and detailed explanation thereof will be omitted.

In FIG. 3, 40′ synchronous separation circuit of the present invention;
42' is a D flip-flop. In FIG. 4, a to c are reprints of FIG. 11 a to c.

The video signal V input from the terminal 10 is input to the synchronization separation circuit 30. The output signal SY' of the synchronous separation circuit 30 is connected to the T ₊₀ terminal and D of the monostable multi-circuit 41.
It is input to the data input terminal D and reset input terminal R of the flip-flop 42'.

The output signal SY ₁ from the terminal Q ₁ of the D flip-flop 42' is similar to the embodiment shown in FIG.
SY' is latched at the rising edge of signal '. Therefore, in the regular synchronous HS part, “H”
However, the incorrectly separated noise I portion does not become "H" but remains "L". In the synchronous HS part, the D flip-flop 42' is reset at the trailing edge of the synchronous HS after a time Δτ, so the signal is
SY ₁ becomes the signal shown in FIG. 4d. In this way, the erroneously separated noise I is removed and only the synchronization HS' based on the normal synchronization HS is detected.

In addition, as shown in Figure 4d, the rising edge of signal SY ₁ contains information based on the leading edge of regular synchronization HS.
The falling edge of the signal SY ₁ contains information based on the trailing edge of the regular synchronization HS, and it is possible to detect information on either the leading edge or the trailing edge.

Above, using Fig. 4, we have explained that noise N can be separated when it exists far from the regular synchronization signal position.
The case where the HS exists near the HS will be explained using FIG.

FIG. 5a shows the video signal V. When the S/N of the video signal V is degraded, the noise N in the front porch X and back porch Y portions exceeds the threshold Vr of the synchronization separation circuit 30 and is likely to be separated as erroneous synchronization I. If the threshold value Vr of the synchronization separation circuit 30 is lowered in order to do this, the normal synchronization HS may not reach the reference potential Vr, and the synchronization signal may be missing. Further, even if the signals are separated, noise jitter occurs due to the influence of noise, resulting in phase fluctuation.
Therefore, the threshold value Vr cannot be lowered extremely.

Figure 5b shows the signal SY' when the S/N of the video signal V is degraded, the noise N is separated at the front porch X and the back porch Y, and the separated noise I is output near the synchronization HS. ing.

Figure 5e shows the monostable multicircuit 4 shown in Figure 3.
1 shows the signal ' when there is no retrigger function. When the signal I enters within the period τ ₁ from the leading edge of the synchronous HS, the monostable multicircuit 41 is triggered by the rising edge of the signal I, and the signal ′ becomes “L” and becomes “H” after the period τ ₁ . . Synchronous HS signal
Since DSY' reverses its state and becomes "H" within the "L" period, the monostable multi-circuit 41 is not triggered by the synchronous HS. Therefore, although the noise I is removed, the signal SY shown in FIG. 5d will output a wide synchronization HS' only in this case.

The leading edge of this wide synchronous HS' stores the information of the noise I, and the information at the leading edge of the synchronous HS is lost. However, D flip-flop 42 is synchronous.
Since it is reset at the trailing edge of the HS, the information on the trailing edge of the synchronous HS is stored in the trailing edge of the synchronous HS'.

Note that if there is a signal I on the back pouch Y, the noise I will be removed without any problem as explained in FIG.
is removed.

Figure 5e shows the monostable multicircuit 4 shown in Figure 3.
1 shows the signal ' when the retrigger function is provided. Even if noise I enters the front porch X, the monostable multicircuit 41 is retriggered at the rising edge of the synchronous HS, so the signal ' becomes "H" after a period τ ₁ from the rising edge of the synchronous HS.

Therefore, as shown in FIG. 5f, a signal HS' is output in which the noise I is removed and information based on the leading and trailing edges of the normal synchronizing signal HS is preserved.

As described above, even when the S/N of the video signal V is poor, the threshold value Vr of the synchronization separation circuit 30 is not lowered, and therefore the synchronization signal dropouts and phase fluctuations can be minimized, and Synchronization separation errors due to noise can be eliminated.

In the embodiment shown in Fig. 3, a monostable multi-circuit that delays the separated signal SY' in an analog manner was used as a delay circuit for the separated signal SY', but it is also possible to use a digital delay circuit such as a counter or a shift register. However, it does not depart from the spirit of the present invention.

FIG. 6 is a block diagram showing an embodiment in which the synchronization separation circuit of the present invention is applied to a segment recording type helical scan type magnetic recording and reproducing apparatus.

In FIG. 6, 100 is a segment recording type helical scan type recording and reproducing device, and 110 is a
FM demodulation circuit; 30 is the conventional synchronization separation circuit shown in FIGS. 1 and 3; 120 is the conventional synchronous separation circuit shown in FIGS.
The synchronous separation circuit of the present invention shown in FIG. 40', 130
1 is a time axis correction device, and 140 is an output terminal for a video signal.

The signal reproduced by the device 100 is sent to the FM demodulation circuit 1
FM demodulation is performed at 10. The FM demodulated video signal contains large spike-like noises caused by the discontinuity of the FM signal when switching heads, as well as noises generated in the tape head system. The FM demodulated signal containing this noise is input to a conventional synchronization separation circuit 30.

The conventional synchronization separation circuit 30 mistakenly separates head switching noise and noise generated in the tape/head system from the synchronization signal. This noisy synchronization signal is further input to the synchronization separation circuit 120 of the present invention. In the synchronization separation circuit 120 of the present invention, pulses having a duration less than the regular synchronization signal time width are removed, and only the regular synchronization signal is separated and output.

In a segment recording type magnetic recording/reproducing apparatus, the skew distortion that occurs when switching heads appears on the screen, so there is no need to remove the skew distortion. In order to remove skew distortion, time-base processing is performed using, for example, a sampling signal whose phase is instantaneously synchronized with a synchronization signal. A time axis correction device is required. 130 is a time axis correction device having this function.

The synchronization separation circuit 120 according to the present invention removes signals mixed with noise and the like, and only the regular synchronization signal is input to the time base correction device 130. The signal from which skew distortion and jitter have been removed is terminal 1.
40.

In order to remove skew distortion, the time axis correction device 130 needs to instantly correct phase fluctuations in the video signal that occur when switching heads.
It is controlled by feed forward control. Therefore, it is weak against noise and responds to signals other than the regular synchronization signal. In such a case, the synchronization separation circuit according to the present invention becomes essential, and the stability of the signal processing device is significantly improved.

〔Effect of the invention〕

According to the present invention, it is possible to remove the erroneously separated signal along with the regular synchronization signal with a simple circuit,
The reliability of the synchronization separation circuit can be significantly improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram 2 showing one embodiment of the present invention.
3 is a block diagram showing another embodiment of the present invention. FIGS. 4 and 5 are waveform diagrams for explaining the operation. FIG. 6 is a synchronization according to the present invention. FIG. 2 is a block diagram showing an embodiment in which the separation circuit is applied to a helical scan type magnetic recording and reproducing apparatus using a segment recording method. 40, 40'... Synchronous separation circuit, 41, 43... Monostable multicircuit, 42, 42' D flip-flop.

Claims (1)

[Claims] 1. Separation means for separating a synchronization signal from an input video signal; delay means for delaying the synchronization signal by a time shorter than the time width of the separated synchronization signal; latching means for latching the separated synchronous signal based on the latching means; and reset means for resetting the latching means in a period other than the separated synchronous signal, and for obtaining a synchronous separated output from the output of the latching means. A synchronous separation circuit characterized by: 2. The synchronization separation circuit according to claim 1, wherein the delay means has a retrigger function. 3 separation means for separating a synchronization signal from an input video signal; first delay means for delaying the synchronization signal by a time shorter than the time width of the separated synchronization signal; and separating the synchronization signal based on the delayed synchronization signal. latching means for latching the synchronization signal that has been output, and a second delaying means for delaying the output signal of the first delaying means.
and gate means for gating the output signal of the latch means with the output signal of the second delay means, and a synchronous separated output is obtained from the output of the gate means. Synchronous separation circuit. 4. The synchronization separation circuit according to claim 3, wherein the first delay means has a retrigger function.