JPH0573313B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a vertical synchronization separation circuit, and in particular, detects only the correct vertical synchronization signal among the vertical synchronization signals that have been incorrectly separated due to missing video signals, noise, etc. The present invention relates to a vertical synchronization separation circuit suitable for

[Background of the invention]

Video signal processing devices such as television receivers and magnetic recording and reproducing devices perform signal processing based on synchronization signals included in video signals. Therefore,
It is necessary to correctly separate the synchronization signal from the video signal.

In a conventional vertical synchronization separation circuit, a composite synchronization signal is separated from a video signal by comparing amplitudes using a predetermined threshold value, and then the vertical synchronization signal is separated using a low-pass filter. As a method for reducing synchronization separation errors when a composite synchronization signal is separated by a synchronization separation circuit, there is a circuit disclosed in, for example, Japanese Patent Laid-Open No. 187078/1983. However, due to dropouts in the video signal, disturbance of the video signal due to unstable operation of the servo system at the start of playback in a helical scan type magnetic recording/playback device, and noise due to S/N deterioration of the video signal, the erroneous signal may be vertically There is no mention of a method for removing the erroneous signal, even though it causes great disturbance to signal processing using the vertical synchronization signal if it is separated along with the synchronization signal.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a vertical synchronization signal separation circuit that removes signals that are erroneously separated along with the vertical synchronization signal due to video signal loss or noise, and separates and outputs only the normal vertical synchronization signal. It is in.

[Summary of the invention]

In order to achieve the above object, the present invention removes signals shorter than the regular vertical synchronization signal time width τ ₀ . Furthermore, the gate circuit also removes erroneously separated signals other than those in the vicinity of the regular vertical synchronizing signal.

The leading edge of the separated vertical synchronization signal containing the erroneous signal is separated by a time Δτ ₀ than the normal vertical synchronization signal time width τ ₀ .
It is delayed for a short time τ ₁ and the separated vertical synchronization signal is latched with this delayed vertical synchronization signal. As a result, among the separated vertical synchronization signals including erroneous signals, signals with a time width shorter than time width τ ₁ are not output from the latch circuit, and signals with a normal time width τ ₀ longer than time width τ ₁ are output from the latch circuit. is output from the latch circuit.

Further, in a helical scan type magnetic recording/reproducing apparatus, the vertical synchronization signal and the head switching signal are phase-synchronized. A signal with a time width Δτ 1 + τ ₀ + Δτ ₂ where the leading edge is the time Δτ ₁ before the leading edge of the regular vertical synchronization signal, and the trailing edge is the time Δτ ₂ after the trailing edge of the regular _vertical synchronization signal. Generated from the head switching signal. This signal gates the separated vertical synchronization signal containing the erroneous signal. Among the separated signals, the signals input while the gate is closed are not output, and the signals input while the gate is open are output. Since the regular vertical synchronization signal is input while the gate is open, it is output from the gate circuit.

In this way, the erroneously separated signals are removed and only the normal vertical synchronization signal is detected.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIG. FIG. 2 is a waveform diagram of each part.

In FIG. 1, 10 is an input terminal for a video signal V, 20 is an output terminal for a normal vertical synchronizing signal SY which has been synchronously separated according to the present invention, and 30 is a composite synchronous signal whose amplitude is compared using a conventionally known predetermined threshold value Vr. A vertical synchronization separation circuit 40, which separates the vertical synchronization signal using a low-pass filter after separating the vertical synchronization signals, is a vertical synchronization separation circuit of the present invention, and a monostable multicircuit 42 with a rising edge operation 41 is a D flip-flop.

The video signal V input from the terminal 10 includes noise N and video signal loss L, as shown in FIG. 2a. Due to noise or loss of the video signal, the video signal remains at a predetermined threshold value Vr (Vr in FIG. 2a) for a time longer than the time constant of the low-pass filter in the vertical synchronization separation circuit 30.
If it is below, it will be mistaken as a vertical synchronization signal, and as shown in Figure 2b
As shown in FIG. 2, the vertical synchronization separation circuit 30 outputs the noise I mixed into the normal vertical synchronization signal VS and separated.

The output signal SY' of the vertical synchronization separation circuit 30 is input to the trigger input terminal T+ ₀ of the monostable multi-circuit 41, the data input terminal D and the reset input terminal R of the D flip-flop 42.

In the signal SY', the time width of the regular vertical synchronizing signal VS is set to τ ₀ , and the delay time of the monostable multi-circuit 41 is set to τ ₁ . Then, the time constant of the monostable multicircuit 41 is set so that τ ₁ <τ ₀ . The output signal DSY' from the output terminal Q0 of the monostable multi-circuit ₄₁ becomes a negative polarity signal with a time width _τ1 synchronized with the rising edge of the signal SY', as shown in FIG. 2c. signal
DSY' is input to the clock input terminal CK of the D flip-flop circuit 42. On the other hand, the signal SY' is input to the terminal D of the D flip-flop circuit 42.

When the regular vertical synchronization signal VS (VS in Fig. 2b) is output from the vertical synchronization separation circuit 30, the signal
When DSY′ rises, SY′ is at a high level (hereinafter referred to as “H”).
), and the signal SY′ is the signal
DSY' is latched, and the output signal SY from the output terminal _Q1 of the D flip-flop 42 is inverted and becomes "H". After a time .DELTA..tau., the D flip-flop 42 is reset at the trailing edge of the vertical synchronization VS, so that the signal SY becomes the signal shown in FIG. 2d. signal
SY is the detected regular vertical synchronizing signal VS, and the vertical synchronizing signal VS is detected as the vertical synchronizing signal VS.

Next, a case where the noise N or the video signal loss L is mistakenly separated by the vertical synchronization separation circuit 30 will be described. The noise I erroneously separated by the vertical synchronization separation circuit 30 is generally shorter than the time width of the normal vertical synchronization signal VS. When the monostable multicircuit 41 is triggered by the separated noise I, the separated noise I has already reached a low level (hereinafter referred to as The signal SY' is not latched by the signal DSY', and the output signal SY from the output terminal _Q1 of the D flip-flop 42 remains at "L".
Therefore, the erroneously isolated noise I is removed.

In the above manner, signals shorter than time τ ₁ are removed, and the regular vertical synchronizing signal VS is separated and output as the vertical synchronizing signal VS' based on this signal, and the vertical synchronizing signal is not disturbed by noise or video signal loss. It is possible to separate the synchronization signal.

Next, another embodiment of the present invention will be described with reference to FIG. FIG. 4 is a waveform diagram of each part. Note that FIG. 3 has some parts in common with FIG. 1, and the common parts are given the same reference numerals and detailed explanation thereof will be omitted.

In FIG. 3, 21 is an output terminal for the normal vertical synchronizing signal GSY, which is synchronously separated according to the present invention;
0 is a head switching signal input terminal of a helical scan type magnetic recording/reproducing device, 60 is a circuit for detecting both ends of the head switching signal, 40' is a vertical synchronization separation circuit of the present invention, and 43 is a monostable multi-circuit with falling edge operation. , 44 is a monostable multi-circuit with rising edge operation, and 45 is an AND circuit. In FIG. 4, a and b are reprints of a and b in FIG. 2.

The video signal V input from the terminal 10 is input to the vertical synchronization separation circuit 30. As shown in FIG. 4b and c, the output signal from the vertical synchronization separation circuit 30
Of SY', the normal vertical synchronizing signal VS is synchronized with the head switching signal SW (signal shown in FIG. 4c). The time between the leading edge or trailing edge of the head switching signal SW and the leading edge of the regular vertical synchronizing signal VS is defined as _τ1 . The output signal SY' from the vertical synchronization separation circuit 30 is input to an AND circuit 45.

On the other hand, the head switching signal SW input from the terminal 50 is input to the both edge detection circuit 60. The output signal ESW from the both edge detection circuit 60 is shown in FIG.
As shown in FIG. 2, the signal has a time width τ ₂ that is synchronized with both edges of the head switching signal SW. The time width τ ₂ is shorter than 1/2 period of the head switching signal SW. The signal ESW is input to the trigger input terminal T _-3 of the monostable multi-circuit 43. Let the delay time of the monostable multi-circuit 43 be τ ₃ . Then, the time constant of the monostable multi-circuit 43 is set so that τ ₃ <τ ₁ . The output signal DESW from the output terminal Q3 of the monostable multi-circuit ₄₃ becomes a signal with a time width _τ3 synchronized with the falling edge of the signal ESW, as shown in FIG. 4e. signal DESW
is input to the trigger input terminal T ₊₄ of the monostable multi-circuit 44. Letting the delay time of the monostable multi-circuit 44 be τ ₄ , the time constant of the monostable multi-circuit 44 is set so that τ ₀ +τ ₁ <τ ₃ +τ ₄ . The output signal DG from the output terminal Q ₄ of the monostable multi-circuit 44 becomes a signal with a time width τ ₄ synchronized with the rising edge of the signal DESW, as shown in FIG. 4f. i.e. the signal
DG rises a time Δτ ₁ before the rising edge of the normal vertical synchronization signal VS, and a time Δτ ₂ before the falling edge of the normal vertical synchronization signal VS.
This becomes a signal that falls later. Signal DG is AND circuit 45
is input.

The AND circuit 45 receives a signal SY' (signal shown in FIG. 4b) and a signal DG (signal shown in FIG. 4f).
The regular vertical synchronization signal VS is sent to the vertical synchronization separation circuit 30
As can be seen from Figure 4b and f, when the normal vertical synchronizing signal VS is "H",
Signal DG is also at "H". Therefore, the normal vertical synchronizing signal VS is output from the output terminal 21 of the AND circuit 45 as shown in FIG. 4g. Noise I
is mistakenly separated by the vertical synchronization separation circuit 30, when the noise I is "H", the signal DG becomes "L", the AND circuit 45 is closed, and the incorrectly separated noise I is removed. Ru.

As described above, by using the synchronization relationship between the head switching signal SW and the regular vertical synchronization signal VS, it is possible to remove the noise I that is erroneously separated during the period when the signal DG is "L", and the regular vertical synchronization signal VS can be removed. Only the signal VS can be separated.

The embodiment shown in FIG. 3 is a helical scan type magnetic recording and reproducing apparatus that records one vertical scanning line period on one track. In the case of a segment recording type helical scan type magnetic recording/reproducing device, multiple head switching points occur within one vertical scanning period, but the gate signal DG synchronizes with the edge of the head switching signal SW immediately before the regular vertical synchronizing signal VS. By gating the separated vertical sync signal containing the erroneous signal at VS
can only be detected. Therefore, the application of the present invention to a helical scan type magnetic recording/reproducing apparatus using a segment recording method does not depart from the gist of the present invention.

As described above, there is a method for removing signals with a time width shorter than the regular vertical synchronization signal VS, and a method for using the separated vertical synchronization signal SY′ containing the erroneous signal as a gate using the gate signal DG synchronized with both edges of the head switching signal. Therefore, only the regular vertical synchronization signal VS can be detected. Furthermore, one embodiment of a vertical synchronization separation circuit that combines these two methods will be described with reference to the block diagram shown in FIG.

In FIG. 5, 10 is a video signal input terminal;
50 is an input terminal for a head switching signal; 30 is a conventional vertical synchronization separation circuit shown in FIGS. 1 and 3;
60 is a circuit for detecting both edges of the head switching signal shown in FIG. 3, 40' is a vertical synchronization separation circuit of the present invention shown in FIG. 3, and 40 is a vertical synchronization separation circuit of the present invention shown in FIG. The circuit 20 is an output terminal for a normal vertical synchronizing signal which is synchronously separated by the circuit according to the present invention.

The video signal inputted from the terminal 10 is synchronously separated by a conventional vertical sync separation circuit 30. Since the video signal input from the terminal 10 contains noise and video signal loss, the conventional vertical synchronization separation circuit 3
From 0, noise and video signal loss are mistakenly mistaken as synchronization signals and are separated and output together with the regular vertical synchronization signal. The separated vertical synchronization signal containing this erroneous signal is input to the vertical synchronization separation circuit 40' of the present invention. On the other hand, the head switching signal inputted from the terminal 50 is sent to the both edge detection circuit 60 of the head switching signal.
Both edges are detected, and this detection signal is input to the vertical synchronization separation circuit 40' of the present invention. In the vertical synchronization separation circuit 40' of the present invention, a gate signal synchronized with both edges of the head switching signal is generated from the detection signal on both edges of the head switching signal, and the vertical synchronization signal including the erroneous signal is gated with this gate signal. This separates the normal vertical synchronization signal and removes the erroneous signal during the period when the gate signal is "L".
Furthermore, the vertical synchronization signal gated by this gate signal is input to the vertical synchronization separation circuit 40 of the present invention. In the vertical synchronization separation circuit 40, pulses having a duration less than the regular vertical synchronization signal time width are removed, and only the regular vertical synchronization signal is separated and output.

In the embodiment shown in FIG. 5, a monostable circuit that delays in an analog manner is used as a delay circuit, but a digital delay circuit such as a counter or a shift register may also be used, which is outside the scope of the present invention. isn't it. Furthermore, in the embodiment shown in FIG. 5, a gate signal for gating the normal vertical synchronizing signal is generated from the head switching signal. but,
The gate signal can be generated in a similar manner using not only the head switching signal but also a signal representing the rotational phase of the rotary head, without departing from the spirit of the present invention.

In this way, among the incorrectly separated signals, it is possible to remove signals shorter than the time width τ ₀ of the regular vertical synchronization signal, and also remove incorrectly separated signals other than those in the vicinity of the normal vertical synchronization signal. can.

〔Effect of the invention〕

According to the present invention, it is possible to reliably remove a signal that is erroneously separated along with a normal vertical synchronization signal using a simple circuit, and the reliability of the vertical synchronization separation circuit can be significantly improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention;
2 is a waveform diagram for explaining the operation, FIG. 3 is a block diagram showing another embodiment of the present invention, FIG. 4 is a waveform diagram for explaining the operation, and FIG. 5 is the same as shown in FIG. 1. FIG. 4 is a block diagram showing an embodiment in which the embodiment and the embodiment shown in FIG. 3 are combined. 40, 40'...Vertical synchronization separation circuit, 41, 43,
44...monostable multi-circuit, 42...D flip-flop.

Claims (1)

[Claims] 1. A means for separating a vertical synchronizing signal contained therein from an input video signal, and a time width of the vertical synchronizing signal separated by the separating means as τ ₀ , and a time τ ₁ such that τ ₀ >τ ₁ . means for delaying the separated vertical synchronization signal; means for latching the separated vertical synchronization signal based on the delayed vertical synchronization signal that is an output signal of the delaying means; and separating the output of the latching means. 1. A vertical synchronization separation circuit, comprising: means for resetting at the trailing edge of a vertical synchronization signal which has been latched; and a vertical synchronization separation output is obtained from the output of said latching means. 2 Means for separating the vertical synchronizing signal contained in the input video signal; and the time width of the vertical synchronizing signal separated by the separating means being τ ₀ , and the time width of the vertical synchronizing signal separated by the separating means based on the signal representing the rotational phase of the rotating head. The time Δτ ₁ before the leading edge of the vertical synchronization signal is the leading edge,
means for generating a gate signal having a time width Δτ ₁ +τ ₀ +Δτ _{2 whose trailing edge is a time Δτ 2 after} the trailing edge of the separated vertical synchronization signal; gate means for outputting the separated vertical synchronization signal for only a period of ₁ +τ ₀ +Δτ ₂ ; means for delaying the vertical synchronization signal outputted from the gate means by a time τ ₁ ; and an output signal of the delaying means. It has means for latching the vertical synchronizing signal output from the gate means based on the delayed vertical synchronizing signal, and means for resetting the output of the latch means at the trailing edge of the vertical synchronizing signal output from the gate means. A vertical synchronization separation circuit characterized in that a vertical synchronization separation output is obtained from the output of the latch means.