JPH0519347B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an automatic fall back and a restore method, and in particular to an automatic equalization circuit for equalizing line distortion. The present invention relates to an automatic fallback and restoration method for automatically rolling back and restoring the transmission speed in data communication using a data modulation/demodulation device included in a part.

[Conventional technology]

Conventionally, when performing data communication using data transmission devices facing each other, if the line deteriorates and errors increase and normal data transmission is no longer possible, it is necessary to ensure the minimum level of transmission as a system. , reduce the transmission speed (fallback),
In response to line deterioration factors, a method is used to increase the error margin and ensure data transmission, although the speed will be slower.

Furthermore, if the deterioration of the line improves over time, the original transmission speed is restored and normal data transmission is performed, so-called restoration.
will be done.

At this time, first, regarding the former fallback, the limit of normal data transmission is determined, and the determination level is set in advance inside the data transmission device, and when the received signal reaches that value, the transmission speed of transmission and reception is It is possible to perform a so-called automatic fallback, which reduces the Here, whether or not the received signal has deteriorated to a certain determination level due to line deterioration can be easily determined based on the degree of spread of the received signal eye.

Next, regarding the latter restoration, after a period of time has passed after the fallback, the cause of the line deterioration has been improved (restored) and the original transmission speed can be returned to normal data transmission. Since the transmission speed is reduced due to fallback and the error margin is increased, it is difficult to make a judgment based on the current speed, and the only way is to actually return it to the original speed and try it.

[Problem that the invention seeks to solve]

With the conventional method described above, even if you try to restore it, it is not known whether normal data transmission without errors can be reproduced, and the only way to do so is to actually restore the original transmission speed and try again. Therefore, if it fails, there is a problem that even the minimum level of data transmission cannot be secured.

There was also the problem that it was not possible to list items automatically.

[Means for solving problems]

The automatic fallback and restore method of the present invention includes a reception register that shifts received data every time slot, a correction register that stores an equalization correction amount, and one of the above reception registers.
A calculation means for multiplying and adding the above-mentioned equalization correction amount to the output of each time slot to obtain equalized data, and an identification circuit for creating an error amount between the equalization data obtained by this calculation means and the ideal value. and a correction means for changing the equalization correction amount according to the error amount, a data modulation/demodulation device having an automatic equalization circuit,
In the receiving section, a squaring circuit that squares the data in each slot of the correction register, an adder that adds the outputs of the squaring circuit of each slot, and a signal quality detection signal output from the automatic equalization circuit are used. a memory circuit that is controlled and stores the output of the adder; a comparison circuit that compares the output of the memory circuit with the output of the adder; and a selection circuit that selects the output of the comparison circuit or the signal quality detection signal or transmission data. The transmission section receives the comparison circuit output or the signal quality detection signal from the reception section and outputs a speed selection signal for determining the transmission data speed to the terminal.

[Effect]

In the present invention, the value of a correction register that compensates for line deterioration is monitored.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In the figure, 1 indicates a transmitter, 2 a modulation circuit, and 3 a demodulation circuit. 4 indicates the receiving section, 5
is a demodulation circuit, 6 is a modulation circuit, 7 is an automatic equalization circuit,
8 is a squaring circuit for squaring the data in each slot of the modification register, which will be described later; 9 is a squaring circuit 8 for each slot;
10 is an automatic equalization circuit 7
11 is a comparator circuit that compares the output of the memory circuit 10 with the output of the adder 9; 12 is a comparator circuit of the comparator circuit 11; This is a selection circuit that selects the output or signal quality detection signal SQD or transmission data, and these are provided in the receiving section 4.

The transmitter 1 is configured to receive the output of the comparison circuit 11 or the signal quality detection signal SQD from the receiver 4 and output a speed selection signal SS for determining the speed of transmission data to the terminal. has been done.

FIG. 2 is a block diagram showing where the squaring circuit used in the present invention is connected to the conventional automatic equalization circuit.

In FIG. 2, the same symbols as in FIG. 1 indicate corresponding parts, 21 is a reception register that shifts the received data RD every time slot, and 23 is a correction register (C register) that stores the equalization correction amount.
It is. 22 is a multiplier, 24 is an adder, and 25 is an adder, and these constitute an arithmetic means for multiplying the output of each time slot of the receiving register 21 by the equalization correction amount and adding the same to obtain equalized data. ing.
Reference numeral 26 represents an identification circuit for creating an amount of error between the equalized data obtained by this calculation means and the ideal value, and 27 represents a signal quality detection circuit.

The reception register 21 and signal quality detection circuit 27 constitute an automatic equalization circuit.

Next, the operation of the embodiment shown in FIG. 1 will be explained with reference to FIG. 2.

First, in the transmitter 1, it is assumed that the transmission data SD is switched to 9600 bps or 4800 bps, respectively, by "0" and "1" of the speed selection signal SS, as an example.
The speed selection signal SS is "0" and transmission data of 9600 bps is being transmitted.

On the other hand, in the receiving section 4, if the deterioration of the line is small,
The signal quality detection signal SQD, which is the signal quality detection output of the automatic equalization circuit 7, is "0", and the squaring circuit 8 squares each slot of the correction register 23 (C register) shown in FIG. Since the added output of the circuit 9 has little line deterioration, it is also a small value to compensate for it, and is stored in the memory circuit 10 for each time slot.
Furthermore, when the signal quality detection signal SQD is "0", the output of the comparison circuit 11 is fixed to "0". Therefore, the selection circuit 12 normally selects the transmission data.
SD is selected and data transmission is taking place.

Next, if the line deteriorates significantly due to line disturbances, the signal quality detection signal SQD becomes "1" and the selection circuit 12 The signal quality detection signal SQD is sent instead of the transmitted data SD.
="1" information is sent, and the speed selection signal SS in the transmitter 1 is changed to "1". Therefore, the transmission data SD is rolled back to 4800 bps.

At this time, in reception, the signal quality detection signal is
By setting SQD="1", the normal square value of the correction register 23 (C register) shown in FIG. 2 before the disturbance is stored in the memory circuit 10 and saved.

Now, the data speed is 4800bps due to the above operation
Even when the line deteriorates significantly, the inter-symbol interference is small compared to 9600bps, so a sufficient data error margin is secured and the signal quality detection signal SQD returns to "0", but even if the line deteriorates, Since the factor is still large, the output of the squaring circuit 8 is a large value. Therefore, when compared with the normal value that has already been stored, the value of the A input of the comparison circuit 11 has become larger, and the comparison circuit 11 has a "1" value.
is outputting. Here, the output of the comparator circuit 11 was initially fixed at "0" due to SQD="0", but once SQD="1", the output becomes SQD="0". Even after getting old, the comparison operation has started. As a result, even if SQD="0", the selection circuit 12 selects the output "1" of the comparison circuit 11 and periodically sends "1" to the transmitter 1. (Communicated during normal data communication free time).

Next, consider the case where the line disturbance returns to its original normal value over time. At this time, the value of the correction register 23 (C register) that compensates for line deterioration similarly returns to its original normal value, so the output of the squaring circuit 8 also returns to its original small value.

At this time, when the comparison circuit 11 compares the value already stored in the memory circuit 10 and the output of the squaring circuit 8, the A input and the B input are equal, or the A input is smaller. Then,
Comparison circuit 11 outputs "0". This "0" signal is sent to the transmitter 1 via the selection circuit 12, and sets the speed selection signal SS to "0". Therefore, the transmitted data will be restored to its original 9600bps.
In the receiving section 4, since the line value is small, the signal quality detection signal SQD is the original normal "0".

In this way, automatic fallback from 9600bps to 4800bps, then
Automatic restore from 4800bps to 9600bps can be achieved.

FIG. 3 shows the values of the correction register 23 (C register) for compensating for line deterioration shown in FIG. 2 in each state. Further, a shows a case where line deterioration is small, and b shows a case where line deterioration is large.

〔Effect of the invention〕

As explained above, according to the present invention, by monitoring the value of the correction register (C register) that ensures line deterioration, the original data can be transferred without interfering with normal data transmission, especially in the state of once fallback. This has the effect of being able to determine the state that can be restored to speed and execute automatic restoration.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention;
Figure 2 is a block diagram showing where the squaring circuit used in the present invention is connected to the conventional automatic equalization circuit, and Figure 3 shows the values of the correction register that compensates for line deterioration in each state. FIG. DESCRIPTION OF SYMBOLS 1... Transmission section, 2... Modulation circuit, 3... Demodulation circuit, 4... Receiving section, 5... Demodulation circuit, 6... Modulation circuit, 7... Automatic equalization circuit, 8... Square circuit, 9
... Adder, 10 ... Memory circuit, 11 ... Comparison circuit, 12 ... Selection circuit, 21 ... Reception register, 22 ... Multiplier, 23 ... Correction register, 2
4... Adder, 25... Adder, 26... Discrimination circuit, 27... Signal quality detection circuit.

Claims (1)

[Claims] 1. A reception register that shifts received data every time slot, a correction register that stores an equalization correction amount, and an equalization data obtained by multiplying and adding the equalization correction amount to the output of the reception register for each time slot. a discriminating circuit for creating an error amount between the equalized data obtained by the arithmetic means and an ideal value, and a correcting means for changing the equalization correction amount in accordance with the error amount. In the data modulation/demodulation device having an automatic equalization circuit, the reception section includes a squaring circuit for squaring the data in each slot of the correction register, an adder for adding the outputs of the squaring circuit for each slot, and the automatic equalization circuit. a memory circuit that is controlled by a signal quality detection signal of the output of the converter circuit and stores the output of the adder; a comparator circuit that compares the output of the memory circuit with the output of the adder; A selection circuit that selects a signal quality detection signal or transmission data is provided, and the transmission section receives the comparison circuit output or signal quality detection signal from the reception section and determines the speed of the transmission data to the terminal. An automatic fallback and restore method characterized by outputting a selection signal.