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JPH0519689B2 - - Google Patents
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JPH0519689B2 - - Google Patents

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Publication number
JPH0519689B2
JPH0519689B2 JP60011849A JP1184985A JPH0519689B2 JP H0519689 B2 JPH0519689 B2 JP H0519689B2 JP 60011849 A JP60011849 A JP 60011849A JP 1184985 A JP1184985 A JP 1184985A JP H0519689 B2 JPH0519689 B2 JP H0519689B2
Authority
JP
Japan
Prior art keywords
semiconductor film
substrate
electrode
film
display device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP60011849A
Other languages
Japanese (ja)
Other versions
JPS61170724A (en
Inventor
Shunichi Motsute
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP60011849A priority Critical patent/JPS61170724A/en
Publication of JPS61170724A publication Critical patent/JPS61170724A/en
Publication of JPH0519689B2 publication Critical patent/JPH0519689B2/ja
Granted legal-status Critical Current

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  • Liquid Crystal (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、アクテイブマトリクス液晶表示装置
用基板における薄膜トランジスタに関するもので
ある。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a thin film transistor in a substrate for an active matrix liquid crystal display device.

〔発明の概要〕[Summary of the invention]

透明絶縁基板上に電荷保持用容量を持つアクテ
イブマトリクス表示装置用基板において、電荷保
持用容量部を前段のゲート電極とゲート絶縁膜と
半導体膜と透明電極からなる画素電極の一部から
形成し、前記半導体膜はトランジスタ部とドレイ
ン配線部と分離された島状領域に形成することに
よつて、良好な画質を持つたアクテイブマトリク
ス表示装置用基板が提供できる。
In a substrate for an active matrix display device having a charge retention capacitor on a transparent insulating substrate, a charge retention capacitor portion is formed from a part of a pixel electrode consisting of a previous gate electrode, a gate insulating film, a semiconductor film, and a transparent electrode, By forming the semiconductor film in an island-like region separated from the transistor section and the drain wiring section, a substrate for an active matrix display device having good image quality can be provided.

〔従来の技術〕[Conventional technology]

従来のアクテイブマトリクス液晶表示装置の単
位画素の例を第2図に示す。第2図aは、単位画
素構造例の平面図を示し、第2図bは、第2図a
のc−c′線に沿つた断面図、第2図cは第2図a
のD−D′線に沿つた断面図である。ガラス等の
透明絶縁基板1上には、cr,Av,/Cr,Mp,Al
等のゲート電極2が設けられ、行電極として延在
している。前段のゲート電極2′も図示されてい
る。ゲート電極2上には、二酸化シリコン、チツ
化シリコン等のゲート絶縁膜3、アモルフアスシ
リコン等の半導体膜5が設けられ、半導体膜5上
には列電極としてのドレイン電極6、ソース電極
7が配され、ソース電極7と画素電極4が接続さ
れている。画像信号等を保持するための電荷保持
用容量は、前段のゲート電極2′とゲート絶縁膜
3と半導体膜5と画素電極4とで構成されてい
る。なおトランジスタ部と電荷保持用容量部の半
導体膜5は接続された型で配されていう。さらに
上部からの光を遮閉するための遮光膜やパツシベ
ーシヨン膜等が形成されることもあるが、本発明
に直接関係ないので省略する。第2図a,b及び
cの構造例では、電荷保持用容量に書き込まれた
画像信号等がリークして良好な画質が得られない
欠点がある。
FIG. 2 shows an example of a unit pixel of a conventional active matrix liquid crystal display device. FIG. 2a shows a plan view of an example of a unit pixel structure, and FIG. 2b shows a plan view of an example of a unit pixel structure.
A cross-sectional view taken along line c-c' of Figure 2c is Figure 2a
FIG. 2 is a sectional view taken along line DD' of On the transparent insulating substrate 1 made of glass or the like, cr , A v , /C r , M p , A l
A gate electrode 2 is provided, extending as a row electrode. The preceding gate electrode 2' is also illustrated. On the gate electrode 2, a gate insulating film 3 made of silicon dioxide, silicon dioxide, etc., and a semiconductor film 5 made of amorphous silicon, etc. are provided, and on the semiconductor film 5, a drain electrode 6 and a source electrode 7 as column electrodes are provided. The source electrode 7 and the pixel electrode 4 are connected to each other. A charge retention capacitor for retaining image signals and the like is composed of a front-stage gate electrode 2', a gate insulating film 3, a semiconductor film 5, and a pixel electrode 4. Note that the semiconductor film 5 of the transistor section and the charge holding capacitor section are arranged in a connected type. Furthermore, a light shielding film, a passivation film, etc. for blocking light from above may be formed, but these are not directly related to the present invention and will therefore be omitted. The structural examples shown in FIGS. 2a, b, and c have the drawback that image signals and the like written in the charge holding capacitor leak, making it impossible to obtain good image quality.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

第2図a,b及びcに示すように、従来の構造
だと、電荷保持用容量に書き込まれた画像信号
が、半導体膜5を介してドレイン電極6あるいは
ソース電極7′にリークして、画像信号が保持さ
れず、コントラストの良い画質が得られない。本
発明は、上記問題点を解決するもので工数を特に
増加しないで、良好な画質を持つたアクテイブマ
トリクス表示装置のための薄膜トランジスタの単
位画素構造を提供するものである。
As shown in FIGS. 2a, b, and c, in the conventional structure, the image signal written in the charge holding capacitor leaks to the drain electrode 6 or source electrode 7' via the semiconductor film 5. Image signals are not maintained and image quality with good contrast cannot be obtained. The present invention solves the above problems and provides a unit pixel structure of thin film transistors for an active matrix display device that has good image quality without particularly increasing the number of man-hours.

〔問題点を解決するための手段〕[Means for solving problems]

上記問題点を解決するために本発明は、電荷保
持用容量部とトランジスタ部に形成される半導体
膜を分離形成することによつて、画像信号等のリ
ークを防止するものである。
In order to solve the above-mentioned problems, the present invention prevents leakage of image signals and the like by separately forming the semiconductor film formed in the charge holding capacitor part and the transistor part.

〔作用〕[Effect]

上記のように構成すると、例えば電荷保持用容
量に書き込まれた画像信号は、半導体膜を伝わつ
てリークすることなく保持され、コントラストの
良い画質が工数の増加なく達成できる。
With the above configuration, for example, the image signal written in the charge holding capacitor is held without leaking through the semiconductor film, and image quality with good contrast can be achieved without increasing the number of steps.

〔実施例〕〔Example〕

以下に本発明の実施例を図面に基づいて詳細に
説明する。第1図aは、本発明の単位画素の構造
例の平面図を示す。第1図bは、第1図aのA−
A′線に沿つた断面図、第1図cは第1図aのB
−B′線に沿つた断面図である。ガラス等の透明
絶縁基板1上には、Al,cr,Mp等のゲート電極
2が設けられ、行電極として延在している。前段
のゲート電極2′も図示している。ゲート電極2
上には、二酸化シリコン、チツ化シリコン等のゲ
ート絶縁膜3、アモルフアスシリコン等の半導体
膜5が形成されている。、前段のゲート電極2′上
には、前記ゲート絶縁膜3、半導体膜5と同時に
積層された絶縁膜3′、半導体膜5′が形成され、
ITO等の透明導電膜である画素電極4の一部とに
よつて電荷保持用容量が構成されている。半導体
膜5上には、列電極としてのドレイン電極6、ソ
ース電極7が配され、ソース電極7と画素電極4
が接続されている。電荷保持用容量部の半導体膜
5′をドレイン電極6、ソース電極7,7′を配す
る半導体膜5と分離した島状領域に形成すること
によつて、例えば電荷保持用容量に書き込まれた
画像信号は、半導体膜5′が島状に形成されてい
るのでリークすることなく保持され、工数を増す
ことなくコントラストの良好な画像表示を得るこ
とが出来る。なお、電荷保持用容量の構成を半導
体膜5′をなくす方法も考えられるが、トランジ
スタ部の半導体膜5のバターニング時、エツチヤ
ント等による損傷を絶縁膜3′に与え、絶縁耐圧
不良発生の原因となるので、本発明に示すように
半導体膜5′を島状に形成した構造が良い。
Embodiments of the present invention will be described in detail below based on the drawings. FIG. 1a shows a plan view of a structural example of a unit pixel according to the present invention. Figure 1b is A- in Figure 1a.
A cross-sectional view along line A', Figure 1c is B of Figure 1a.
FIG. 3 is a cross-sectional view taken along line -B'. Gate electrodes 2 such as Al , cr , and Mp are provided on a transparent insulating substrate 1 made of glass or the like and extend as row electrodes. The preceding gate electrode 2' is also shown. Gate electrode 2
A gate insulating film 3 made of silicon dioxide, silicon nitride, etc., and a semiconductor film 5 made of amorphous silicon, etc. are formed thereon. , an insulating film 3' and a semiconductor film 5', which are laminated simultaneously with the gate insulating film 3 and semiconductor film 5, are formed on the previous gate electrode 2',
A charge retention capacitor is constituted by a part of the pixel electrode 4 which is a transparent conductive film such as ITO. A drain electrode 6 and a source electrode 7 as column electrodes are arranged on the semiconductor film 5, and the source electrode 7 and the pixel electrode 4
is connected. By forming the semiconductor film 5' of the charge retention capacitor part in an island-like region separated from the semiconductor film 5 on which the drain electrode 6 and source electrodes 7 and 7' are arranged, it is possible to Since the semiconductor film 5' is formed in an island shape, the image signal is held without leakage, and an image display with good contrast can be obtained without increasing the number of steps. Although it is possible to configure the charge retention capacitor by eliminating the semiconductor film 5', this may cause damage to the insulating film 3' due to etchant etc. during patterning of the semiconductor film 5 of the transistor section, causing breakdown voltage failure. Therefore, a structure in which the semiconductor film 5' is formed into an island shape as shown in the present invention is preferable.

〔発明の効果〕〔Effect of the invention〕

本発明は以上説明したように、単位画素をマト
リクス状に配置するアクテイブマトリクス表示装
置用基板の製造工数を増加することなく、電荷保
持用容量の耐圧をそこなうことなく良好な画質を
持つたアクテイブマトリクス液晶表示装置用基板
における薄膜トランジスタを提供できる。
As explained above, the present invention provides an active matrix that has good image quality without increasing the number of manufacturing steps for a substrate for an active matrix display device in which unit pixels are arranged in a matrix, and without impairing the withstand voltage of the charge retention capacitor. A thin film transistor in a substrate for a liquid crystal display device can be provided.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図aは本発明による薄膜トランジスタの単
位画素構造例の平面図であり、第1図bは第1図
aのA−A′線に沿つた断面図、第1図cは第1
図aのB−B′線に沿つた断面図である。第2図
aは従来の単位画素構造例の平面図であり、第2
図bは第2図aのc−c線に沿つた断面図、第2
図cは第2図aのD−D′線に箔つた断面図であ
る。 1……基板、2,2′……ゲート電極、3……
ゲート絶縁膜、4……画素電極、5,5′……半
導体膜、6……ドレイン電極、7……ソース電
極。
FIG. 1a is a plan view of an example of a unit pixel structure of a thin film transistor according to the present invention, FIG. 1b is a cross-sectional view taken along line A-A' in FIG. 1a, and FIG.
FIG. 3 is a sectional view taken along line BB' in FIG. FIG. 2a is a plan view of an example of a conventional unit pixel structure.
Figure b is a cross-sectional view taken along line c-c in Figure 2 a;
Figure c is a sectional view taken along line D-D' in Figure 2a. 1... Substrate, 2, 2'... Gate electrode, 3...
Gate insulating film, 4...pixel electrode, 5, 5'... semiconductor film, 6... drain electrode, 7... source electrode.

Claims (1)

【特許請求の範囲】[Claims] 1 少なくとも電荷保持用容量部が、前段のゲー
ト電極とゲート絶縁膜と半導体膜と透明導電膜か
らなる画素電極の一部とによつて構成されたアク
テイブマトリクス表示装置用基板において、前記
半導体膜は少なくともトランジスタ部とドレイン
配線部と分離された島状領域に形成されているこ
とを特徴とするアクテイブマトリクス表示装置用
基板。
1. In a substrate for an active matrix display device in which at least a charge retention capacitor section is constituted by a preceding gate electrode, a gate insulating film, a semiconductor film, and a part of a pixel electrode made of a transparent conductive film, the semiconductor film is 1. A substrate for an active matrix display device, characterized in that the substrate is formed in an island-like region separated from at least a transistor section and a drain wiring section.
JP60011849A 1985-01-25 1985-01-25 Substrate for active matrix display device Granted JPS61170724A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60011849A JPS61170724A (en) 1985-01-25 1985-01-25 Substrate for active matrix display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60011849A JPS61170724A (en) 1985-01-25 1985-01-25 Substrate for active matrix display device

Publications (2)

Publication Number Publication Date
JPS61170724A JPS61170724A (en) 1986-08-01
JPH0519689B2 true JPH0519689B2 (en) 1993-03-17

Family

ID=11789169

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60011849A Granted JPS61170724A (en) 1985-01-25 1985-01-25 Substrate for active matrix display device

Country Status (1)

Country Link
JP (1) JPS61170724A (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61157927U (en) * 1985-03-20 1986-09-30
US4819038A (en) * 1986-12-22 1989-04-04 Ibm Corporation TFT array for liquid crystal displays allowing in-process testing
US5210045A (en) * 1987-10-06 1993-05-11 General Electric Company Dual dielectric field effect transistors for protected gate structures for improved yield and performance in thin film transistor matrix addressed liquid crystal displays
JP2828981B2 (en) * 1987-12-25 1998-11-25 株式会社日立製作所 Liquid crystal display panel
DE69022010T2 (en) * 1989-12-22 1996-04-18 Philips Electronics Nv Electro-optical display device with active matrix and storage capacitors and color projection apparatus using the same.
JP2907629B2 (en) * 1992-04-10 1999-06-21 松下電器産業株式会社 LCD panel
DE69326123T2 (en) * 1992-06-24 1999-12-23 Seiko Epson Corp., Tokio/Tokyo THIN FILM TRANSISTOR AND METHOD FOR PRODUCING A THIN FILM TRANSISTOR

Also Published As

Publication number Publication date
JPS61170724A (en) 1986-08-01

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