JPH0519824B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (A) TECHNICAL FIELD OF THE INVENTION The present invention relates to an integrated circuit pattern generation system, and more particularly, to a system for generating integrated circuit patterns, and more particularly, to a system for generating integrated circuit patterns, and in particular to an integrated circuit pattern generation system, which is structured so that fixed wiring cells, e.g. This relates to an integrated circuit pattern generation system that automatically designs wiring patterns by inputting a logic circuit diagram consisting of predetermined logic symbols and connection information to a master bulk in which elements such as transistors and resistance elements are regularly arranged in advance. It is.

(B) Technical Background and Problems In order to easily and quickly supply integrated circuits with new functions, the so-called master slice method is known as an LSI chip configuration method. In the master slicing method, a basic cell in which a NAND gate or the like can be configured, such as a NAND gate, is prepared in common for each product type, and the detailed functions of the LSI are determined. At this stage, the detailed wiring pattern is determined.

Figure 1 is an example of a semiconductor substrate on which basic cells are arranged, Figure 2 is an example of a 3-input Nando game equivalent circuit with one basic cell, Figure 3 is an example of the symbol of the circuit shown in Figure 2, and Figure 4 is a macro. The fifth example shows an example of a logic diagram of a logic block, and the fifth example shows an example of a symbol of a macro logic block.

For example, as shown in FIG. 1, the semiconductor substrate 1 includes
A master bulk pattern is prepared in advance, which is created in common for all types of products, including the diffusion process and basic wiring. For example, a large number of basic cells 2 are arranged so that gates such as basic NAND or Norr gates can be configured, and input/output buffer cells 4 are provided around the basic cell area 3. Furthermore, an input/output pad 5 is arranged around the periphery. When an integrated circuit having a desired logical function is required, by providing this master bulk with a wiring pattern for connecting and combining each basic cell 2, etc.,
Logic circuits can now be constructed with fewer steps.

Although detailed pattern diagrams are omitted, for example, one basic cell 2 is a typical example as shown in Fig. 2.
A fixed pattern cell of TTL NAND circuit is obtained.
When this circuit is converted into a logic symbol, it is usually represented as shown in FIG. In addition, by using a plurality of basic cells, it is possible to create fixed pattern cells such as NAND gates and NOR gate latches that have many inputs. On a larger scale, for example, as shown in the logic diagram of FIG. 4, a well-known D-type flip-flop is constructed by combining many fixed pattern cells (hereinafter referred to as cells). be able to. An example of this flip-flop converted into a logical symbol is shown in FIG. A block composed of a plurality of cells and having a certain logic function is called a macro logic block. There are two ways to implement the macro logic block.

(1) A method of configuring cells by combining cells such as NAND gates and NOR gates.

In other words, only the logical connection relationship between cells and the overall logical symbol are registered, the actual physical pattern is not fixed, the constituent cells are flexibly arranged, and the cells are also flexibly and optimally wired. Configure.

(2) A macro logic block having a hierarchical structure is constructed by combining the above macro logic block and fixed pattern cells. This is also handled in the same way in that only the logical configuration and symbols are registered.

Once developed, each cell is a collection of fixed pattern cells, and although the physical pattern is not fixed, the logical configuration is fixed, so to speak, it is a flexible cell, and on the logic circuit diagram it is a single symbol. It can be thought of as being expressed and treated as

Conventionally, when placing and wiring cells in an integrated circuit from a logic circuit diagram of an integrated circuit that combines many logic symbols of various cells and flexible cells, the components of the logic circuit diagram are numerically transferred to a computer that designs patterns. It was common to input data. Recently, for example, logical circuit diagrams drawn on graph paper are read using optical means.
It has been proposed that a computer internally analyze the components of a logic circuit. However, there has been a problem in the past that it has been difficult to clarify how symbols are given to macro logic blocks. The reason for this is that macro logic blocks are assembled hierarchically using other macro logic blocks and are generally not standardized, and when the terminals for various input/output functions of macro logic blocks are unused. The reason for this is that it does not appear on the logical drawing. Another problem is that it is difficult to optimize wiring patterns for power supplies using computers, especially when designing connections with so-called stack cells, because lines that supply power are usually omitted in logical drawings. It was hot.

Therefore, when a designer creates a logic diagram from, for example, an actual IC wiring diagram, there is a problem in that he or she must first be aware of the internal logic of the IC, and then search for and draw the terminals of the macro logic block that match that logic. .

(C) Object and Structure of the Invention The present invention aims to solve the above-mentioned problems, and provides a macro logic block with functions at the small scale integrated circuit (SSI) and medium scale integrated circuit (MSI) level. The image of the IC package is given as a logic symbol, and its terminals are also expressed as
Match the input/output terminals of standard ICs with the same function, and connect empty terminals to Vcc or Vcc terminals.
An integrated circuit pattern that facilitates the creation of a logic diagram to be input by connecting it to a GND terminal, etc., allows complete information to be obtained from the logic diagram, and furthermore enables the design of an optimal pattern. The purpose is to provide a generation system. Therefore, the integrated circuit pattern generation system of the present invention provides a logic circuit diagram in which fixed wiring on an integrated circuit chip and/or connection relationships between macro logic blocks with a fixed internal logic configuration are defined by predetermined logic symbols. a graphic data input means for inputting data; a library storing the logic symbols and detailed wiring data associated with the logic symbols; and logic circuit diagram drawing data input by the graphic data input means. and a logic circuit connection information extraction means for analyzing the logic symbol based on the library and analyzing the connection between the terminals of the logic symbol to extract connection information of the logic circuit. In an integrated circuit pattern generation system that creates integrated circuit pattern data based on the results, the logic symbols extracted by the logic circuit connection information extraction means include a rectangular figure image and the fixed wiring cell surrounding the rectangular figure. and/or terminals arranged in a predetermined positional relationship corresponding to the functions of the macro logic block, including power supply and/or
or a terminal image including a ground terminal, and is characterized by comprising stack cell connection processing means for processing empty terminals of the logic symbol based on connection information to the power supply and/or ground terminal in the logic symbol. . This will be explained below with reference to the drawings.

(D) Embodiment of the Invention Fig. 6 shows the configuration of an embodiment of the invention, Fig. 7 is an explanatory diagram of the macro logic data file creation process, Fig. 8 is an explanatory diagram of the processing of the logic symbol analysis section, and Fig. 9 is Examples of logic symbols of macro logic blocks related to the present invention, FIG. 10 is a specific example of logic symbols of macro logic blocks, FIG. 11 is a logic diagram corresponding to the logic symbols shown in FIG. An example of a drawing using logical symbols according to the invention is shown.

In FIG. 6, a logic circuit diagram 11 is a diagram drawn, for example, on a predetermined graph paper, and defines the logical functions of an integrated circuit to be developed, and includes macros that will be described later with reference to FIG. It is created using logic symbols of logic blocks. Of course, conventionally used symbols such as and gates and or gates can also be used in combination. The graphic input device 12 is a device that irradiates and scans the logic circuit diagram 11 with light, for example, by optical means, and inputs graphic data on the logic circuit diagram 11 based on the intensity of the reflected light. When a dedicated graphics processor is used to input graphic data, the graphic data is delivered to a large host computer via an external storage medium such as a magnetic tape or online.

For example, the logic symbol analysis unit 13, which consists of a group of instructions executed by a large computer, extracts logic symbols of various cells and macro logic blocks predefined in a predetermined format from the graphic data obtained from the logic circuit diagram 11. Then, the symbol data file 22 is referred to for analysis. The symbol data file 22 is a library in which what symbol corresponds to which cell or macro logic block is registered and stored in advance. After the logical symbol analysis section 13 extracts the logical symbols, the connection data extraction section 14 is activated. The connection data 14 is for extracting connection information between the terminals of the logic symbol recognized by the logic symbol analysis unit 13 from the graphic data. The extracted connection data is stored in the logical connection data file 27 as a relationship between cells/flexible cells and their terminals. The logical connection data file 27 is a work file in which connection information at a logical level whose physical location is not fixed is recorded. In addition, the logical symbol analysis unit 1
Techniques such as closed region extraction and line segment extraction in image recognition are used for the extraction of logical symbols by 3 and the extraction of connection data by the connection data extraction unit 14, but various methods are known.
A detailed explanation thereof will be omitted.

The logic hierarchy expansion unit 15 refers to the macro logic data file 23 and expands the macro logic block included in the input logic symbol into lower level cells and other macro logic blocks that constitute the macro logic block. It performs various processing. In the macro logic data file 23, cell/macro logic block information that is a component of each macro logic block and information on their logical connections are registered and stored in advance for each macro logic block. By repeatedly referring to this macro logic data file 23, the expansion process is finally performed up to the logic level of the basic cell corresponding to the fixed pattern, and the expansion result is stored in the logic connection data file 27.
Store in. Logic data about the cell logic is obtained from the cell logic data file 24.

The detail processing unit 16 executes necessary processing prior to placement/wiring processing, such as erasing invalid gates and inspecting empty terminals. The stack cell connection processing unit 17 connects power sources such as Vcc and GND represented by logic symbols of macro logic blocks.
This process performs processing to configure a logic circuit so that a ground terminal is connected to a stack cell. At this time, stack cells are provided separately for each macro logic block or for each block having a certain logical function. Unused empty terminals in macro logic blocks are closed within each macro logic block and wired to stack cells for applying DC bias to the empty terminals. Note that the order of processing by the logical hierarchy expansion section 15, detail processing section 16, stack cell connection processing section 17, etc. does not necessarily have to be in the order described in this explanation.

The automatic layout processing unit 18 reads the contents of the logical connection data file 27, refers to the cell shape characteristic data file 25 and the LSI chip physical data file 26, and determines which physical position cells are used to configure each macro logical block. The layout will be done as to what will be done. The cell shape characteristic data file 25 stores arrangement information, dimension information, etc. of resistors and transistor elements constituting the cell. LSI chip physical data file 26
Physical information regarding the master bulk, such as dimension information, number of basic cells, number of input/output buffers, and number of input/output pads, is stored in advance. The automatic layout processing unit 18 allocates cells, for example, by trial and error, checks logical unpredictability, evaluates virtual wiring lengths, etc., and determines the optimal layout. The results are stored in layout output data file 28.

The pattern data creation section 19 reads the contents of the layout output data file 28, refers to the cell shape characteristic data file 25 and the LSI chip physical data file 26, and creates actual pattern data. The created actual pattern data is input directly or via an external storage medium such as the magnetic tape 20 to a pattern generator 21 such as an electron beam exposure device, and a mask pattern is manufactured. It is also possible to draw by directly exposing the chip.

The macro processing data file 23 is, for example, the seventh
It is created by the process shown in the figure. First, in the process 30 shown in FIG. 7, a logic diagram 11' of a macro processing block to be newly defined is input.
This logic diagram 11' was created using logic symbols for cells and other predefined macro logic blocks. Next, in process 31, symbols and connection data constituting a logic circuit are extracted, and in process 32, logic data consisting of component cells, macro logic blocks, and their connection information is stored in a macro logic data file. Register on 23. By repeating the above process, macro logic blocks can be defined hierarchically, and the defined macro logic blocks can be used from now on, focusing only on their logical functions, without having to be aware of their internal structure. It becomes like this.

FIG. 8 shows the logic symbol analysis unit 13,
In particular, it describes the process of extracting logical symbols represented by the image of an IC package from graphical data. First, in process 40, the graphic data prepared on the buffer is scanned, connection figures and symbol figures are distinguished, and rectangular figures are extracted. Next, in process 41, images of terminals arranged in a predetermined positional relationship around the extracted rectangular figure are extracted. Images of these terminals are connected to line segments for wiring. Once the terminal images have been extracted, in step 42, the vertical direction of the logical symbol is determined, for example, from the positional relationship of the extracted terminals. In process 43, identification information regarding which macro logic block this logic symbol corresponds to is read and analyzed. The identification information is given, for example, as a macro logic block identification name placed at a predetermined position of a rectangular figure, and is recognized by a well-known character recognition technique. The recognition data resulting from the recognition is set in a working storage area in a process 44.

FIG. 9 shows an example of a macro logic block symbol given as an image of an IC package. When a macro logic block has the same logical function as, for example, a dual-in-line package such as SSI or MSI, the shape of the package is symbolized as it is. The terminal image 52 is arranged in a predetermined positional relationship with respect to the rectangular figure 50. The functions of these terminal images 52 are as follows:
It corresponds to the input/output pins of the IC package. In particular, in conventional logic diagram symbols, power/ground terminals such as Vcc and GND that are not shown on the diagram are also symbolized in correspondence with input/output pins of the IC package. Further, this symbol includes symbol direction information in order to clarify the positional relationship of the terminals. for example,
This direction information may be given by a mark (not shown) inside the rectangular figure 50 indicating the direction.
It may also be provided by partial unevenness of 0 (not shown). In the example of FIG. 9, the distances a and b from the end of the rectangular figure 50 to the first terminal are set to be larger in the upward direction than in the downward direction. That is, in this example, since the distance a is larger than the distance b, the side a is recognized as being upward. The area 51 within the symbol is an area where identification information of the macro logic block is given,
For example, the type of macro logic block is uniquely determined by the code, character, etc. written in this area 51. In addition, the rectangular figure 50
does not necessarily have to be a perfect rectangle, but may be any shape that can be considered to substantially imitate the shape of the IC package.

FIG. 10 shows specific examples of symbols. The symbols shown in FIGS. 10A and 10B are symbols for macro logic blocks having the function of a data selector/multiplexer, such as those of the very well-known SN74LS157 and SN74LS158 type integrated circuits from Texas Instruments. Each corresponds to the function of the circuit. Regarding the terminal with this symbol, for example, "The TTL Data Book" published by Texas Instruments Inc.
It now corresponds to the package input/output pin arrangement described in "For Design Engineers." Similarly, the symbols shown in FIG.
It supports the functions of SN74LS161 type integrated circuit. These TTL integrated circuits are very well known and can be said to be treated as standardized by those skilled in the art.
Just by looking at the symbol representing the IC package,
It can be said that its functions and input/output information can be grasped immediately. Note that the identification names of macro processing blocks may also be changed, such as "F157", "F158", "F160", etc.
It is convenient to give a name related to the type number, such as "F161".

FIG. 11 is a diagram showing the internal logical configuration of the macro logic block represented by the symbols shown in FIG. 10D. By the process explained in FIG. 7, once the internal configuration of the macro logic block as shown in FIG. Focusing only on the 10th
A macro processing block symbolized as shown in FIG. 2 can be used. Power/ground terminal
For Vcc and GND, stack cell ST1,
ST0 is assigned. A stack cell is a basic cell whose function is simply to shoot to a power line.

FIG. 12 shows an example of a portion of a drawing of a logic circuit used for input according to the present invention. In this example, six symbols of the macro logic block explained in FIG. 9 are used. As can be seen from FIG. 12, a logic diagram can be created directly from an IC board or IC physical layout diagram, making it extremely easy to create a logic diagram. In particular, the input/output pins of the IC package can be copied as they are, and the probability of writing errors and connections can be greatly reduced. Furthermore, in the case of the present invention, as shown in FIG. 12, by connecting the empty terminals of the symbolized macro logic block to the power/ground terminals Vcc and GND of the macro logic block, each empty terminal is Information on whether to connect to the high potential side or the low potential side can be given. The processing device is connected to an empty terminal.
Since the wiring to the stack cells for applying DC bias can be processed in each macro logic block, it is possible to generate a wiring pattern that is simple and favorable in terms of layout. In other words, if a macro logic block does not have terminals such as Vcc and GND, it tends to wire many functional units from one stack cell, which has the disadvantage that the wiring pattern becomes complicated. That is avoided.

(E) Effects of the invention As explained above, according to the present invention, an IC board,
When creating a high-performance integrated circuit by creating a logic diagram from an IC physical wiring diagram, you can work directly and easily generate integrated circuit patterns. In addition, the wiring to the stack cell for applying DC bias to empty terminals can be simplified, and a pattern suitable for layout can be generated.Furthermore, the logic diagram that serves as input information is simple and its function and configuration are clear. As a result, debugging and modification to other functions are facilitated.

[Brief explanation of the drawing]

Figure 1 shows an example of a semiconductor substrate on which basic cells are arranged, Figure 2 shows an example of a NAND gate equivalent circuit using one basic cell, Figure 3 shows an example of the symbol of the circuit shown in Figure 2, and Figure 4 shows a macro logic block. Example of logic diagram,
FIG. 5 is an example of a symbol of a general macro logic block, FIG. 6 is a configuration of an embodiment of the present invention, FIG. 7 is an explanatory diagram of the creation process of a macro logic data file, and FIG.
9 is an explanatory diagram of the processing of the logic symbol analysis unit, FIG. 9 is an example of logic symbols of a macro logic block related to the present invention, FIG. 10 is a specific example of logic symbols of a macro logic block, and FIG. FIG. 12 shows an example of a drawing using logic symbols according to the present invention. In the figure, 11 represents a logic circuit diagram, 12 represents a graphic input device, 13 represents a logic symbol analysis section, and 17 represents a stack cell connection processing section.

Claims (1)

[Claims] 1. Input of logic circuit diagram drawing data that defines the connection relationships between fixed wiring cells on an integrated circuit chip and/or macro logic blocks with a defined internal logic configuration using predetermined logic symbols. a library in which the logic symbols and detailed wiring data associated with the logic symbols are stored; and a logic circuit connection information extraction means for analyzing the logic symbol based on the logic symbol and extracting connection information of the logic circuit by analyzing the connection between the terminals of the logic symbol, based on the extraction result of the logic circuit connection information. In an integrated circuit pattern generation system that creates pattern data of an integrated circuit, the logic symbols extracted by the logic circuit connection information extraction means include a rectangular figure image and fixed wiring cells and/or macros surrounding the rectangular figure. A terminal image including a power supply and/or ground terminal, which is a terminal arranged in a predetermined positional relationship corresponding to the function of the logic block, and is based on connection information to the power supply and/or ground terminal in the logic symbol. 1. An integrated circuit pattern generation system comprising: stack cell connection processing means for processing empty terminals of the logic symbol.