JPH0520017B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a data transfer method performed between a system controller and various peripheral ICs in the audio field.

(b) Conventional technology Toshiba Review (Vol. 38, No. 13), pages 1145 to 1148
As shown on the page, even in the audio field, microcomputers are used as system controllers, and PLLIC, display ICs,
In recent years, the ability to perform total control by transferring data between various peripheral ICs such as graphic equalizers and electronic volumes has been developed.

Conventionally, in such a transfer method, as shown in FIG. When exchanging data between the two, use four serial lines, and when transferring data unilaterally to the peripheral IC2, use three serial lines.
system controller 5 and interface 3,
4 is connected, and this interface 3, 4 and
A PLL circuit 6 and a display circuit 7 were connected via a data bus 8. When transferring data from the controller side, as shown in Figure 7 A to C, first, serial data SI and clock signal CK, which are address codes C1 to C4, are sent out, and then data D1 to D4 are sent. Serial data SI and clock signal CK were sent out, and after these codes and data were transferred, a pulsed strobe signal STB was sent out. In addition, when data is to be read into the controller side, as shown in Figure 7, first send the clock signal CK and address codes C1 to C4, then send the strobe signal STB, and then read the data. In order to capture the serial data SO, which is D1 to D4, a clock signal CK was sent out, and a strobe signal STB was also sent out.

As shown in FIG. 6B, the interface 3 includes a shift register 9 that takes in serial data SI using the clock signal CK as a shift pulse and sends out the serial data SO, and a shift register 9 that uses the clock signal CK as a shift pulse and sends out the serial data SO.
and a code decoder 100 that decodes the strobe signal STB, a code latch 10 that latches the address codes C1 to C4 taken into the shift register 9 according to the output signal of the code decoder, that is, the strobe signal STB, and data D1 from the controller. ~Data from D4 or PLL circuit 6
Multiple latch circuits 11 that latch DT1 to DT4
a to 11c, and a decoder 12 for decoding the contents of the code latch 10 and addressing one of the latch circuits 11a to 11c according to the address codes C1 to C4.
When writing data D1 to D4 to any one of a to 11c, first send a clock signal to the shift register 9.
Acquire address codes C1 to C4 based on CK, address the latch circuit according to this address code, and then acquire data D1 to D4 to the shift register 9 based on the clock signal.
~D4 was written to the addressed latch circuit in response to the strobe signal STB.

(c) Problems to be solved by the invention In general, error correction processing must be performed to deal with noise during data transfer, but it takes longer time in a stationary state than in data transfer. The period is much longer, and if noise countermeasures are taken during this period, system malfunctions can be greatly reduced. However, in the above-mentioned conventional technology, the strobe signal STB and clock signal are
When noise is added to CK, erroneous data is written to the latch circuit, and the erroneous data is transferred to peripheral circuits such as PLL circuits, causing malfunctions.

Furthermore, in the conventional technology, the shift register for data input and the shift register for data output were the same, and the shift register for receiving the address code was also the same, so it was impossible to input and output at the same time. It was impossible.

(d) Means for Solving Problems The present invention sends serial data consisting of a control signal, a clock signal, an address code and input data from the system controller side, and in the first state of the control signal, the address code is and a clock signal, and after sending the control signal to the second clock signal.
Input data and a clock signal are sent during the second state, and the peripheral circuit includes a first shift register that receives an address code based on the clock signal, and a first shift register that decodes the output of the first shift register. a decoder; a second shift register that is addressed in response to a particular output of the decoder and takes in input data based on a clock signal; a first control circuit for applying a clock signal to the second shift register only during the period when the control signal is in the second state; and a third shift register for controlling the parallel output data when the control signal is in the first state. A third shift register that enables writing to the register, inhibits writing of the parallel output data to the third shift register after the control signal changes to the second state, and further enables data transfer from the third shift register. 2 control circuits.

(e) Effect In the present invention, a clock signal is applied to the second shift register for data input only while the control signal is in the second state, and application of the clock signal is prohibited during the first state, so that transfer Even if noise is added to the control signal or clock signal, the contents of the second shift register do not change. Therefore, when not during transfer, erroneous data is rarely transferred to the latch circuit due to noise. It disappears.

Furthermore, by sending an address code corresponding to a specific output of the decoder, serial transfer of input data from the system controller side to the second shift register and serial transfer of parallel output data from the third shift register to the system controller side can be performed. It becomes possible to do both at the same time.

(C) Embodiment FIGS. 1 to 3 are block diagrams showing an embodiment of the present invention, and FIGS. 4 and 5 are timing charts for explaining the operation, and correspond to the interface in the conventional technology. This shows the circuit configuration.

In this transfer method, a system controller (not shown) sends out a control signal CE, a clock signal CK, and serial data SI, and inputs serial data SO. , as shown in FIG. 4, when the control signal CE is "L", address codes C1 to C4 and four clock signals CK are sent out,
After sending, the control signal CE is set to "H", and this "H"
During this period, data D1 to D4 and four clock signals are sent out.

In FIG. 1, 13, 14, 15 are each
Serial data SI, clock signal CK, control signal
Input terminal for inputting CE, 16 is clock signal CK
17 is an AND gate 17a to 17.
A decoder 18 decodes the contents of the shift register 16, consisting of a decoder 18, which sends a control signal CE to a data terminal D, and a clock pulse φ to a clock terminal.
A D flip-flop 19 inputs the signal CED to CL and outputs the signal CED.
A D flip-flop 20 generates the write signal W, which generates the period-delayed signal CEDCL.
NOR gate, 21 is a NOR gate that generates the reset signal RST, 22a to 22e are decoders 17
The respective output signals LIS, L2S, TS, OUT, and IO are input to the data terminal, the signal CEDCL is input to the clock terminal CL, the signal RST is input to the reset terminal, and the address designation signals L1SD and IO are respectively input to the clock terminal CL.
It is a D flip-flop that outputs L2SD, TSD, OUTD, and IOD.

Next, in FIG. 2, 23 and 24 convert data D1 to D4 in the serial data SI to clock signals.
4-bit shift registers 25 and 26 for inputting data to be taken in based on CK are connected to shift registers 23 and 24, respectively, and a latch circuit 27 latches the contents of the shift register using the write signal W as a latch pulse. 28 is an AND gate that receives the signal CED and the clock signal CK; 28 is an OR gate that receives the address designation signals LISD and TSD; 29 is an OR gate that receives the address designation signals L2SD and TSD; and 30 and 31 are the OR gates that receive the IOD.
An AND gate 32 inputs the output of the AND gate 27 at one end, the outputs of the OR gates 28 and 29 at the other end, and inputs the outputs to the clock terminals FCL of the shift registers 23 and 24, respectively.
A data selection circuit consisting of AND gates 33, 34, an OR gate 35, and an inverter 36, which selectively inputs data D1 to D4 from the controller or the output of the shift register 23 to the shift register 24 according to the address designation signal TSD; 37 and 38 input the write signal W to one end, and input the write signal W to the other end, respectively.
This is an AND gate that inputs the outputs of OR gates 28 and 29 and inputs the outputs to the latch pulse input terminals L of latch circuits 25 and 26, respectively.
It is connected to peripheral circuits such as a PLL circuit via 39d and 40a to 40d.

Furthermore, in FIG. 3, 41a to 41d are
Input terminals connected to peripheral circuits such as PLL circuits and inputting data DT1 to DT4 from the peripheral circuits, 4
2 takes in data DT1 to DT4 and outputs the data from output terminal 43 using the clock signal as a shift clock.
A 4-bit shift register for data output that sends DT1 to DT4 as serial data SO to the system controller, 44 is an address designation signal
OR gate that inputs OUTD and IOD, 45 inputs signal CED and the output of OR gate 44
AND gate, 46 is an inverter that inverts the output of AND gate 45, 47a to 47d are data
Each bit signal of DT1 to DT4 DT1, DT2, DT3,
Input DT4 to one end and inverter 4 to the other end.
input the output of shift register 4, and the output is input to shift register 4.
Each flip-flop 42a to 42d constituting 2
AND gate connected to the set terminal of 48
A to 48d input the inverted signal of each bit signal of data DT1 to DT4 to one end, and input the inverter 4 to the other end.
6 is input, and the output is connected to the reset terminal of each flip-flop 42a to 42d.
It is an AND gate, and the clock signal CK is passed through an inverter 49 to the flip-flops 42a to 42d.
is applied to each clock terminal. Further, NMOS transistors 50 and 51 are connected in cascade between the output terminal 43 and the ground, and a signal obtained by inverting the output of the shift register 42 by an inverter 52 is applied to the gate of the NMOS transistor 50.
The output of the AND gate 45 is applied to the NMOS transistor 51 . The output terminal 43 is commonly connected to the output terminal 53 of other peripheral ICs and is connected to the data input terminal of the system controller, and the common connection line is connected to the power supply potential _VDD via a pull-up resistor 54.

Incidentally, the address codes C1 to C4 are codes for addressing the shift registers 23, 24, and 42, but in this embodiment, the codes for individually addressing each of the shift registers 23, 24, and 42 are "0", "1" and "2" are determined, "3" is assigned as a code for addressing both shift registers 23 and 24, and "4" is assigned as a code for addressing both shift registers 24 and 42. .

Next, the operation of this embodiment will be explained with reference to timing charts.

Now, in order to transfer data to the latch circuit 25,
Assume that address code "0" and data D1 to D4 are sent from the system controller. Then, based on the clock signal CK, the shift register 16 receives address codes C1 to C4 (0, 0, 0,
0) is taken in, and only the decoded output LISN of the AND gate 17a becomes "H" as shown in FIG. When the control signal CE is “L”, the signals CED and CEDCL are both “L”, so the reset signal
RST is at "H", and flip-flops 22a to 22e are in a reset state due to this signal. After sending the address codes C1 to C4 and the four clock signals CK, if the control signal CE is set to "H" for a predetermined period, the signal CED is output as shown in FIG.
becomes "H", so the reset signal RST becomes "L", and the flip-flops 22a to 22
The reset of e is released. Next, as shown in FIG. 4, the signal CEDCL becomes "H", and at its rising edge, the outputs of the AND gates 17a-17e are latched into the respective flip-flops 22a-22e. In this case, the decode output LIS is “H”
Therefore, as shown in Figure 4, the addressing signal
LIS becomes "H".

Control signal CE becomes "H" and signal CED becomes "H"
Then, the clock signal CK passes through the AND gate 27 and is applied to the AND gates 30 and 31, but in this case, only LISD is "H".
Therefore, the clock signal CK is applied to the shift register 23 via the AND gate 30, and the clock signal CK is not applied to the shift register 24. That is, only the shift register 23 is addressed. Therefore, during the period when the control signal CE is "H", the four clock signals CK
and data D1 to D4 are sent out, the shift register 23 transfers the data based on this clock signal CK.
Take in D1 to D4. After sending the data D1 to D4, the control signal CE is set to "L", so accordingly,
First, the signal CED becomes "L", and after one cycle of clock pulse φ, the signal CED becomes "L", so
As shown in FIG. 4, the write signal W becomes "H" in response to the fall of the signal CED, and becomes "L" after one cycle of the clock pulse has elapsed. AND gate 37
Since LISD of "H" is inputted to, when the write signal W becomes "H", the contents D1 to D4 of the shift register 23 are latched into the latch circuit 25 by its output. That is, the data transfer to the latch circuit 25 is completed.

Here, since the signal CEDCL becomes "H" after the control signal CE becomes "H" and becomes "L" when the write signal W becomes "L", the signal CEDCL becomes "L" after the control signal CE becomes "H". Until it is written to the latch circuit 25, the address designation signal LISD~
The state of the IOD never changes.

By the way, since the shift register 42 is not addressed in the above example, the signal CED
Even if the signal becomes "H", the output of the AND gate 45 becomes "L", and this signal turns off the NMOS transistor 51, so that the contents of the shift register 42 are not sent out as serial data SO.

Next, suppose address code "1" and data D1 to D4 are sent from the system controller.
Similarly, only the decode output L2S becomes "H", and in response, the address designation signal L2SD becomes "H" and the shift register 24 is addressed. In the data selection circuit 32, since the address designation signal TSD is "L", the transfer data from the system controller is transferred to the shift register 24 via the AND gate 33 and the OR gate 35.
D1-D4 are input and this data is taken in based on the clock signal. Similarly, data D1 to D4 are latched in the latch circuit 26 by the write signal W.

In the above, the operation during data transfer has been described, but it is assumed that noise is superimposed on the clock signal CK and the control signal CF while no data is being transferred.

In this case, the control signal CE becomes “H” due to noise.
It is extremely rare for noise to be added to the clock signal CK during the period when Therefore, the incorrect data is stored in the shift register 23.
and 24, thereby preventing erroneous data from being latched into latch circuits 25 and 26. Therefore, peripheral circuits such as PLL circuits will not malfunction.

Next, in the two shift registers 23 and 24,
The case where data D1 to D4 and D5 to D8 are respectively transferred will be explained.

In this case, the system controller sends "2" as the address code C1 to C4, and the control signal
After setting CE to "H", continuously transmit data D1 to D4 and D5 to D8 during this "H" period, and
Sends eight clock signals CK.

Then, only the decoded output TS becomes "H",
When the control signal CE becomes "H", the addressing signal TSD becomes "H". Addressing signal TSD
When both become "H", OR gates 28 and 29
The output of becomes “H” and AND gates 30 and 3
1, the clock signal CK can be applied to both shift registers 23 and 24. That is, 2
Two shift registers 23 and 24 will be addressed. Also, in the data selection circuit 32
Since one input signal of the AND gate 34 becomes "H", the output of the shift register 23 is input to the shift register 24 via the AND gate 34 and the OR gate 35, and the shift registers 23 and 24 are They will be connected in cascade. Therefore, when the clock signal CK is applied during the "H" period of the control signal CE, data D1 to D8 are sequentially taken in based on the clock signal, and as a result, data D1 to D8 are taken in sequentially based on the clock signal.
~D4 is transferred to the shift register 23, and the data
D5 to D8 are taken into the shift register 24. Therefore, the latch circuit 25 latches data D1 to D4, and the latch circuit 26 latches data D5 to D8. For example, when data D1 to D4 are frequency division number data and data D5 to D8 are band data, the PLL
Frequency division number data and band data are transferred to the circuit by one address specification.

Furthermore, next, data DT1 to DT1 are input from peripheral circuits such as PLL circuits via input terminals 41a to 41d.
The case where DT4 is imported and transferred to the system controller as serial data SO will be explained.

In this case, as shown in Fig. 5, first, as in the case of transferring data from the system controller, when the control signal is "L", the address code is
C1 to C4 and four clock signals CK are sent out, and after sending out, the control signal CE is set to "H", and only four clock signals CK are sent out during this "H" period. At this time, "3" is sent as address codes C1 to C4.

In this case, the address code (1, 1, 0,
0) is taken in, only the decode output OUT is “H”
However, when the control signal CE is "L", the signal
CED is “L”, so inverter 4
The output of 6 becomes "H", and the AND gate 47a~
47d and 48a to 48d are open, and each flip-flop constituting the shift register 42 is
Each is set or reset by data DT1, DT2, DT3, and DT4. That is, data
DT1 to DT4 are written to the shift register 42.
Then, when the control signal CE becomes "H", the signal CED
becomes “H” and the address designation signal
OUTD becomes "H", therefore, the output of AND gate 45 becomes "H", and the output of inverter 46 becomes "L", and AND gates 47a to 47d
and 48a to 48d are closed, and data DT1 to
Writing to the shift register 42 of DT4 is prohibited, and the NMOS transistor 51 is turned on to enable data output. clock signal CK
is applied, the shift register 42 starts a shift operation and transfers the NMOS transistor 50 to the data.
By turning on and off according to DT1 to DT4,
The data DT1 to DT4 are transferred from the output terminal 43 to the system controller as serial data SO.

Furthermore, in this embodiment, data D1 to D4 are transferred from the system controller to the shift register 24 for data input by one address specification,
At the same time, data DT1 to DT4 can be transferred from the data output shift register 42 to the system controller. In this case, as in the case of transferring data D1 to D4 from the system controller, as shown in FIG. 4, the control signal CE, clock signal CK, and serial data SI are sent, and the address codes C1 to C4 are Sends "4".

In this way, the address code (0, 0, 1, 0) is taken into the shift register 16, only the decode output IO becomes "H", and when the control signal CE is "L", the AND gate 47a-47
d and 48a to 48d are opened, and data DT1 to
DT4 is written to shift register 42. Then, when the control signal CE becomes "H", the signals CED and CEDCL become "H", and the address signal IOD becomes "H". Therefore, the clock signal CK can be applied to the shift register 24, and the data DT1 can be applied to the shift register 42.
Writing to ~DT4 is prohibited, and furthermore, the NMOS transistor 51 is turned on. Therefore, the clock signal
When CK is applied, data D1 to D4 are taken into the shift register 24, while data D1 to D54 are sent out from the shift register 42.

(g) Effect of the invention According to the present invention, except during data transfer,
Even if noise is added to the clock signal or control signal, erroneous data is almost never transferred to the second shift register.

Furthermore, serial transfer of input data to the second shift register and serial transfer of parallel output data to the third shift register can be performed at the same time.
Data input and output can be performed simultaneously between the system controller side and peripheral circuits, thus reducing transfer time.

[Brief explanation of the drawing]

Figures 1 to 3 are block diagrams showing one embodiment of the present invention, Figure 4 is a timing chart when data is transferred from the system controller to the peripheral circuit, and Figure 5 is a diagram of data transfer from the peripheral circuit to the system controller. Timing chart for transfer,
FIG. 6 is a block diagram showing a conventional data transfer system, and FIG. 7 is a timing chart showing the operation of the conventional example. Explanation of main drawing numbers, 16, 23, 24, 42...
Shift register, 17... Decoder, 25, 26
... Latch circuit, 32 ... Data selection circuit.

Claims (1)

[Claims] 1 The address code and input data for address specification are serial data, the address code and clock signal are sent in the first state of the control signal, and after sending, the control signal is set to the second state, and the control signal is in the second state. a first shift register that transmits the input data and the clock signal during a period and receives the address code based on the clock signal; a decoder that decodes the output of the first shift register; and a specific output of the decoder. a second shift register that is addressed in response to the specified output of the decoder and receives the input data based on the clock signal; and a third shift register that is addressed in response to the specific output of the decoder and transfers data based on the clock signal. a register, and applying the clock signal to the second shift register in response to the change of the control signal from the first state to the second state, the change of the control signal from the second state to the first state; a first control circuit that inhibits the application of the clock signal to the second shift register in response to the clock signal; and a first control circuit that enables writing of parallel output data to the third shift register when the control signal is in a first state; a second control circuit that inhibits writing of the parallel output data to a third shift register after the control signal changes to a second state, and further enables transfer of data from the third shift register; 1. A data transfer system, wherein serial transfer of input data to said second shift register and serial transfer of said parallel output data by said third register can be performed simultaneously.