JPH0337776B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a data transfer method performed between a system controller and various peripheral ICs in the audio field.

(b) Conventional technology As shown on pages 1145 to 1148 of Toshiba Review (Vol. 38, No. 13), in the audio field, microcomputers are used as system controllers, and PLLIC, display ICs, or graph In recent years, the ability to perform total control by transferring data between various peripheral ICs such as equalizers and electronic volumes has been developed.

Conventionally, in such a transfer method, as shown in FIG. When exchanging data between the two, use four serial lines, and when transferring data unilaterally to the peripheral IC2, use three serial lines.
system controller 5 and interface 3,
4 is connected, and this interface 3, 4 and
A PLL circuit 6 and a display circuit 7 were connected via a data bus 8. When data is transferred from the controller side, as shown in Fig. 7 A to C, first, serial data SI, which is address codes C1 to C4, and a clock signal CK are sent,
Next, serial data SI, which is data D1 to D4, and clock signal CK are sent out, and after these codes and data are transferred, a pulsed strobe signal STB is sent.
was being sent. Also, when loading data to the controller side, as shown in FIG. 7, first, the clock signal CK and address code C are
1 to C4 and the strobe signal STB, the serial data which is data D1 to D4 is transmitted.
In order to capture SO, a clock signal CK was sent out, and a strobe signal STB was sent out.

As shown in FIG. 6B, the interface 3 includes a shift register 9 that takes in serial data SI using the clock signal CK as a shift pulse and sends out the serial data SO, and a shift register 9 that uses the clock signal CK as a shift pulse and sends out the serial data SO.
and a code decoder 100 that decodes the strobe signal STB, a code latch 10 that latches the address codes C1 to C4 taken into the shift register 9 according to the output signal of the code decoder, that is, the strobe signal STB, and data D1 from the controller. ~ D4 or a plurality of latch circuits 11a to 11c that latch data DT1 to DT4 from the PLL circuit 6, and a plurality of latch circuits 11a to 11c that decode the contents of the code latch 10 and select one of the latch circuits 11a to 11c according to the address codes C1 to C4. A decoder 12 for specifying an address is provided, and data D1 is sent to any one of the latch circuits 11a to 11c.
When writing ~D4, first write address codes C1~C to the shift register 9 based on the clock signal CK.
4 and addresses the latch circuit according to this address code, then shifts register 9.
Data D1 to D4 are taken in based on the clock signal, and these data D1 to D4 are written to the addressed latch circuit in response to the strobe signal STB.

(c) Problems to be solved by the invention In general, error correction processing must be performed to deal with noise during data transfer, but it takes longer time in a stationary state than in data transfer. The period is much longer, and if noise countermeasures are taken during this period, system malfunctions can be greatly reduced. However, in the above-mentioned conventional technology, the strobe signal STB and clock signal are
When noise is added to CK, erroneous data is written to the latch circuit, and the erroneous data is transferred to peripheral circuits such as PLL circuits, causing malfunctions.

Furthermore, for example, in a PLL circuit, when changing the receiving frequency within the same band, only the frequency division number data needs to be changed, but when changing the band, both the frequency division number data and the band data must be changed. Must be. Also, with electronic volume, the left and right volume may be changed independently,
You may also want to change the left and right volumes at the same time. If you want to change two types of data at the same time like this,
Conventionally, the only way to do this was to specify the address twice and transfer the data separately, which was not a very efficient transfer method.

(d) Means for solving the problem The present invention uses serial data as the address code and data for address designation, and the first one of the control signals.
After sending the address code and the clock signal, the control signal is set to the second state, and during the second state, the data and the clock signal are sent, and the address code and the clock signal are sent out based on the clock signal. an address code input shift register for inputting a code; a decoder for decoding the output of the address code input shift register; a shift register for data input,
a control circuit for applying the clock signal to the addressed data input shift register only during a period in which the control signal is in a second state; In the data transfer method, a specific address code that simultaneously addresses at least two of the data input shift registers is assigned, and further, when a specific output of the decoder is generated in response to input of the specific address code. A selection circuit is provided in which the at least two data input shift registers are connected in cascade.

(e) Effect In the present invention, the data input shift register includes
The clock signal is applied only when the control signal is in the second state, and the application of the clock signal is prohibited during the first state, so even if noise is added to the control signal or clock signal other than during transfer, the clock signal cannot be used for data input. The contents of the shift register do not change, so no erroneous data is transferred.

Further, by transferring a specific address code, data can be continuously transferred to a plurality of data input shift registers with one address designation.

(f) Embodiment FIGS. 1 to 3 are block diagrams showing one embodiment of the present invention, and FIGS. 4 and 5 are timing charts for explaining the operation, and correspond to the interface in the conventional technology. This shows the circuit configuration.

In this transfer method, a system controller (not shown) sends out a control signal CE, a clock signal CK, and serial data SI, and inputs serial data SO. , as shown in FIG. 4, when the control signal CE is "L", address codes C1 to C4 and four clock signals CK are sent out, and after sending out, the control signal CE is set to "H", and this "H" During this period, data D1 to D4 and four clock signals are sent out.

In FIG. 1, 13, 14, 15 are each
Serial data SI, clock signal CK, control signal
Input terminal for inputting CE, 16 is clock signal CK
17 is an AND gate 17a to 1.
A decoder 7e decodes the contents of the shift register 16; 18 a D flip-flop which inputs a control signal CE to a data terminal D and a clock pulse φ to a clock terminal CL and outputs a signal CED; 19 a D flip-flop which outputs a signal CED; A D flip-flop 20 generates a write signal W, which generates a signal CEDCL delayed by one period.
NOR gate, 21 is a NOR gate that generates the reset signal RST, 22a to 22e are decoders 17
The output signals L1S, L2S, TS, OUT, IO are input to the data terminal, the signal CEDCL is input to the clock terminal CL, the signal RST is input to the reset terminal, and the address designation signal L1 is input to the reset terminal.
It is a D flip-flop that outputs SD, L2SD, TSD, OUTD, and IOD.

Next, in FIG. 2, 23 and 24 convert data D1 to D4 in the serial data SI to clock signals.
4-bit shift registers 25 and 26 for inputting data to be taken in based on CK are connected to shift registers 23 and 24, respectively, and a latch circuit 27 that latches the contents of each shift register using the write signal W as a latch pulse. 28 is an AND gate that inputs the signal CED and the clock signal CK, and 28 is an OR gate that inputs the address designation signals L1SD and TSD.
Gate 29 is the address designation signal L2SD.
OR gates 30 and 31 which input TSD and IOD input the output of AND gate 27 at one end,
The outputs of OR gates 28 and 29 are input to the other end, and the outputs are sent to shift registers 23 and 24, respectively.
AND gate, 32 input to the clock terminal CL of
consists of AND gates 33, 34, an OR gate 35, and an inverter 36, and transfers data D1 to D4 from the controller or the shift register 23 to the shift register 24 according to the address designation signal TSD.
a data selection circuit for selectively inputting the output of 37;
and 38 are AND gates which input the write signal W to one end, input the outputs of the OR gates 28 and 29 to the other end, and input the outputs to the latch pulse input terminals L of the latch circuits 25 and 26, respectively;
The output of each latch circuit 25 and 26 is connected to an output terminal 39.
PLL via a to 39d and 40a to 40d
Connected to peripheral circuits such as circuits.

Furthermore, in FIG. 3, 41a to 41d are
An input terminal connected to a peripheral circuit such as a PLL circuit and inputting data DT1 to DT4 from the peripheral circuit;
42 is a 4-bit shift register for data output that takes in data DT1 to DT4 and uses the clock signal as a shift clock to send data DT1 to DT4 from an output terminal 43 as serial data SO to the system controller; 44 is an address designation signal;
OR gate that inputs OUTD and IOD, 45 inputs signal CED and the output of OR gate 44
AND gate, 46 is an inverter that inverts the output of AND gate 45, 47a to 47d are data DT
Each bit signal DT1 to DT4 DT1, DT2, DT3,
Input DT4 to one end and inverter 4 to the other end.
6 output is input, and the output is input to shift register 4.
Each flip-flop 42a to 42d constituting 2
AND gate connected to the set terminal of 48
A to 48d are AND gates that input the inverted signal of each bit signal of data DT1 to DT4 to one end, input the output of the inverter 46 to the other end, and connect the output to the reset terminal of each flip-flop 42a to 42d. Yes, the clock signal CK is passed through the inverter 49 to the flip-flops 42a to 42.
d is applied to each clock terminal. In addition, an NMOS transistor 50 is connected between the output terminal 43 and the ground.
and 51 are connected in cascade, and a signal obtained by inverting the output of the shift register 42 by an inverter 52 is applied to the gate of the NMOS transistor 50.
The output of the AND gate 45 is applied to the NMOS transistor 51 . The output terminal 43 is commonly connected to the output terminal 53 of other peripheral ICs and is connected to the data input terminal of the system controller, and the common connection line is connected to the power supply potential _VDD via a pull-up resistor 54.

Incidentally, the address codes C1 to C4 are codes for addressing the shift registers 23, 24, and 42, but in this embodiment, the codes for individually addressing each of the shift registers 23, 24, and 42 are "0", In addition to setting "1" and "2",
"3" is assigned as a code for addressing both shift registers 23 and 24, and "4" is assigned as a code for addressing both shift registers 24 and 42.

Next, the operation of this embodiment will be explained with reference to timing charts.

Now, in order to transfer data to the latch circuit 25,
Assume that address code "0" and data D1 to D4 are sent from the system controller. Then,
Shift register 16 based on clock signal CK
For address codes C1 to C4 (0, 0,
0, 0) is taken in, and only the decoded output L1S of the AND gate 17a becomes "H" as shown in FIG. When the control signal CE is “L”, the signal
Since both CED and CEDCL are at "L", the reset signal RST is at "H", and the flip-flops 22a to 22e are in the reset state due to this signal. After sending the address codes C1 to C4 and the four clock signals CK, if the control signal CE is set to "H" for a predetermined period, the signal as shown in FIG.
CED becomes “H” and therefore the reset signal
RST becomes "L", flip-flop 22
The resets of a to 22e are released. Next, as shown in Fig. 4, the signal CEDCL becomes "H", and
At the rising edge, AND gates 17a to 17e
Each output of each flip-flop 22a to 22e
is latched to. In this case, decode output L1S
is "H", so the address designation signal L1SD becomes "H" as shown in FIG.

Control signal CE becomes "H" and signal CED becomes "H"
Then, the clock signal CK passes through the AND gate 27 and is applied to the AND gates 30 and 31, but in this case, only L1SD is "H".
Therefore, the clock signal CK is applied to the shift register 23 via the AND gate 30, and the clock signal CK is not applied to the shift register 24. That is, only the shift register 23 is addressed. Therefore, during the period when the control signal CE is "H", the four clock signals CK
When the data D1 to D4 are sent out, the shift register 23 takes in the data D1 to D4 based on this clock signal CK. After sending the data D1 to D4, the control signal CE is set to "L", so in response, the signal CED first becomes "L", and after one cycle of the clock pulse φ, the signal CEDCL becomes "L".
Therefore, as shown in Figure 4, the signal CED
The write signal W becomes "H" in response to the fall of the clock pulse, and becomes "L" after one cycle of the clock pulse has elapsed.
Since L1SD of "H" is input to the AND gate 37, when the write signal W becomes "H", its output causes the contents D1 to D4 of the shift register 23 to be input.
is latched by the latch circuit 25. That is, the data transfer to the latch circuit 25 is completed.

Here, since the signal CEDCL becomes "H" after the control signal CE becomes "H" and becomes "L" when the write signal W becomes "L", the signal CEDCL becomes "L" after the control signal CE becomes "H". Until the address designation signal L1SD is written into the latch circuit 25,
~IOD status never changes.

By the way, since the shift register 42 is not addressed in the above example, the signal CED
Even if the signal becomes "H", the output of the AND gate 45 becomes "L", and this signal turns off the NMOS transistor 51, so that the contents of the shift register 42 are not sent out as serial data SO.

Next, if address code "1" and data D1 to D4 are sent from the system controller, only the decode output L2S becomes "H" in the same way.
Accordingly, the address designation signal L2SD
becomes "H" and the shift register 24 is addressed. In the data selection circuit 32, since the address designation signal TSD is "L", the transfer data D1 to D4 from the system controller is input to the shift register 24 via the AND gate 33 and the OR gate 35, and This data is captured. Similarly, data D1 to D4 are latched in the latch circuit 26 by the write signal W.

In the above, the operation during data transfer has been described, but it is assumed that noise is superimposed on the clock signal CK and the control signal CE while no data is being transferred.

In this case, the control signal CE becomes “H” due to noise.
It is extremely rare for noise to be added to the clock signal CK during the period when Therefore, the incorrect data is stored in the shift register 23.
and 24, thereby preventing erroneous data from being latched into latch circuits 25 and 26. Therefore, peripheral circuits such as PLL circuits will not malfunction.

Next, in the two shift registers 23 and 24,
The case where data D1 to D4 and D5 to D8 are transferred will be explained.

In this case, the system controller sends "2" as address codes C1 to C4, sets the control signal CE to "H", and then continuously sends data D1 to D4 and D5 to D8 during this "H" period. death,
In addition, eight clock signals CK are sent out.

Then, only the decoded output TS becomes "H",
When the control signal CE becomes "H", the addressing signal TSD becomes "H". Addressing signal TSD
When both become "H", OR gates 28 and 29
The output of becomes “H” and AND gates 30 and 3
1, the clock signal CK can be applied to both shift registers 23 and 24. That is, 2
Two shift registers 23 and 24 will be addressed. Also, in the data selection circuit 32
Since one input signal of the AND gate 34 becomes "H", the output of the shift register 23 is input to the shift register 24 via the AND gate 34 and the OR gate 35, and the shift registers 23 and 24 are They will be connected in cascade. Therefore, when the clock signal CK is applied during the "H" period of the control signal CE, data D1 to D8 are sequentially fetched based on the clock signal, and as a result, the data D
Data 1 to D4 are taken into the shift register 23, and data D5 to D8 are taken into the shift register 24. Therefore, the latch circuit 25 receives data D1 to D.
4, data D5 to D8 are latched in the latch circuit 26. For example, when data D1 to D4 are frequency division number data and data D5 to D8 are band data, the PLL circuit can be set with one address specification.
Frequency division number data and band data will be transferred.

Furthermore, next, data DT1 to DT1 are input from peripheral circuits such as PLL circuits via input terminals 41a to 41d.
The case where DT4 is imported and transferred to the system controller as serial data SO will be explained.

In this case, as shown in FIG. 5, first, as in the case of transferring data from the system controller, when the control signal is "L", the address code C
After sending out four clock signals CK, 1 to C4, the control signal CE is set to "H", and only four clock signals CK are sent out during this "H" period. At this time, "3" is sent as address codes C1 to C4.

In this case, the address code (1, 1, 0,
0) is taken in, and only the decode output OUT is “H”
However, when the control signal CE is "L", the signal
CED is “L”, so inverter 4
The output of 6 becomes "H", and the AND gate 47a~
47d and 48a to 48d are open, and each flip-flop constituting the shift register 42 is
Each is set or reset by data DT1, DT2, DT3, and DT4. That is, data
DT1 to DT4 are written to the shift register 42. Then, when the control signal CE becomes "H", the signal
As soon as CED becomes “H”, the address designation signal
OUTD becomes "H", therefore, the output of AND gate 45 becomes "H", and the output of inverter 46 becomes "L", and AND gates 47a to 47d
and 48a to 48d are closed, and data DT1 to 48d are closed.
Writing to the shift register 42 of the DT 4 is prohibited, and the NMOS transistor 51 is turned on to enable data output. When the clock signal CK is applied, the shift register 42 starts a shift operation and transfers the NMOS transistor 50 to the data DT.
By turning on and off according to 1 to DT4,
The data DT1 to DT4 are transferred from the output terminal 43 to the system controller as serial data SO.

Furthermore, in this embodiment, data D1 to D4 are transferred from the system controller to the shift register 24 for data input by one address specification, and at the same time, the data D1 to D4 are transferred to the shift register 42 for data output.
Data DT1 to DT from to system controller
4 can be transferred. In this case, as in the case of transferring data D1 to D4 from the system controller, as shown in FIG.
CE, clock signal CK, and serial data SI are sent, and address codes C1 to C4 are "4".
Send out.

In this way, the address code (0, 0, 1, 0) is taken into the shift register 16, only the decode output IO becomes "H", and when the control signal CE is "L", the AND gate 47a-47
d and 48a to 48d are opened, and data DT1 to 48d are opened.
DT4 is written to shift register 42. Then, when the control signal CE becomes "H", the signals CED and CEDCL become "H", and the address signal IOD becomes "H". Therefore, the clock signal CK can be applied to the shift register 24, and the data DT1 can be applied to the shift register 42.
~Writing to DT4 is prohibited, and furthermore, the NMOS transistor 51 is turned on. Therefore, the clock signal
When CK is applied, data D1 to D4 are taken into the shift register 24, while data DT1 to DT4 are sent out from the shift register 42.

(g) Effect of the invention According to the present invention, except during data transfer,
Even if noise is added to the clock signal or control signal, erroneous data is almost never transferred to the data input shift register, and data can be continuously transferred to multiple data input shift registers with one address specification. Since data can be transferred efficiently, efficient data transfer can be achieved.

[Brief explanation of drawings]

Figures 1 to 3 are block diagrams showing one embodiment of the present invention, Figure 4 is a timing chart when data is transferred from the system controller to the peripheral circuit, and Figure 5 is a diagram of data transfer from the peripheral circuit to the system controller. Timing chart for transfer,
FIG. 6 is a block diagram showing a conventional data transfer system, and FIG. 7 is a timing chart showing the operation of the conventional example. Explanation of main drawing numbers, 16, 23, 24, 42...
Shift register, 17... Decoder, 25, 26
... Latch circuit, 32 ... Data selection circuit.

Claims (1)

[Scope of Claims] 1. A control signal is set in a first state to serially transmit an address code for address designation and a clock signal, and after the transmission, the control signal is set to a second state to transmit data and the clock signal. a system controller that serially sends out the address code; an address code input shift register that receives the address code based on the clock signal; a decoder that decodes the output of the address code input shift register; a plurality of data input shift registers that are each addressed and take in the data based on the clock signal; and the control signal changes from a first state to a second state in the addressed data input shift register. a control circuit that causes the clock signal to be applied in response to the clock signal and inhibits the application of the clock signal in response to the change of the control signal from the second state to the first state; In the data transfer method, a specific address code is assigned to simultaneously address at least two of the data input shift registers, and further, a specific output of the decoder is assigned in response to input of the specific address code. A selection circuit is provided to continuously connect the at least two data input shift registers when a data input signal is generated, so that data can be continuously transferred to the at least two data input shift registers with one address designation. A data transfer method characterized by: