JPH0520773B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a microprocessor equipped with a mechanism for easily performing a stack operation test.

[Technical background of the invention]

In recent years, microcomputers have rapidly become popular, and their use extends to all industrial fields. The microprocessor, which is the main component of this microcomputer, is configured as shown in Figure 1.
(abbreviated as ) 2 transfers the instruction at the address specified via the address bus 3 to the microprogram memory (hereinafter referred to as
(abbreviated as ROM) 4 and temporarily stored in the instruction register 5. The instruction register 5 executes the instruction by driving the execution circuit 6 based on the stored instruction. For example, if this instruction is an instruction to be output to an external device, the execution circuit 6
A control signal was sent from the controller via the data bus 8 to control the data register 9 and output to a predetermined external device.

A program given in this way is processed by executing instructions one by one in order, but
If this program has an instruction to jump to a predetermined address level, for example, a subroutine jump instruction, the PC 2 stores the address data of the main routine to which the subroutine jump instruction is executed and returns to after the execution is completed in stack 1. Output and memorize. Thereafter, the PC 2 jumps to the specified address of the subroutine, executes the instructions of the subroutine sequentially, and when the execution of the subroutine instructions is completed, the PC 2 transfers the address data of the address to return to, which was stored when jumping to the subroutine, from stack 1. Read the read address data and specify it to POM4,
The instruction at this address is executed, and the instructions of the main routine after this instruction are sequentially executed. By the way, as mentioned above, when sequentially executing program instructions, it is important to ensure that the program returns to the specified return destination, that is, the address stored in stack 1, after executing the instruction according to the subroutine jump instruction. Therefore, it is necessary to test whether the address stored in stack 1 corresponds to a normal program.

Conventionally, such a stack operation test is performed as shown below when executing a program having a subroutine jump instruction as shown in FIG. In other words, the program shown in FIG. 2 starts executing instructions at address 100 of the main routine, jumps to the subroutine instruction from address 500 by executing the instruction at address 103, and sequentially executes the subroutine instructions from address 500 to address 505. I'm going to go. and address 5
By executing the instruction 05, the main routine returns to address 104, and the address 1
After executing instruction 04, sequentially 105, 106...
This command means to carry out the command. Therefore, the microprocessor starts executing instructions from address 100 using the method described above, and when the instruction execution reaches address 103, PC 2 specifies this address 103 in ROM 4. Since this instruction 103 is an instruction to jump to address 500, PC2 starts searching for address 500 of the subroutine that is the jump destination, and also the address of the main routine to which to return after the subroutine has been executed from addresses 500 to 505. 104 is sent to stack 1 and stored therein, the CPU jumps to address 500, which is the destination of the search, by a predetermined operation. After that, instructions are executed sequentially starting from 500, and address 5 is sent from PC2 to ROM4.
When 05 is specified, the instruction at address 505 is stored in the instruction register 5, and the contents of this instruction are decoded. At this time, since the command at address 505 is a command to return to 104, execution circuit 6 sends a control signal to PO2 via control line 7. Therefore, when the PC 2 jumps to the subroutine, it reads the address 104 stored in the stack 1 as the return destination address from the stack 1, and specifies this address 104 to the ROM 4 via the address bus 3. after that,
The ROM 4 fetches the data of this instruction, loads it into the instruction register 5, and based on the contents of the loaded instruction, sends a control signal from the execution circuit 6 to execute the instruction at the address 104 via the data bus 8 and data register 9. . Here, the data register 9 outputs 1 from the external terminal 91 if the executed operation is due to the instruction at the address stored in the stack 1, and otherwise outputs 0 from the external terminal 90. As mentioned above, this address 104 is the address stored in stack 1 before jumping to the subroutine.
The conventional stack operation test uses this address 104.
This was done by executing an instruction and checking the address data stored in stack 1 according to the execution result.

[Problems with background technology]

According to such a conventional microprocessor, when performing a stack operation test, there is no path for extracting the address stored in the stack 1 to the outside, and the contents of the stack 1 are passed through the microprogram counter 2 to specify the address of the microprogram memory 4. The contents of stack 1 cannot be determined unless the instruction at this address is executed, and it is necessary to analyze whether the execution result of execution circuit 6 is due to the instruction at the address stored in stack 1. I had to. Therefore, in order to make the analysis as simple as possible, it is recommended to include a push instruction or a return instruction in the test program, or to connect an external connection terminal when a normal operation is performed by the instruction at the address stored in stack 1. There was a drawback that a load device was required to perform processing such as changing from 0 to 1.

[Purpose of the invention]

The present invention has been made in order to eliminate such conventional drawbacks, and does not require the above-mentioned load device for determining the quality of stack operation, reduces various considerations for test programs, and stores data in the stack. The purpose of the present invention is to provide a microprocessor equipped with a mechanism that allows easy testing of data generated by the microprocessor.

[Summary of the invention]

In the present invention, a pass line is provided between the microprogram counter or stack and a data bus connected to the output data register for directly transferring the return destination address stored in the stack to the output data register. There is.
Then, a return & transfer instruction stored at a predetermined address N of the program memory is executed, the return address stored in the stack is outputted to the path line by the return instruction, and the return destination address stored in the stack is output to the path line by the transfer instruction. The above objective is achieved by opening the gate circuit constructed inside the stack and directly reading the return destination address stored in the stack into the output register for monitoring.

[Embodiments of the invention]

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Figure 3 is a block diagram of a microprocessor showing one embodiment of the present invention, and is
A path line 11 is provided between the address bus 3 between the ROM 4 and the data register for transferring the address data stored in the stack 1, and this path line 11 is further provided with a gate that is opened and closed by a predetermined command. A circuit 10 is provided.

Further, FIG. 4 shows an example of a test program used for a stack operation test in the microprocessor shown in FIG. 3. Now, when the microprocessor is given an instruction to execute an instruction, the PC2
specifies address 100 in the ROM 4 and sequentially executes instructions from address 100 in the manner described above. When the PC 2 specifies address 103 to the ROM 4, the contents of the instruction at this address 103 are stored in the instruction register and determined. Since the instruction at address 103 is an instruction to jump to address 500 of the subroutine, the PC 2 starts searching for address 500 of the subroutine to jump to, and this is the address to return to after execution of the subroutine instruction. Stack address 104 of main routine to stack 1
, the address 104 is stored in stack 1, and then a jump is made to address 500 of the subroutine being searched. Then subroutine 50
Instructions from 0 are executed sequentially and transferred from PC2 to ROM4.
When an address 505 is designated, the ROM 4 performs a data fetch, and the instruction at this address 505 is stored in the instruction register 5, and the execution circuit 6 is driven according to the contents of this instruction. As is clear from FIG. 4, this instruction is an instruction to return to address 104 and transfer the output of PC2 to data register 9, so execution circuit 6 sends a signal to PC2 via control signal line 7. A control signal to this effect is sent out and predetermined control is performed. Here, PC2 stores the return destination address 104 in which the instruction to be executed after executing the subroutine instruction, which was stored in stack 1 before jumping to the subroutine by the instruction to return to address 104 at address 505, in stack 1. Read from. Then, this address 104 is outputted to the ROM 4 via the address bus 3 to cause the instruction from the address 104 to be executed subsequently. At the same time, the gate circuit 10 receives an instruction to transfer the output of PC2 at address 505 to data register 9.
will be released. Therefore, the output of the PC 2, that is, the return destination address data 104 stored in the stack 1 is taken into the data register 9 via the address bus 3, the pass line 11, the gate circuit 10, and the data bus 8.

Next, an appropriate test program is created, a command to jump to subroutine 505 is entered into an appropriate address, for example address 300, of this test program, and execution of this test program is started from a predetermined address. When the test program reaches address 300, the address 300 is specified from the PC 2 to the ROM 4, and the instruction at this address 300 is stored in the instruction register 5. this address 3
Since the instruction 00 is an instruction to jump to subroutine 505, the address 104 to be returned to after execution of the subroutine instruction is stored in stack 1 by the same operation as described above, and then the instruction of subroutine 505 is executed. The command at address 505 is a command to return to address 104 and transfer the output of PC2 to data register 9, so execution circuit 6 executes this command. First, on PC2, from stack 1 to return address 10
4 and sends this address 104 to the address bus 3.

At this time, since the gate circuit 10 is opened by the above-mentioned transfer command, the output of this PC2, that is, the storage address 104 of the stack 1, is sent to the data register 9 via the address bus 3 pass line 11 gate circuit 10 and data bus 8. It is captured.
In this way, any address n in the test program
Add a subroutine jump instruction to address N
The contents of stack 1 can be easily loaded into data register 9 by jumping to address N, storing a return & transfer instruction at address N, and executing the instruction from an address close to address n.
Furthermore, in the embodiment described above, a path line 11 is provided between the address bus and the data register between the PC 2 and the ROM 4.
The explanation has been given on a method in which the output of PC2 is directly taken into the data register 9, but as shown in FIG. The same effect can be obtained by directly taking the output of the stack 1 into the data register 9.

At this time, an instruction to return to 104 and transfer the output of stack 1 to data register 9 is set in address 505 of the program shown in FIG.
Jump to 5. The return address 104 previously stored in the PC 2 is output from the stack 1 by the return command from the execution circuit 6, and at the same time, the gate circuit 10 is opened by the transfer command, so the pass line 12 and the gate circuit 10 are , the contents of this stack 1 can be taken directly into the data register 9 via the data bus 8. For example, address 1 of the program shown in FIG.
By adding a transfer instruction to the instruction to jump to address 500 of 03 and executing the instruction 103, address data 500 output from PC 2 and stack 1 can be taken into the data register via gate circuit 9. Therefore, it is possible to easily test jump instructions as well.

〔Effect of the invention〕

As explained above, according to the microprocessor equipped with the functions according to the present invention, a subroutine jump instruction can be placed at an appropriate address N, the jump is made to address N, and a return & transfer instruction is placed at this address N and executed. This makes it possible to easily test the stack, and has the excellent effect of eliminating the need for conventional methods such as incorporating push commands and return commands into the test program, and eliminating the need for a load device to determine the quality of stack operation.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional microprocessor, FIG. 2 is a diagram showing an example of a program used for a conventional stack operation test, and FIGS. 3 and 5 are microprocessor blocks showing an embodiment of the present invention. FIG. 4, a block diagram of the processor, is a diagram showing an example of a program related to the microprocessor of the present invention. 1... Stack, 2... Micro program counter, 4... Micro program memory, 5... Instruction register, 6... Execution circuit, 9... Data register, 1
0...Gate circuit.

Claims (1)

[Scope of Claims] 1. A program memory that stores a predetermined operating program, a program counter that specifies an address to the program memory, and an instruction that reads and stores an instruction at an address specified by the program counter from the program memory. A register, a stack that stores a return address or jump address for executing a return, loop, or jump instruction, and a stack that directly transfers the return or jump address stored in the stack to the output data register. A pass line for executing the instruction stored in the instruction register, and if the instruction to be executed is the return instruction, loop instruction, or jump instruction, storing it in the stack at the same time as each instruction is executed. and instruction execution means for outputting a return destination address or a jump destination address to the pass line. 2. The pass line is connected to the program counter,
2. The microprocessor according to claim 1, wherein the microprocessor is connected between the output data register and a data bus connected to the output data register. 3. The microprocessor according to claim 1, wherein a pass line is connected between the stack and a data bus connected to the output data register. 4. Any one of claims 1 to 3, wherein the pass line has a gate circuit that is opened by executing a transfer instruction added to the return instruction, loop instruction, or jump instruction. The microprocessor described in .