JPH0520838B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention is provided with a voltage booster circuit, and when a memory cell is selected, the voltage booster circuit supplies a voltage higher than a power supply voltage to a selection line of the memory cell. The present invention relates to a semiconductor memory device configured to do so.

[Technical Background of the Invention] In semiconductor memory devices, especially dynamic RAM (random access memory), it is necessary to bring the write voltage of memory cells sufficiently close to the power supply voltage in order to increase the operating speed and increase the data read margin. Therefore, there is a device that provides a voltage booster circuit and outputs a voltage boosted to a level higher than the power supply voltage to a selected word line.

The structure of a conventional semiconductor memory device provided with such a voltage booster circuit is shown in the block diagram of FIG. In the figure, 10 is for example each one for selection.
This is a memory cell array provided with a plurality of dynamic memory cells each consisting of a MOS transistor and a data storage capacitor. The memory cells provided in this memory cell array 10 are connected to one of a plurality of word lines 11, so that when that word line is driven, all the memory cells connected to it are simultaneously selected. It's getting old. 12 is the word line 1 according to the address signal.
This is a row decoder that selects 1. The row decoder 12 is supplied with an output signal OUT boosted to a power supply voltage or higher by a voltage booster circuit 13, and the row decoder 12 drives the word line 11 selected according to the address signal with this signal OUT. The voltage booster circuit 13 is supplied with input signals IN such as RAS (row address strobe signal) and control signals for auto-refresh operation.
The voltage booster circuit 13 outputs a signal OUT boosted above the power supply voltage when the level of the input signal IN changes. Although not shown, the memory cells in the memory cell array 10 are connected to a sense amplifier circuit for each word line via each pair of bit lines, and this sense amplifier circuit is further connected to a column decoder to select a bit line. word line 1
The data stored in the memory cell connected to No. 1 is sensed by the sense amplifier circuit, and some of the data is selected by the column decoder. Data reading is performed by outputting the data selected by the column decoder to the outside, and data writing is performed by supplying new write data to the column decoder.

In this way, by supplying a boosted high voltage to the selected word line 11, the speed at which data is read from the selected memory cell can be increased, or the impedance of the selection transistor of the memory cell can be increased. can be lowered to charge the storage capacitor to a voltage sufficiently close to the supply voltage.

FIG. 8 is a circuit diagram showing a specific configuration of a voltage booster circuit used in the semiconductor memory device of FIG. 7, and FIG. 9 is a timing chart thereof. In this circuit, the node N1 is charged in advance to a potential lower than the power supply voltage _VDD by the threshold voltage _VTH of the N-channel MOS transistor via the N-channel MOS transistor 20 serving as a load MOS transistor. When the input signal IN is at a low potential (V _SS ), the voltage at the node N1 is boosted by the capacitor 21 to V _DD + ΔV2 (where ΔV2 is a voltage sufficiently larger than the threshold voltage V _TH of the N-channel MOS transistor). . The N-channel MOS transistor 22 is turned on by the potential of the node N1, and the capacitor 23 charges the node N2 via the transistor 22 until the node N2 reaches the power supply potential _VDD . Also at this time, the output control signal
CONT1 is brought to V _SS and CONT2 is brought to V _DD , and the signal
CONT1 allows N-channel MOS transistor 2
4 is off, N channel by signal CONT2
Since the MOS transistor 25 is on, the potential of the signal OUT at the output node N3 is V _SS .

When the input signal IN rises from V _SS to V _DD , the output of the inverter 26 is inverted from V _DD to V _SS , and as a result, the node N1 decreases from V _DD +ΔV2 to V _DD −V _TH due to the coupling by the capacitor 21 . This turns off transistor 22. Furthermore, the output of inverter 27 changes from V _SS to V _DD , and the node
N2 is coupled by the capacitor 23 and boosted from V _DD to V _DD +ΔV1. As the input signal IN rises, the output control signal CONT1 changes from V _SS to V _DD
and then enters a high impedance state. As a result, transistor 24 is first turned on, and node N2
The potential is output from output node N3 as output signal OUT. Next, when the signal CONT1 becomes a high impedance state, the transistor 2
The gate potential of No. 4 is boosted. As a result, the transistor 24 operates as a triode, and the node is boosted.
The potential V _DD +ΔV1 of N2 is output as is to the output node N3. The output control signal CONT2 is the input signal
As IN rises, V _DD changes to V _SS ,
This turns off transistor 25.

Next, when the input signal IN changes from V _DD to V _SS ,
Output control signal CONT1 is V _SS , output control signal
CONT2 goes to V _DD , which turns off transistor 24 and turns on transistor 25, so that output node N3 is discharged by transistor 25 to V _SS . On the other hand, the output of the inverter 26 becomes V _DD and the output of the inverter 27 becomes V _SS , and the node N1 is again boosted to V _DD +ΔV2, which turns on the transistor 22 and charges the capacitor 23 .

Here, after discharging the capacitor 23, the node
The potential of N2 drops to about 1/2V _DD or 2/3V _DD . The time t1 required to charge this potential to about V _DD depends on the element dimensions of the transistor 22, but is usually about 20 to 30 ns at the fastest.

[Problems with the Background Art] By the way, in a conventional storage device as shown in FIG. It takes 20ns to 30ns to do this.

If such a time interval is not taken and the next operation is started with insufficient charging, the word line potential will be low, the conductance of the memory cell selection transistor will be small, and the bit line will not have enough power. The sense amplifier circuit operates before a potential difference occurs, which causes malfunction, and the write voltage of the storage capacitor decreases, resulting in data loss due to a reduction in data retention time and an increase in the soft error rate. Therefore, even if other circuits can operate during this charging time, they cannot proceed to the next operation. Therefore, there is a drawback that the cycle time becomes longer by the charging time in the capacitor 23.

Recently, dynamic RAMs have been developed that have an internal address counter and an auto-refresh function that allows refreshing to be performed without applying an external address. like this
In the RAM, normal data write and read operations (hereinafter such operations will be referred to as normal operations) and refresh operations can be performed as separate operations. Therefore, in order to shorten the refresh time, it is conceivable to divide the memory cell array into columns and simultaneously drive more word lines than during normal operation. However, in the voltage booster circuit used in conventional memory devices, the boosted potential actually applied to the word line exists in the capacitance of the capacitor 23 in FIG. 8 and the path from the output node N3 to the word line. Since it is determined by the ratio to the parasitic capacitance, if you try to drive more word lines during refresh operation than during normal operation, the word line potential will be insufficient during refresh operation when the capacitance of the capacitor 23 is adjusted to normal operation. , data loss, increased soft error rate, etc. occur. On the other hand, when the capacitance of the capacitor 23 is adjusted to the refresh operation, the word line potential during normal operation becomes higher than necessary, and the gate oxide film of the selection MOS transistor in the memory cell or the gate oxide film in the row decoder increases.
The reliability of MOS transistors deteriorates significantly.

Therefore, in the conventional memory device, there is a problem in that it is not possible to drive different numbers of word lines in normal operation and refresh operation.

[Objective of the Invention] The present invention has been made in consideration of the above-mentioned circumstances, and its purpose is to enable continuous data writing or reading operations to be performed at high speed, or to enable a refresh operation. It is an object of the present invention to provide a semiconductor memory device which can reduce the time required for refreshing when performing an operation compared to the conventional semiconductor memory device.

[Summary of the invention] In order to achieve the above object, this invention has the following features:
By preparing two voltage boosting circuits and operating these two voltage boosting circuits alternately, it is possible to perform data writing or reading continuously at high speed. One of them is used during data write and read operations, and the other is used during refresh operations, thereby reducing the time required for refresh.

[Embodiment of the Invention] An embodiment of the invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a semiconductor memory device according to the present invention.

In FIG. 1, numeral 10 is a memory cell array provided with a plurality of dynamic memory cells as in the conventional case. The memory cells provided in this memory cell array 10 are connected to one of a plurality of word lines 11. A row decoder 12 selects the word line 11 according to an address signal. This row decoder 12 includes a first voltage boosting circuit 13A and a second voltage boosting circuit 13B.
A signal boosted above the power supply voltage on either one of the
OUT is supplied, and this row decoder 12
drives the word line 11 selected according to the address signal with this boosted signal OUT. The first voltage booster circuit 13A and the second voltage booster circuit 13B
input signal IN via the input signal switching circuit 14.
is now input as IN1 or IN2. Input signal of the input signal switching circuit 14
As IN, RAS (row address strobe signal), control signals for auto-refresh operation, etc. are supplied. The first and second voltage boosting circuits 13A and 13B each boost the power supply voltage and output it as a signal OUT when the level of the input signal IN1 or IN2 changes.

FIG. 2 shows the first and second voltage booster circuits 1.
3A and 13B are circuit diagrams showing specific configurations.
These first and second voltage booster circuits 13A, 13
Each of the voltage boosting circuits B has the same structure as the voltage boosting circuit shown in FIG. 8, except for the MOS transistor 25, and the eighth
For the portions corresponding to the circuit shown in the figure, an alphanumeric character A is added to the suffix of the symbol, and similarly, for the portion corresponding to the circuit of FIG. Add. and first and second voltage booster circuits 13
In A and 13B, output nodes N3 and N3B for obtaining a signal OUT are commonly connected, and a MOS transistor 25 is connected to this commonly connected output node N3C. The gate of this MOS transistor 25 is supplied with an output control signal CONT2 having a negative phase relationship with the input signal IN. Furthermore, the first voltage booster circuit 1
The output control signal CONT11 is applied to the gate of the 3A transistor 24A, and the output control signal CONT11 is applied to the gate of the 3A transistor 24A.
The output control signal is applied to the gate of the transistor 24B.
CONT22 is supplied to each inverter 2 of the first voltage booster circuit 13A.
6A is supplied with IN1 as an input signal, and IN2 is supplied as an input signal with the inverter 26B of the second voltage boosting circuit 13B.

FIG. 3 is a circuit diagram showing a specific configuration of the input switching circuit 14. This circuit 14 is composed of a pair of AND gate circuits 31 and 32 and a toggle flip-flop circuit 33. The input signal IN is supplied in parallel to one input terminal of each of the AND gate circuits 31 and 32. The other input terminal of the AND gate circuit 31 is supplied with the Q output of the flip-flop circuit 33. The output of the flip-flop circuit 33 is supplied to the other input terminal of the AND gate circuit 32. A "1" level (V _DD ) is always supplied to the toggle input (T) of the flip-flop circuit 33, and the clock input (CP) has a cycle corresponding to one data write operation period or read operation period. A clock pulse φ having a clock pulse φ is supplied.

A storage device configured in this manner is designed to speed up data writing or reading operations in a continuous manner.
The operation will be explained using the timing chart shown in FIG. First, in the circuit shown in Figure 3, the clock pulse φ
Q of the flip-flop circuit 33 is
The output and the output are alternately set to the "1" level. Therefore, the pair of AND gate circuits 31, 3
The input signal IN is alternately switched through the input terminal 2, and the signals IN1 and IN2 are alternately set to the "1" level. For example, if the input signal IN rises to the "1" level at a certain timing and one of the signals IN1 is thereby set to the "1" level, this signal IN1 causes the first voltage booster circuit 13 to
A operates, and the potential boosted to V _DD +ΔV1 is obtained at its internal node N2A as described above.
As the input signal IN rises, the output control signal
CONT11 goes from V _SS to V _DD and then goes into a high impedance state. As a result, the transistor 24A
is turned on first, and the potential of node N2A is output from common output node N3C. Next signal CONT11
becomes a high impedance state, capacitor 2
By coupling with 8A, transistor 2
4A is boosted, transistor 24A operates as a triode, and the boosted potential V _DD +ΔV1 of node N2A is directly output to common output node N3C. The output control signal CONT2 is
As the input signal IN rises, it changes from _VDD to _VSS , thereby turning off the transistor 25.

Next, when the input signal IN drops to “0” level,
Transistor 24A turns off and transistor 25
turns on, then the common output node N3C
The potential at will drop to V _SS . At this time, the output of inverter 27A is inverted to V _SS , so node N2A
The potential at node N2A decreases from V _DD +ΔV1 to 1/2V _DD or 2/3V _DD , and this node N2A is connected to transistor 24A.
It enters the charging state by

Next, when the input signal IN rises to the "1" level, the other signal IN2 is set to the "1" level. Therefore, this signal IN2 operates the second voltage booster circuit 13B, and then the node
As mentioned above, a potential boosted to V _DD +ΔV1 is obtained at N2B, and this potential is applied to the common output node N3C.
is output from. During this period, the first voltage booster circuit 13A continues to charge the capacitor 13A, and the charging is completed while the second voltage booster circuit 13B is operating. Below, the first and second
By alternately operating the voltage boosting circuits 13A and 13B, the first and second voltage boosting circuits 13
The period of the boosted signal (OUT) obtained at the common output node N3C of A, 13 can be shortened to about half that of the signal shown in FIG.

In this way, the first and second voltage booster circuits 1
While one of 3A and 13B is in operation, the capacitor 23 is being charged in the other, so the voltage booster circuit 1
There is no need for waiting time for charging as in the conventional case in 3A and 13B. Therefore, the cycle time is shortened compared to the conventional method, and it is possible to operate at higher speed.

FIG. 5 is a circuit diagram showing a specific configuration of the input signal switching circuit 14 according to another embodiment of the invention.
This switching circuit is used in place of the switching circuit shown in FIG. 3 when attempting to shorten the time required for refresh operation in the storage device of the present invention. And this circuit consists of a pair of AND gate circuits 4
1 and 42 and an inverter 44. An input signal IN is supplied in parallel to one input terminal of each of the AND gate circuits 41 and 42. The other input terminal of the AND gate circuit 41 is directly supplied with a switching signal N/ which is set to "1" level during normal operation and set to "0" level during refresh operation. This switching signal N/ is supplied to the end via the inverter 43. That is, if such an input signal switching circuit is used, the input signal IN is output as the signal IN1 through the AND gate circuit 41 during normal operation, and the input signal IN is output as the signal IN2 through the AND gate circuit 42 during the refresh operation. is output as Therefore, in this case, the first voltage booster circuit 13A can be used as a voltage booster circuit exclusively for normal operation, and the second voltage booster circuit 13B can be used as a voltage booster circuit exclusively for refresh operation.

Here, if the capacitance of the capacitor 23B in the 24th voltage booster circuit 13B is set larger than that of the capacitor 23A in the first voltage booster circuit 13A, more words can be used during the refresh operation than during the normal operation. Lines can be driven simultaneously. As a result, in the case of column-divided RAM, more memory cells can be refreshed in one refresh operation, and the time required for refresh can be shortened.

In addition, when performing normal operation, it is only necessary to drive one word line, which is the minimum necessary, so the first voltage booster circuit 13 dedicated for normal operation is used.
In A, a small capacitor 23A can be used, which has the effect of reducing power consumption.

If the signal switching circuit 14 is configured to switch the input signal IN between normal operation and refresh operation, the first and second voltage boosting circuits 1
3A and 13B can be optimally designed for normal operation and refresh operation, respectively.

By the way, when the first and second voltage booster circuits 13A and 13B are used exclusively for normal operation and refresh operation as in the above embodiment,
When only the refresh operation is performed and the normal operation is not performed for a long time, the node N1A in the first voltage booster circuit 13A for normal operation is
remains unattended for a long time. At this time, when the potential of this node N1A gradually decreases due to leakage current and becomes below V _DD , the potential of node N2A decreases.
It will only be charged up to V _DD −V _TH . If the first voltage booster circuit 13A operates in such a potential state, a sufficient boosted voltage may not be obtained at the output node N3A, and the effects of the present invention may not be fully exhibited. Therefore, in such a case, as shown in the embodiment circuit of FIG. 6, the node of the first voltage booster circuit 13A for normal operation is
Connect one end of capacitor 29 to N1A,
The other end of this capacitor 29 is supplied with an input signal IN2 that is supplied to the second voltage boosting circuit 13B.

According to such a configuration, even if the normal operation is not performed for a long time and the node N1A in the first voltage booster circuit 13A for normal operation is left unused for a long time, the signal IN2 is used when the refresh operation is performed. Therefore, the potential of node N1A is capacitor 2
It rises each time by coupling with 9. As a result, the transistor 22A is turned on, and the capacitor 23A is charged via the transistor 22A, so that the above-mentioned problem does not occur.

[Effects of the Invention] As explained above, according to the present invention, when data is continuously written or read, it can be performed at high speed, or when a refresh operation is performed, the refresh operation can be performed at high speed. It is possible to provide a semiconductor memory device that can take less time than conventional ones.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a configuration according to an embodiment of the present invention, FIGS. 2 and 3 are circuit diagrams specifically showing a part of the above embodiment circuit, and FIG. 4 is a circuit diagram of the above embodiment circuit. FIG. 5 is a circuit diagram according to another embodiment of the invention, FIG. 6 is a circuit diagram according to still another embodiment of the invention, and FIG.
The figure is a block diagram of a conventional semiconductor memory device, FIG. 8 is a circuit diagram showing a specific configuration of a voltage booster circuit used in the semiconductor memory device of FIG. 7 above, and FIG. 9 is a timing diagram of the circuit of FIG. 7 above. It's a chat. 10...Memory cell array, 11...Word line, 12...Row decoder, 13A, 13B...
Voltage booster circuit, 14...signal switching circuit.

Claims (1)

[Scope of Claims] 1. A memory cell array provided with a plurality of memory cells, a word line for selecting a memory cell in the memory cell array, a word line selection circuit for selectively driving the word line, and a normal data writing circuit. and a first voltage booster circuit that is controlled to operate during reading and boosts the power supply voltage and supplies it to the word line selection circuit; and a first voltage booster circuit that is controlled to operate during refresh and boosts the power supply voltage to supply the voltage to the word line A semiconductor memory device comprising: a second voltage booster circuit that supplies a voltage to a selection circuit. 2. The first and second voltage boosting circuits each include at least a first inverting circuit to which an input signal input during normal data writing and reading or refreshing is supplied, and an output terminal of the first inverting circuit. a first capacitor to which one end is connected; a first node to which the other end of the first capacitor is connected; a load transistor inserted between the first node and a power supply; a second inverting circuit whose input terminal is connected to the output terminal of the inverting circuit; a second capacitor whose one end is connected to the output terminal of the second inverting circuit; and a second capacitor whose other end is connected to the output terminal of the second inverting circuit. a second node connected to obtain a boosted voltage; and a transistor with a current path inserted between the second node and a power supply and a control end connected to the first node. A semiconductor memory device according to claim 1. 3. A memory cell array provided with a plurality of memory cells, a word line that selects a memory cell in the memory cell array, a word line selection circuit that selects and drives the word line, and a word line selection circuit that operates during normal data writing and reading. a first voltage booster circuit that is controlled to boost the power supply voltage and supply it to the word line selection circuit; and a first voltage booster circuit that is controlled to operate during refresh and boosts the power supply voltage and supplies it to the word line selection circuit. The first voltage booster circuit includes a first inverter circuit to which an input signal input during normal data writing and reading is supplied, and an output terminal of the first inverter circuit. a first capacitor having one end connected to the first capacitor, a first node having the other end connected to the first capacitor, and a first load transistor inserted between the first node and a power supply; , a second inverting circuit whose input terminal is connected to the output terminal of the first inverting circuit; a second capacitor whose one end is connected to the output terminal of the second inverting circuit; and this second capacitor. the other end is connected to a second node for obtaining a boosted voltage, a current path is inserted between this second node and the power supply, and a control end is connected to the first node. The second voltage booster circuit is composed of a first transistor and a third capacitor, one end of which is supplied with an input signal input during refreshing, and the other end of which is connected to the first node. a third inverting circuit to which an input signal input during data writing and reading is supplied; a fourth capacitor having one end connected to the output terminal of the third inverting circuit; and a fourth capacitor having the other end connected to the output terminal of the third inverting circuit. a fourth inverter whose input end is connected to the output end of the third inverter circuit; a second load transistor inserted between the third node and the power supply; a fifth capacitor having one end connected to the output end of the fourth inverting circuit; a fourth node to which the other end of the fifth capacitor is connected to obtain a boosted voltage; A semiconductor memory device characterized in that a current path is inserted between the fourth node and a power supply, and a second transistor has a control end connected to the third node.