JPH052094B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention converts the peak value of a particle detection signal indicating the particle size into a digital value as a preprocessing for particle analysis to measure the particle size of particles such as blood cells. The present invention relates to a particle detection signal processing device that performs processing such as processing.

[Conventional technology]

As a device to measure the particle size of particles such as blood cells,
There is a conductive particle detection device. In the conductive particle detection device, particles are detected as follows. A suspension of measurement particles is created in a thin electrolyte solution with a salt concentration of about 0.8%, and a pair of electrodes separated by an insulating wall with micropores is immersed in the suspension. Then, a potential difference is applied between the pair of electrodes,
A current is allowed to flow between the electrodes only through the micropores, a water pressure difference is applied between the liquid separated by the insulating wall, and the particles flow together with the liquid through the micropores. At this time, if the micropore diameter is appropriately selected relative to the particle diameter, a current change proportional to the volume of the flowing particles will occur between the electrodes. The particle size of the measurement particles is determined from the particle detection signal indicating the current change.

The particle detection signal obtained as described above is A/D (analog/digital) converted in the particle detection signal processing device according to the present invention, and is inputted to the analysis device as analysis data. In the analyzer, the analysis data is processed by a microcomputer or the like, and the processing results, such as particle size distribution information, are output to a particle size recording device or the like.

Information processing in which multiple analog signals such as pressure and temperature are subjected to analog multiplex processing, the processed signals are A/D converted, and the data is input into a computer is well known. Such processing of a plurality of high-frequency analog signals has not yet been generally performed. Physical quantities such as pressure, temperature, and light used to monitor the operating status of a device or facility or the surrounding environment generally do not change rapidly on a second-by-second basis. Therefore, the computer calculates the physical quantity A/
D conversion can be commanded and the data can be imported into the computer. However, when attempting to obtain, for example, particle size distribution information from a particle detection signal, it is necessary to detect the peak of the particle detection signal in real time, hold the peak value, and perform A/D conversion. The timing for A/D converting the particle detection signal is the time when its peak is detected, and cannot be set at an arbitrary time point like when analog signals such as pressure, temperature, and light are A/D converted.

For these reasons, it is difficult to time-divide and A/D convert multiple types of particle detection signals that are input simultaneously.

[Problem that the invention seeks to solve]

Therefore, when analyzing multiple types of particles, conventionally a high-speed A/D converter is individually provided for each input particle detection signal, and the converted data is individually sent to the analyzer. Store in the provided memory. Further, the converted data is given to the memory as an address, and each time the contents of the address are read, an increment process is performed to add +1 to obtain particle size distribution data on the memory. To perform such processing, multiple controllers are required to control access to each A/D converter and each memory.
PROM that stores the CPU and its processing programs
etc. are required. Therefore, as the number of types of particles to be treated increases, the number of components increases and the cost increases.

An object of the present invention is to provide a particle detection signal processing device that can input a plurality of types of particle detection signals and process them with an inexpensive configuration.

[Means for solving problems]

The present invention includes a plurality of peak detection means for individually inputting a plurality of types of particle detection signals having peaks corresponding to particle sizes and detecting the peaks; a plurality of peak value holding means for holding the peak values in response to peak detection signals from the plurality of peak detection means; A plurality of analog/digital conversion means for converting into digital values, and a sequential selection and operation of the conversion outputs so that a plurality of conversion outputs are derived in a time-sharing manner for the plurality of analog/digital conversion means. and a selection means for sorting and outputting the conversion data from the plurality of analog/digital conversion means according to particle type in response to the selection operation of the conversion output selection means. be.

[Effect]

According to this invention, each peak of a plurality of types of particle detection signals is detected, each peak value is individually held, each peak value is converted to a digital value, and the conversion output selection means is configured to perform analog/digital conversion. The conversion data is sequentially selected by the conversion output means so as to time-share the conversion output, and the output recommendation means selects the conversion data from the analog/digital conversion means in response to the selection operation of the conversion output selection means. By sorting and outputting data by particle type, particle detection signals can be processed quickly with a simple configuration even when there are many types of particles to be processed, and converted data can be output by particle type. be able to.

〔Example〕

An embodiment of the present invention will be described based on FIGS. 1 and 2. FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is a timing chart for explaining its operation.

Particle detection signals S1, S2, and S3 having peaks corresponding to particle sizes are input to sample hold circuits 1, 2, and 3, which are peak value holding means, respectively, and peak detection means 4, 5, and 6.
are also entered respectively.

When a peak is detected by each peak detection means 4 to 6, peak detection signals HLD1 to HLD3 are given to sample and hold circuits 1 to 3, and particle detection signal S
The peak values of 1 to S3 are retained. The held peak value signals SH1 to H3 are given from sample and hold circuits 1 to 3 to A/D converters 7 to 9,
A/D conversion is started by inputting peak detection signals HLD1 to HLD3.

The components included in the conversion output selection means HS will be described below. Peak detection signal HLD1~
When HLD3 is given and A/D conversion is completed,
Conversion completion signals RDY1 to RDY3 indicating completion from each A/D converter 7 to 9 are sent to AND gates 10 to 11.
2 is output. The conversion completion signal RDY1 is shown in FIG. 21, and the conversion completion signal RDY2 is shown in FIG. 2.

On the other hand, the clock signal output from the clock signal generation circuit 12 is frequency-divided by the frequency divider 13, and the frequency is divided by the frequency divider 13.
Counter 1 is used as the clock signal CK shown in (3).
4 is given. This counter 14 receives particle detection signals S1 to S3 based on the clock signal CK.
2-bit identification code signal CD for identifying
Derive 0, CD1. The identification code signal CD0 is shown in FIG. 2, and the identification code signal CD1 is shown in FIG. 2.

The decoder 15 to which the identification code signals CD0 and CD1 are input derives selection signals 1 to 3 for selecting particle detection signals S1 to S3 and a signal 0 indicating that the selection process is in progress. Signal E0 is shown in FIG. 2, and select signals 1-3 are shown in FIGS. 7-9. The selection signals 1 to 3 are sent to the A/D converter 7.
-9, AND gates 10-12, flag reset circuit 16 and gate circuit 17, respectively.

The A/D converters 7-9 output converted data based on the input selection signals 1-3. For example, the A/D converter outputs a conversion output to the data selector DS only when the input selection signal E1 is at a low level.

Each AND gate 10 to 12 receives each input selection signal E1 to E3 and each conversion completion signal described above.
Only when RDY1 to RDY3 are both at high level, the output is set to high level and is applied to each data ready flag 18 to 20. Each conversion ready flag 18-20 is set when the output of the AND gates 10-12 changes from low level to high level, that is, when A/D conversion is completed in A/D converters 7-9. When the flag is not set, the A/D conversion prohibition signal NOT1 is sent from the data ready flags 18 to 20 to the A/D converters 7 to 9.
~NOT3 is output. In the A/D converters 7 to 9, A/D conversion operations are prohibited while the conversion inhibition signals NOT1 to NOT3 are input. When the flag is set, data ready flag 18-20
The A/D converters 7 to 9 output signals A to C, which are at low level while deriving the converted output, to the gate circuit 17. Signals A and B are shown in FIGS. 10 and 11.

The gate circuit 17 includes OR gates 17a to 17c.
and NMND gate 17d.
The OR gates 17a-17c are connected to selection signals E1-E.
3 and signals A to C, and their logical sum signals D to F
The output signal G is sent to the time flag circuit 2.
Output to 1. The OR signals D and E are as shown in FIG.
13, and the output signal G is shown in FIG. 2, 14.

The time flag circuit 21 outputs a pulse signal H as shown in FIG. 2 to the shift register 22 at the rising edge of the output signal G.

When the shift register 22 receives the pulse signal H in synchronization with the clock signal CLK, the shift register 22 outputs the readout signal shown in FIG. 16 via the NOR gate 23.
RD is output to the memory of the analyzer AN, and after a delay of several clock pulses, the write signal shown in Figure 2 17 is generated.
Output WR to analyzer AN memory. When the output of the write signal is finished, the shift register 22
outputs the reset signal shown in FIG. 2 to the flag reset circuit 16.

The flag reset circuit 16 is an OR gate 16a.
16c and AND gates 16d to 23f. The flag reset circuit 16 receives a reset signal, selection signals 1-3, and signals C1-C3 indicating that the CPU of the analyzer AN starts/stops particle counting. Signals C1 and C2 are shown in FIGS. 19 and 20. When the processing of the A/D converted data is completed, the data ready flags 18 to 20 are set by the reset signal.
flag is reset. Also, when particles are not being counted, this flag is forcibly reset.

The data selector DS converts the conversion data given from the A/D converters 7 to 9 into identification code signals CD0,
Select by CD1, set the identification code to the upper address of the memory of the analyzer AN, and give the converted data to the memory of the analyzer AN.

In the analyzer AN, when an address is output from the data selector DS, the data stored at that address in the memory is read out using a read signal, incremented by 1, and the value is written to the same address using a write signal. . During this increment process, the signal 0 from the decoder 15 becomes high level, and the CPU of the analyzer AN cannot access data in the memory. Analyzer AN
When the CPU accesses data, the port access signal shown in FIG. 21 is output to the counter 14, the signal 0 becomes low level, and the particle detection signal processing is interrupted.

Through the operations described above, data indicating the particle size distribution for each type of particle detection signals S1 to S3 is accumulated in the memory of the analyzer AN, and when the counting is completed, the data is read out from the memory and its A particle size distribution map is created based on the data.

In the above embodiment, the data selector DS selects A/
The converted data output from the D converters 7 to 9 is sorted by type using the identification codes CD0 and CD1, and this converted data is given as the upper address of the memory of the analyzer AN. Does not require multiple memories. Therefore, the structure of the analyzer AN is not complicated, and it is small and inexpensive.

〔Effect of the invention〕

According to this invention, conversion data from a plurality of A/D converters are sequentially selected and output by type, so that a plurality of types of particle detection signals can be processed quickly with a simple configuration.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is a timing chart for explaining the operation of the present invention. 1-3...Sample hold circuit (peak value holding means), 4-6...Peak detection means, 7-9...A/
D converter (analog/digital conversion means), 14
...Counter, 15...Decoder, 16...Flag reset circuit, 18-20...Data ready flag,
DS...Data selector (output selection means), HS...Conversion output selection means, AN...Analyzer, S1 to S3...
Particle detection signal.

Claims (1)

[Claims] 1. A plurality of peak detection means for individually inputting a plurality of types of particle detection signals having peaks corresponding to particle sizes and detecting the peaks; a plurality of peak value holding means that respond to peak detection signals from the plurality of peak detection means and hold the peak values; A plurality of analog/digital conversion means to be converted, and sequentially selecting and instructing the conversion output operations of the plurality of analog/digital conversion means so that a plurality of conversion outputs are derived in a time-sharing manner. a conversion output selection means, and a plurality of analog/analog signals corresponding to the selection operation of the conversion output selection means;
A particle detection signal processing device comprising a selection means for sorting and outputting converted data from a digital conversion means according to particle type.