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JPH0522387B2 - - Google Patents
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JPH0522387B2 - - Google Patents

Info

Publication number
JPH0522387B2
JPH0522387B2 JP59188402A JP18840284A JPH0522387B2 JP H0522387 B2 JPH0522387 B2 JP H0522387B2 JP 59188402 A JP59188402 A JP 59188402A JP 18840284 A JP18840284 A JP 18840284A JP H0522387 B2 JPH0522387 B2 JP H0522387B2
Authority
JP
Japan
Prior art keywords
insulating film
epitaxial layer
active region
interface
selective
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59188402A
Other languages
Japanese (ja)
Other versions
JPS6165447A (en
Inventor
Shiro Hine
Masao Yamawaki
Naoki Yuya
Masafumi Ueno
Satoshi Yamakawa
Masaaki Kimata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP59188402A priority Critical patent/JPS6165447A/en
Publication of JPS6165447A publication Critical patent/JPS6165447A/en
Publication of JPH0522387B2 publication Critical patent/JPH0522387B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00Isolation regions in semiconductor bodies between components of integrated devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01Manufacture or treatment

Landscapes

  • Element Separation (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は半導体装置の製造方法、特に半導体
基板表面に絶縁膜で分離された活性領域を形成す
る方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming active regions separated by an insulating film on the surface of a semiconductor substrate.

〔従来の技術〕[Conventional technology]

従来用いられているこの種の方法を第3図に示
す。すなわち、第3図は選択的エピタキシヤル成
長技術によつて活性領域を形成する方法を示すも
ので、はじめにシリコン基板1の主表面上にシリ
コン酸化膜等の絶縁膜2を形成した後(第3図
A)、写真蝕刻法によつて所定の領域にのみ当該
絶縁膜2を残し(第3図B)、その後絶縁膜を除
去した部分に絶縁膜とほぼ同等の厚みのエピタキ
シヤル層3を形成し活性領域とする(第3図C)。
A conventionally used method of this type is shown in FIG. That is, FIG. 3 shows a method of forming an active region by selective epitaxial growth technology. First, an insulating film 2 such as a silicon oxide film is formed on the main surface of a silicon substrate 1, and then a third Figure A), the insulating film 2 is left only in a predetermined area by photolithography (Figure 3B), and then an epitaxial layer 3 with approximately the same thickness as the insulating film is formed in the area where the insulating film is removed. This is used as an active region (Fig. 3C).

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかしながら、この選択的に形成されたエピタ
キシヤル層3では、結晶成長時において、図中×
印を付して示したように絶縁膜2との界面近傍に
格子欠陥が導入されやすく、エピタキシヤル層3
に半導体素子を形成した場合に、上記欠陥領域4
に沿つて不純物原子が異常拡散したり、リーク電
流が多くなる等の不都合が生じる欠点があつた。
この欠陥領域4は、絶縁膜2とエピタキシヤル層
3との界面からエピタキシヤル層内部に、0.5μm
程度から甚しい場合には2μm程度の距離にまで
達することがあつた。
However, in this selectively formed epitaxial layer 3, during crystal growth,
As shown with marks, lattice defects are likely to be introduced near the interface with the insulating film 2, and the epitaxial layer 3
When a semiconductor element is formed in the defect area 4,
However, there are drawbacks such as abnormal diffusion of impurity atoms along the path and an increase in leakage current.
This defect region 4 extends 0.5 μm from the interface between the insulating film 2 and the epitaxial layer 3 into the epitaxial layer.
In severe to severe cases, the distance could reach up to about 2 μm.

この発明は、このような問題点を解決するため
になされたもので、その目的は、選択絶縁膜形成
後のエピタキシヤル成長によりながら、活性領域
から欠陥領域を排除することが可能な半導体装置
の製造方法を提供することにある。
The present invention was made to solve these problems, and its purpose is to create a semiconductor device that can eliminate defective regions from the active region by epitaxial growth after forming a selective insulating film. The purpose is to provide a manufacturing method.

〔問題点を解決するための手段〕[Means for solving problems]

このような目的を達成するために、この発明
は、所定の領域に第1の絶縁膜を形成した後に形
成したエピタキシヤル層に選択酸化法を適用し、
第1の絶縁膜との界面近傍の表面に第2の絶縁膜
を形成するようにしたものである。
In order to achieve such an object, the present invention applies a selective oxidation method to an epitaxial layer formed after forming a first insulating film in a predetermined region,
The second insulating film is formed on the surface near the interface with the first insulating film.

〔作用〕[Effect]

エピタキシヤル層形成の際に第1の絶縁膜との
界面近傍に生じた欠陥領域は、第2の絶縁膜で覆
われてしまい、欠陥のない活性領域を得ることが
できる。
Defect regions generated near the interface with the first insulating film during epitaxial layer formation are covered with the second insulating film, making it possible to obtain a defect-free active region.

〔実施例〕〔Example〕

第1図は本発明の一実施例を示す工程断面図で
ある。同図において前述した従来例と全く同様
に、シリコン酸化膜からなる絶縁膜2を形成し、
これを除去した部分のシリコン基板1表面に選択
エピタキシヤル成長法を適用してエピタキシヤル
層3を形成する(第1図A〜C)。その後、本実
施例ではさらに、このエピタキシヤル層3に選択
酸化法を適用し、絶縁膜2との界面近傍表面に選
択酸化膜5を形成する(第1図D)。この結果、
表面が選択酸化膜5によつて覆われない部分のエ
ピタキシヤル層3が、活性領域として形成される
が、前述したように、欠陥領域4の幅は通常0.5μ
m程度以上あるため、選択酸化用のマスクパター
ンの寸法を適当に調整して上記活性領域の端と埋
め込まれた絶縁膜2の端との距離Dを少なくとも
0.5μm以上とすることが望ましい。
FIG. 1 is a process sectional view showing an embodiment of the present invention. In the same figure, an insulating film 2 made of a silicon oxide film is formed in exactly the same manner as in the conventional example described above.
An epitaxial layer 3 is formed on the surface of the silicon substrate 1 from which this has been removed by selective epitaxial growth (FIGS. 1A to 1C). Thereafter, in this embodiment, a selective oxidation method is further applied to this epitaxial layer 3 to form a selective oxide film 5 on the surface near the interface with the insulating film 2 (FIG. 1D). As a result,
The portion of the epitaxial layer 3 whose surface is not covered by the selective oxide film 5 is formed as an active region, but as described above, the width of the defect region 4 is usually 0.5μ.
Since the distance D between the edge of the active region and the edge of the buried insulating film 2 is at least approximately
It is desirable that the thickness be 0.5 μm or more.

これにより、活性領域に欠陥領域がかからない
ようにすることができ、不純物原子の異常拡散が
なくいり、リーク電流も低減できた。
This made it possible to prevent defective regions from covering the active region, eliminate abnormal diffusion of impurity atoms, and reduce leakage current.

次に、他の実施例を第2図に基いて説明する。
はじめに、シリコン基板1表面に形成したシリコ
ン酸化膜からなる絶縁膜2を選択的に除去する工
程までは先の実施例と全く同様である(第2図
A,B)。異なるのは、次の絶縁膜2の膜厚以上
にエピタキシヤル層3Aを形成し、絶縁膜2をエ
ピタキシヤル層3Aで埋め込むところである。こ
の場合、絶縁膜2の側面との界面近傍に欠陥領域
4が形成される他、絶縁膜2の上面との界面近傍
にも欠陥領域4Aが形成される(第2図C)。
Next, another embodiment will be described based on FIG.
First, the steps up to the step of selectively removing the insulating film 2 made of a silicon oxide film formed on the surface of the silicon substrate 1 are exactly the same as in the previous embodiment (FIGS. 2A and 2B). The difference is that an epitaxial layer 3A is formed to have a thickness greater than that of the next insulating film 2, and the insulating film 2 is buried with the epitaxial layer 3A. In this case, a defective region 4 is formed near the interface with the side surface of the insulating film 2, and a defective region 4A is also formed near the interface with the top surface of the insulating film 2 (FIG. 2C).

次いで、選択酸化法によつて埋め込まれた絶縁
膜紀埋2上部のエピタキシヤル層3Aを酸化し、
選択酸化膜5Aを形成する(第2図D)。この場
合も、酸化膜5Aによつて覆われない活性領域と
なる部分のエピタキシヤル層3Aの端と埋め込ま
れた絶縁膜2の端との距離Dは0.5μm以上とする
ことが望ましく、これによつて不純物原子の異常
拡散がなくなり、リーク電流も少なくなつた。
Next, the epitaxial layer 3A on top of the buried insulating film 2 is oxidized by a selective oxidation method,
A selective oxide film 5A is formed (FIG. 2D). In this case as well, it is desirable that the distance D between the end of the epitaxial layer 3A in the active region not covered by the oxide film 5A and the end of the buried insulating film 2 is 0.5 μm or more; As a result, abnormal diffusion of impurity atoms is eliminated, and leakage current is also reduced.

このような本発明による方法は、シリコン基板
を用いた各種の半導体装置を形成する際に、前提
となる活性領域の形成技術として共通に使用する
ことができる。なお、基板およびエピタキシヤル
層の導電形については特に触れなかつたが、これ
は、本発明がこれらの導電形には一切無関係に適
用できるためで、両者の導電形はP形でもN形で
も、相互に同一でも異なつていてもよい。また、
第1の絶縁膜2はシリコン酸化膜に限らずシリコ
ン窒化膜等他の絶縁膜でもよいことは言うまでも
ない。
Such a method according to the present invention can be commonly used as a prerequisite active region formation technique when forming various semiconductor devices using a silicon substrate. Note that the conductivity types of the substrate and the epitaxial layer have not been specifically mentioned, but this is because the present invention can be applied regardless of these conductivity types, and the conductivity types of both may be P type or N type. They may be the same or different. Also,
It goes without saying that the first insulating film 2 is not limited to a silicon oxide film, but may be another insulating film such as a silicon nitride film.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、この発明によれば、所定
の領域に第1の絶縁膜を形成した後に形成したエ
ピタキシヤル層に選択酸化法を適用して第1の絶
縁膜との界面近傍表面に第2の絶縁膜を形成する
ことにより、第2の絶縁膜によつて覆われない部
分のエピタキシヤル層を、欠陥のない活性領域と
して得ることができる。
As explained above, according to the present invention, selective oxidation is applied to the epitaxial layer formed after forming the first insulating film in a predetermined region, so that the first insulating film is formed on the surface near the interface with the first insulating film. By forming the second insulating film, the portion of the epitaxial layer not covered by the second insulating film can be obtained as a defect-free active region.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示す工程断面図、
第2図は本発明の他の実施例を示す工程断面図、
第3図は従来の半導体装置の製造方法を示す工程
断面図である。 1……シリコン基板、2……絶縁膜(第1の絶
縁膜)、3,3A……エピタキシヤル層、4,4
A……欠陥領域、5,5A……選択酸化膜(第2
の絶縁膜)。
FIG. 1 is a process sectional view showing an embodiment of the present invention;
FIG. 2 is a process sectional view showing another embodiment of the present invention;
FIG. 3 is a process cross-sectional view showing a conventional method of manufacturing a semiconductor device. DESCRIPTION OF SYMBOLS 1... Silicon substrate, 2... Insulating film (first insulating film), 3, 3A... Epitaxial layer, 4, 4
A...Defect area, 5,5A...Selective oxide film (second
insulation film).

Claims (1)

【特許請求の範囲】[Claims] 1 半導体基板上の所定の領域に分離用絶縁膜を
形成する工程と、この半導体基板上にエピタキシ
ヤル成長法を用いて半導体層を形成する工程と、
形成したエピタキシヤル半導体層に選択酸化法を
適用することにより分離用絶縁膜との界面近傍表
面に選択酸化膜を形成しこの選択酸化膜で覆われ
ない部分のエピタキシヤル半導体層を活性領域と
する工程とを含み、上記活性領域が上記分離用絶
縁膜と上記エピタキシヤル半導体層との界面から
0.5μm以上離れるように上記選択酸化膜を形成す
ることを特徴とする半導体装置の製造方法。
1. A step of forming an isolation insulating film in a predetermined region on a semiconductor substrate, and a step of forming a semiconductor layer on this semiconductor substrate using an epitaxial growth method,
By applying a selective oxidation method to the formed epitaxial semiconductor layer, a selective oxide film is formed on the surface near the interface with the isolation insulating film, and the portion of the epitaxial semiconductor layer not covered by this selective oxide film is used as an active region. a step in which the active region is separated from the interface between the isolation insulating film and the epitaxial semiconductor layer.
A method for manufacturing a semiconductor device, characterized in that the selective oxide films are formed at a distance of 0.5 μm or more.
JP59188402A 1984-09-07 1984-09-07 Manufacture of semiconductor device Granted JPS6165447A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59188402A JPS6165447A (en) 1984-09-07 1984-09-07 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59188402A JPS6165447A (en) 1984-09-07 1984-09-07 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS6165447A JPS6165447A (en) 1986-04-04
JPH0522387B2 true JPH0522387B2 (en) 1993-03-29

Family

ID=16223013

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59188402A Granted JPS6165447A (en) 1984-09-07 1984-09-07 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6165447A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02137244A (en) * 1988-11-17 1990-05-25 Nec Corp Manufacture of semiconductor device

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5179590A (en) * 1975-01-06 1976-07-10 Hitachi Ltd HANDOTAISOCHINOSEIZOHOHO
JPS56158446A (en) * 1980-05-12 1981-12-07 Matsushita Electric Ind Co Ltd Manufacture of semiconductor integrated circuit

Also Published As

Publication number Publication date
JPS6165447A (en) 1986-04-04

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