JPH0522389B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor integrated circuit device (hereinafter abbreviated as IC), and particularly to an IC including a bipolar type element.
The target is

In bipolar ICs, it is essential to create electrical isolation between elements, and one specific method for achieving this is to cover the semiconductor region with an oxide film called a field oxide film to achieve high integration. The isoplanar method, in which the material is surrounded by a (SiO ₂ film), is currently widely used.

In this isoplanar IC, it is necessary to provide a channel stopper to prevent current from being conducted to other semiconductor regions by the semiconductor layer under the field oxide film. In forming this channel stopper, the channel stopper and the field oxide film are formed using the same mask according to a method known, for example, in Japanese Patent Publication No. 51-438. When forming this channel stopper, it is necessary to align the substrate and the buried layer of a different conductivity type, which have been previously formed on the surface of the substrate. for example,
An N-type epitaxial layer is formed on ^a P-type Si substrate 1 via an N ⁺ buried layer 2 as shown in FIG. When configuring an NPN transistor separated from the collector (contact part) 5, an N ⁺ buried layer 2 is used to form a channel stopper 6.
This has the disadvantage that mask alignment is required, which impedes improvement in the degree of integration. Furthermore, if there is a mask misalignment under the field oxide film 3, an imbalance in isolation voltage will occur between the base side and the collector side of the transistor.It is necessary to ensure the voltage resistance value between adjacent buried layers in the channel stopper region. 6
It has drawbacks such as difficulty in improving the degree of integration because it cannot be made smaller.

Note that another conventional technique for forming a channel stopper under a field oxide film is disclosed in Japanese Patent Application Laid-open No. 54-162978.
It is shown in the publication No. In this example, after sequentially forming a polycrystalline silicon film and a silicon nitride film (Si ₃ N ₄ ) on a P-type semiconductor substrate, the Si ₃ N ₄ film is selectively removed, and using this as a mask, the N, which will become the buried layer, is removed. After implanting type impurities, the polycrystalline silicon film is selectively oxidized using the same mask to form an oxide film, and after removing the nitride film that served as the mask, P-type Impurities are implanted into the substrate surface to form channel stoppers. However, according to this method, (1) polycrystalline silicon is used as a mask when forming the N+ type buried layer and the oxide film, so the lateral diffusion of N type impurities is _large ; It is difficult to define the position of the N-type buried layer using the _4- layer film, and the withstand voltage between the collectors of adjacent elements is poor. (2) Heat treatment and oxidation of polycrystalline silicon may cause stacking faults and cluster dislocation on the surface of the silicon substrate, and the crystal size of polycrystalline silicon may grow and become larger, resulting in noticeable unevenness on the surface of the silicon substrate. I can't avoid the flaws.

[Problems to be Solved by the Invention] The purpose of the present invention is to solve bipolar ICs.
The purpose is to improve the degree of integration and withstand voltage.

[Means to solve the problem] The configuration of the present invention consists of the following steps.

(1) A step of preparing a semiconductor substrate having one main surface; (2) A step of introducing impurities of a first conductivity type into one main surface of the semiconductor substrate to selectively form a first semiconductor region; (3) introducing an impurity of a second conductivity type into one principal surface of the semiconductor substrate to form a second semiconductor region having an impurity concentration lower than that of the first semiconductor region so as to surround the first semiconductor region; (4) forming a semiconductor layer of a first conductivity type on one main surface of the semiconductor substrate on which the first semiconductor region and the second semiconductor region are formed; (5) the semiconductor layer located on the first semiconductor region; (6) selectively forming an oxidation-resistant film on the main surface of the layer; (6) forming the oxidation-resistant film without substantially etching the surface of the semiconductor where the oxidation-resistant film is not formed; (7) removing the oxidation-resistant film and removing the thermal oxide film by thermally oxidizing the surface of the semiconductor layer using the mask as a mask to selectively form a thermal oxide film having a depth that does not reach the first semiconductor region; and a second conductivity type semiconductor region formed in the semiconductor layer by upward diffusion of the second semiconductor region, forming a bipolar transistor in the semiconductor layer.

Hereinafter, the present invention will be explained in detail with reference to embodiments shown in the drawings.

[Example] Figures 3A to 3I are bipolar according to the present invention.
FIG. 2 is a cross-sectional view of each step showing the IC manufacturing process, and corresponds to the following steps (A) to (I).

(A) A high-resistance P ^- type Si substrate 11 is prepared, and a thin SiO ₂ film 12 of 900 Å is formed on its surface by thermal oxidation. After forming an oxidation-resistant Si ₃ N ₄ film 13 with a thickness of 1500 Å on top of it by CVD (chemical vapor deposition), etc., plasma etching is performed using a photoresist as a mask to form an N ⁺ buried layer. The portions of the SiO ₂ film 12 and Si ₃ N ₄ film 13 to be formed are selectively removed.

(B) The surface impurity concentration is reduced by diffusing antimony (or arsenic) using the Si ₃ N ₄ film 13 as a mask.
They are selectively introduced into the substrate at a concentration of 10 ¹⁹ to 20 ²⁰ atoms/cm ³ , and the surface of the substrate 11 is thermally oxidized. This makes the N ⁺ type buried layer 14 approximately
A thick layer of 4000 Å is formed on the substrate surface on the N ⁺ type buried layer 14.
A SiO ₂ film 15 is formed. That is, the N ⁺ type buried layer 14 and the SiO ₂ film 15 are defined by the same mask.

(C) After removing the Si ₃ N ₄ film 13, the SiO ₂ film 15 and
A P-type channel stopper 16 is formed by utilizing the difference in film thickness of the SiO ₂ film 12. That is, boron (or boron fluoride) ions are implanted into the entire surface of the substrate. At this time, SiO ₂ film 15 and SiO ₂ film 1
Since there is a film thickness difference of 3100 Å between the SiO 2 film 12 and the SiO ₂ film 12, the boroions do not reach the substrate in the region where the SiO 2 film 12 is present, but on the other hand, in the region where the SiO ₂ film 12 is present, they pass through this film and are implanted into the substrate. be included. After this, heat treatment is performed to reduce the surface impurity concentration to 10 ¹⁷ atoms/cm ³
The P-type channel stopper 16 is formed so that.

In this way, the P-type channel stopper 16
It is formed using the SiO ₂ film 15 as a mask. As mentioned earlier, the SiO ₂ film 15 and the N ⁺ type buried layer 14
are defined by the same mask, the position of the P-type channel stopper 16 is equivalent to being defined by the N ⁺ type buried layer 14, and therefore, their mutual positions are defined by the same mask. are defined in a self-consistent manner without alignment.

(D) SiO ₂ film 12 and
All of the SiO ₂ film 15 is removed by etching. At this time, a step is generated on the surface of the substrate as shown in the figure. This is because the amount of silicon on the substrate used to form the oxide film differs.

(E) Form an N ^- type doped eptaxial silicon layer on the entire surface of the substrate to a thickness of 1.5 μm to 2.0 μm. At this time, the above-mentioned step difference appears as it is on the surface of the epitaxial layer 17.

(F) A thin SiO ₂ film 18 of 900 Å is formed on the surface of the epitaxial silicon layer 17 by surface oxidation by heat treatment in an oxidizing atmosphere. moreover
After forming the Si ₃ N ₄ film 19 to a thickness of 1500 Å using the CVD method, the Si ₃ N ₄ film is removed by photoetching in the areas where an isolation layer made of SiO ₂ for insulating and isolating each semiconductor region is to be formed. Remove by etching.

(G) By performing heat treatment in an oxidizing (wet) atmosphere, the epitaxial layer 17 in the area where the Si ₃ N ₄ film 19 is not formed is selectively oxidized to form the field SiO ₂ film 20 to a thickness of 10,000 Å. to form. This is for insulating and separating each semiconductor region from each other. At this time, the channel stopper 16 is extended and the field
The SiO ₂ film 20 is reached and isolation is completed.

(H) After removing the Si ₃ N ₄ film 19, a new
A Si ₃ N ₄ film 24 is formed to a thickness of 1400 Å using the CVD method. Then, the Si ₃ N ₄ film in the portion where the collector connection region 21 is to be formed is selectively removed by etching, phosphorus is ion-implanted using the exposed field SiO ₂ film as a mask, and then heat treatment is performed to form the N ⁺ type. A collector connection region 21 is formed.

(I) After removing the entire Si ₃ N ₄ film 24, a photoresist mask (not shown) is formed to cover the collector connection region 21, boron ions are implanted into the entire surface to form a base, and then heat treatment is performed. The P ⁺ type base region 22 is formed to a depth of about 0.6 μm.
form. Next, after removing the photoresist mask, a PSG (phosphorus silicate glass) film 25 is formed to a thickness of about 3500 Å by CVD, and the base surface is etched by photoetching.
By removing a part of the PSG film, implanting arsenic ions, and subsequently performing heat treatment, the depth can be increased.
A 0.35 μm N ⁺ emitter region 23 is formed.

(J) Finally, contact holes are opened in each region, aluminum is deposited by vacuum evaporation method, and this is then patterned as desired.
By forming aluminum electrodes E, B, and C in ohmic contact with each region, as shown in FIG.
The NPN bipolar transistor is completed.

[Effects of the Invention] According to the present invention as described above, the following effects can be obtained.

(1) An IC including highly integrated bipolar elements can be obtained.

The reason for this is that within the semiconductor substrate (high resistance P ^- type Si substrate 11), there is a region opposite to the first conductivity type in contact with the semiconductor region of the first conductivity type (in the example, the N ⁺ type buried layer 14). This is because the second conductivity type semiconductor region (P ⁺ type buried layer 16 in the embodiment) is selectively provided. This is because the method described above eliminates the need for separate masks for forming a semiconductor region of the first conductivity type and a mask for forming a semiconductor region of the second conductivity type, so there is no need to consider mask alignment. . That is, there is no need for a margin for mask alignment, and both buried layers overlap each other in a self-aligned manner, so that as a result, the degree of integration can be greatly improved. This point will be described in more detail below.

According to the method described above, the position of the P ⁺ type buried layer serving as a channel stopper is defined by the thick oxide film 15. On the other hand, this thick oxide film 1
5 and the N ⁺ type buried layer 14 have a common mask (SiO ₂
film and Si ₃ N ₄ film). N ⁺ because polycrystalline Si is not used in the mask
There is no horizontal spread of N ⁺ type impurities due to N ⁺ type buried diffusion. P+ type diffusion (channel stopper formation) into the substrate 11 is performed using a thick oxide film 14.
This can be performed with good control by utilizing the difference in thickness between the thin oxide film 12 and the thin oxide film 12. Therefore, the positions of the P ⁺ type buried layer are defined by the N ⁺ type buried layer, and the mutual positions match without alignment. In this way, the pre-formed N
There is no need for alignment when forming the P ⁺ type buried layer with respect to the + type buried layer, and therefore there is no need to provide a margin for mask alignment.

As a result of eliminating the need for mask alignment margins, the elements can be formed smaller, as is clear from the patterns shown in FIG. 2 and FIG.
The degree of integration will improve. In the case of the present invention, FIG.
FIG. 6 shows the pattern of one transistor in a plan view in the case of the prior art. First, in Fig. 6, the distance lA is the mask alignment margin (=maximum error in alignment ≒ 1 μm), and the distance lB is between the P type base region B and the P ⁺ type buried layer (P type channel stripper). The distance LC is the distance between the collectors of adjacent transistors to obtain the necessary withstand voltage. On the other hand, according to the present invention, as shown in FIG. 2, the base B and collector C have the same dimensions as the conventional ones, but since both buried layers overlap each other in a self-aligned manner, there is a mask alignment margin.
Only lA can be omitted.

(2) Processes can be simplified.

As mentioned above, since the need for alignment is eliminated, the mask forming step for forming the second conductivity type semiconductor region (P+ type buried layer 16 in the example) can be omitted, simplifying the process. can.

(3) While achieving high integration, it is possible to improve voltage resistance.

Due to the reason (1) above, there is no variation in the distance between the second conductivity type semiconductor region (P ⁺ type buried layer 16) and the bipolar element formation region (P type base region), which improves the breakdown voltage and improves reliability. You can improve your sexuality. That is, after forming the second conductivity type semiconductor layer (epitaxial layer 17), the second conductivity type semiconductor region (P ⁺ type channel stopper P ⁺
The distance between the second conductivity type semiconductor region (P ⁺ type buried layer 16), that is, the channel stopper, and the bipolar element forming region (P type base region) is smaller than when forming the type buried layer 16). It can be used to increase pressure resistance. The reasons for this will be explained in more detail below.

As is clear from the above-mentioned process D, after the removal of the SiO ₂ films 15 and 16 (FIG. 3D), the surface of the N ⁺ type buried layer 14 and the surface of the P ⁺ type buried layer (P ⁺ type channel stopper) 16 are removed. A difference is generated between the two, and this difference also appears on the surface of the epitaxial layer 17. The presence of this difference causes the impurity concentration of the N ⁺ type buried layer 14 to be higher than that of the end layer 16, as shown in FIG. 3G.
In other words, the P+ type buried layer 16 has a lower impurity concentration than the N ⁺ type buried layer 14. Further, as evidenced by the fact that the channel stopper 16 is stretched in the aforementioned step G, the impurity concentration of the N ^- type semiconductor layer is even lower than that of the P ⁺ type buried layer. Therefore, an increase in the PN junction capacitance between the two can be avoided.

(5) No crystal defects occur in the semiconductor layer.

The introduction of impurities for the formation of a P ⁺ type buried layer is carried out through a thin SiO ₂ film, and then the SiO ₂
Since the film is removed and epitaxial growth is performed directly on the P ⁺ type buried layer, crystal defects in the semiconductor layer do not occur. Furthermore, unevenness on the surface of the semiconductor layer due to crystal size growth is also reduced.

(6) According to the embodiment of the present invention described above, in addition to the above, there is a significant effect in improving the degree of integration.

That is, instead of the isoplanar method
Formed by LOCOS (Si selective low temperature oxidation) method
Parts 20a and 20b of the field SiO ₂ film 20 on the portion where the SiO ₂ film performs insulation isolation of the elements are formed to be depressed. This depressed field formed
The SiO ₂ film portion 20a expands the isolation margin with the base region 22 shown in FIG. 3I. i.e. field _SiO2
The film portions 20a and 20b suppress the lateral expansion and diffusion of the P ⁺ type buried layer 16. Furthermore, as is clear from the manufacturing process of the present invention described above, since the N ⁺ type buried layer 14 has a higher impurity concentration than the P ⁺ type buried layer 16, the lateral direction of the P ⁺ type buried layer 16 It suppresses the spread and spread.

As a result, it is possible to improve the degree of integration and the breakdown voltage.

(4) Substrate junction capacitance can be reduced.

That is, according to (1) above, the PN junction area between the semiconductor substrate and the collector region can be reduced, so the PN junction capacitance (substrate junction capacitance) can be reduced.

In addition, as mentioned above, the N+ type buried layer 14 is P ⁺ type buried, so there is no underetching of the silicon under the Si ₃ N ₄ film mask, and therefore there is no need to leave room for the mask, and the integration density can be increased. You can improve. As shown in Figures 3F to 3G, when forming the isolation SiO ₂ film, the Si ₃ N ₄ mask is formed in the recessed part of the epitaxial layer, so the bird heads (projections of the SiO ₂ film) are removed by selective oxidation. The formation is relaxed, and there is no disconnection in the wiring formed thereon. As described above, according to this embodiment, in addition to the above-mentioned effect of improving the degree of integration by omitting the mask alignment margin, a synergistic effect is produced, which is extremely effective in improving the degree of integration of bipolar ICs.

[Modification] Next, as a second embodiment of the present invention, an example will be described in which PN junction isolation is used as a method of insulation separation between elements.

In this case, the process up to the formation of the epitaxial semiconductor layer 17 on the semiconductor substrate 11 (FIGS. 3A to 3E) described in the previous embodiment is the same process, and then the surface of the semiconductor layer 17 is formed. A window is etched by photoresist treatment on a portion of the SiO ₂ film, and boron or the like is selectively diffused or ion implanted to obtain a P ⁺ type insulating isolation region 26 that reaches from the semiconductor layer surface to the P ⁺ type buried layer 16. .

Figure 4 shows the P obtained by such a process.
A P + type base region 22 and an N ⁺ type base region 22 are formed on the surface of the N type epitaxial layer 17 surrounded by the + type insulation isolation region 26 ^.
On the other hand, a structure in which an epitaxial region 23 and an N ⁺ type collector extraction portion 21 are formed is shown. According to this embodiment, the following effects can be obtained in addition to the effects obtained by the previously described embodiments. In particular, in ICs that require high speed, the epitaxial layer 17 is thin.
For example, since it is formed to have a thickness of 1.5 to 2.0 μm, a highly integrated IC can be obtained with almost no change in the area of the insulating isolation region even by combining isolation methods using PN junctions. Also, unlike the separation method using an oxide film (isoplanar method), the surface is flat,
This is effective in preventing disconnection in wiring layers.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of essential parts of a bipolar IC according to the present invention. FIG. 2 is a plan view of essential parts of the bipolar IC of the present invention. Figures 3A to 3I are according to the present invention.
Cross-sectional views of each step to show the IC manufacturing process.
FIG. 4 is a sectional view showing another form of the bipolar IC according to the present invention. FIG. 5 is a sectional view of essential parts showing an example of a bipolar IC manufactured by the conventional technique. FIG. 6 is a plan view of essential parts showing an example of a bipolar IC manufactured by the conventional technique. 11...P- type silicon substrate, 12...Thin oxide film, 13...Silicon nitride film, 14...N ⁺ type buried layer, 15...Thick oxide film, 16...P ⁺ type channel stopper, 17...N ^- type epitaxial layer, 20... Field oxide film for insulation isolation,
21...N ⁺ type collector connection region, 22...P type base region, 23...N type emitter region, 25...
...PSG membrane, 26...P ⁺ type separation region.

Claims (1)

[Claims] 1. (1) A step of preparing a semiconductor substrate having one principal surface; (2) Introducing impurities of a first conductivity type into one principal surface of the semiconductor substrate to selectively form a first semiconductor region. (3) introducing a second conductivity type impurity into one main surface of the semiconductor substrate, and forming a second conductivity type impurity having a lower impurity concentration than the first semiconductor region so as to surround the first semiconductor region; a step of forming a semiconductor region; (4) a step of forming a semiconductor layer of a first conductivity type on one principal surface of the semiconductor substrate on which the first semiconductor region and the second semiconductor region are formed; (5) a step of forming the first semiconductor layer. selectively forming an oxidation-resistant film on the main surface of the semiconductor layer located on the region; (6) substantially etching the surface of the semiconductor layer where the oxidation-resistant film is not formed; (7) selectively forming a thermally oxidized film having a depth that does not reach the first semiconductor region by thermally oxidizing the surface of the semiconductor layer using the oxidation-resistant film as a mask; removing the film and forming a bipolar transistor in the semiconductor layer surrounded by the thermal oxide film and a second conductivity type semiconductor region formed in the semiconductor layer by upward diffusion of the second semiconductor region; A method for manufacturing a semiconductor integrated circuit device, comprising the steps of: 2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein in the step (4), the semiconductor layer is formed after providing a stepped portion on the surface of the first semiconductor region. 3. In step (2), a pattern of an oxidation-resistant film is formed on the surface of the semiconductor substrate, and a first conductivity type is exhibited on the surface of the semiconductor substrate corresponding to a portion where the pattern of the oxidation-resistant film is not formed. Introducing impurities
selectively forming a thermal oxide film on the surface of the semiconductor substrate using the oxidation-resistant film as a mask, and forming a first semiconductor region of the first conductivity type located under the selective oxide film; (3) shows a second conductivity type different from the first conductivity type on the surface of the semiconductor substrate on which the selective oxide film is not formed using the selective oxide film as a mask; A patent claim characterized by comprising the step of ion-implanting an impurity with a large amount of elongated diffusion to surround the first semiconductor region to form the second semiconductor region having a lower impurity concentration than the first semiconductor region. A method for manufacturing a semiconductor integrated circuit device according to item 1.