JPH052243B2 - - Google Patents

Description

[Detailed Description of the Invention] (a) Field of Industrial Application This invention relates to a measuring device, specifically a measuring device capable of measuring objects to be measured whose location and number are uncertain, and a measuring device capable of counting objects to be measured. related to a measuring device.

(b) Conventional technology Conventionally, in order to measure the number of holes in an object to be measured, for example, a board with multiple holes, the board is passed straight horizontally between a light source and a measuring means that are lined up above and below, and the light source illuminates the board. A measuring means receives the light with a CCD camera or the like, and transmits the presence or absence of the light as a digital signal to a measurement processing means such as a microcomputer or a counting processing means. In this device, light from areas with holes reaches the light receiving section, while light from areas without holes is blocked and does not reach the light receiving section. The presence or absence of this light reception is used as information for each point on the object to be measured, and the object is scanned perpendicularly to the direction of movement of the object by slicing it by the width of the light-receiving element (hereinafter also referred to as dot width). The information was transmitted from the department to a processing means such as a microcomputer. Furthermore, in order to count the objects to be measured, the signal from the light receiving section is stored in a storage device provided in the microcomputer, and then the image on the storage device is sequentially scanned by raster scanning to find one pixel and label it. Next, the same label is attached to pixels within 8 neighborhoods of this labeled pixel, and when there are no more pixels to be newly labeled, the same label is assigned to one connected pixel.
When there are no more pixels to label,
Scanning is performed again, and when a pixel that does not yet have a label is found, a new label that has not been used before is attached, and the same label is attached to the pixels within the 8-neighborhood again. By repeating this process, when the images of all the dots on the object to be measured have been scanned, the number of labels used for labeling becomes the number of holes on the object to be measured. .

However, in the above-mentioned method, the presence or absence of light reception for all dots assumed on the object to be measured must be stored in a microcomputer, requiring complicated computer software for labeling, and scanning, This method had problems such as requiring a large amount of counting time due to repeated labeling.

In order to solve the above-mentioned problem, the present inventor proposed in Japanese Patent Application No. 117849/1984 a counter capable of counting objects whose location and number are uncertain. According to this counting machine, in order to measure the number of holes in an object to be measured, for example, a board with multiple holes, the board is passed horizontally in a straight line between vertically arranged light sources and a light receiving means which is a measuring means. The light from the portions with holes reaches the light receiving means, and the light from the portions without holes is blocked and does not reach the light receiving means. The presence or absence of this light reception is used as information for each point on the object to be measured, and the object is scanned in a direction intersecting the direction of movement of the object. is digitized as 〓1〓, and when no light is received, it is digitized as [0] and transmitted. The signal from the wave light means is input to the storage means and the counting means, and the storage means stores the signals sequentially for each width of the substrate that is the object to be measured, as if the scanned signal were recorded as a collection of dots on the object to be measured. Memorize the collection of dots in the width direction of the object to be measured.
If it is a line, it is possible to store one line of input signals, output the stored one line of signals, erase the memory, and at the same time store the signal currently being transmitted by the light receiving means. Therefore, a counting means consisting of an AND gate, a flip-flop circuit, a counting counter, and a display device synchronizes and inputs the currently scanning signal from the light receiving means and the signal from one line before stored in the storage means, and performs counting. He invented and proposed a counting machine with a display.

(C) Problems to be Solved by the Invention However, for example, when measuring a hole in a substrate that is an object to be measured, the light receiving means that is the measuring means of the above-mentioned measuring device is wider than the object to be measured. Because of the small size, the passing light from the light source reaches the measuring means at an acute angle as it approaches the end of the substrate in the scanning direction from the center of the substrate, which is the object to be measured. The apparent diameter of the overlapping portion of the circumferential edge of the hole on the measuring means side and the circumferential edge of the light source side is smaller than the diameter of the hole. Therefore, the light that passes through the hole and reaches the corresponding light-receiving element of the light-receiving means cannot be received by the light-receiving element in an amount equivalent to the diameter of the hole, and the measuring means measures the hole to be smaller than it appears. There were some problems.

As mentioned above, when measuring an object, it is difficult to accurately measure the object depending on the thickness of the object and the relative positional relationship between the light source, the object, and the light receiving means. In order to avoid this problem, several CCD cameras should be installed in succession so that the light-receiving element of the CCD camera used as the measurement means is equal to or longer than the width of the object to be measured in the scanning direction. I made it. However, in this measurement method, the light passing through the object to be measured must be installed so that it can be received by the light receiving element located in the direction that corresponds to the axis of the hole in the object to be measured. Although one hole is sufficient to measure a hole, it is not longer than the width of the object to be measured in the scanning direction, so several holes must be connected in a manner that is longer than the width of the object to be measured in the scanning direction. This method has problems such as the need for complicated means to operate several CCD cameras as one CCD camera, and therefore has economical problems such as the manufacturing cost of manufacturing the counting machine.

(d) Means for Solving the Problems This invention scans the object one-dimensionally in the direction of movement and crossing the object as it passes, and scans the object at the scanning point of the object. A measurement means that detects "" or "absence", digitizes it, and transmits the signal, and inputs the signal output from the measurement means and instructs the measurement target position of the object in a one-dimensional scanning direction of the input signal. Input the address signal, and if the signal from the measurement means is a digitized signal that detects the measurement target as "present", outputs the digitized signal that detects the measurement target as "presence" to the specified output. Then, depending on the measurement object position of the scanning signal that intersects the direction of movement of the object to be measured, the digitized signal indicating that the object to be measured is detected as "present" is increased and corrected to a predetermined number of other outputs and output. a signal generating means having a plurality of outputs, a plurality of logic operation means inputting the plurality of output signals outputted by the signal generating means so as to correspond to each other, and one signal output maintaining means outputting a measurement target output from the signal generating means. 1 logic operation means inputs the same signal as one of the signals detected as "presence" or "absence" and maintains the output to the logic operation means 1, and inputs the signal output from the signal output maintenance means 1; simultaneously inputs other output signals from the signal generating means,
If at least one of the signals detects that the measurement target is "present," outputs the signal that detects the measurement target as "presence" to the next signal output maintaining means,
In other cases, the signal that detects that the measurement target is "absent" is outputted to the next signal output maintaining means, and the signal output maintaining means that has input the signal output from the first logical operation means is sent to the next logical operation means. Connected so as to maintain the output of the input signal, and connect a plurality of other logic operation means and signal output maintaining means in the same way in sequence, and the final signal output maintaining means comprises correction signal output means for outputting a measurement signal. A measuring device characterized by: and a measuring device that scans one-dimensionally in a direction intersecting the traveling direction of the measured object when the measured object passes, and detects whether the measured object is present or absent at a scanning point of the measured object. A measuring means that detects, digitizes and transmits a signal, inputs the signal output from the measuring means, and inputs an address signal that indicates the applicable position of the object to be measured in a one-dimensional scanning direction of the input signal, If the signal from the measurement means is a digitized signal that indicates that the object to be measured is "present," the digitized signal that indicates that the object to be measured is "present" is output to a predetermined output, and Measurement of the object to be measured in the scanning direction intersecting the direction of travel Depending on the applicable position, the digitized signal that detects the presence of the object to be measured is increased and corrected to a predetermined number of other outputs and has multiple outputs. A signal generating means and a plurality of output signals outputted from the signal generating means are inputted so as to correspond to each of the plurality of logic operation means,
The signal output maintaining means inputs the same signal as one of the signals output by the signal generating means that detects the measurement target as "presence" or "absence", maintains the output to the logic operation means of 1, and outputs the signal of 1. One logic operation means which inputs the signal output from the maintenance means simultaneously inputs another output signal from the signal generation means, and if at least one of the signals is a signal that detects that the measurement target is "present", A signal that detects that the measurement target is "present" is output as a signal to the next signal output maintaining means, and in other cases, a signal that detects that the measurement target is "absent" is output as a signal to the next signal output maintaining means; The signal output maintaining means inputting the signal output from the logical operating means is connected to the next logical operating means so as to output and maintain the input signal, and the other plurality of logic operating means and signal output maintaining means are sequentially connected in the same manner. the final signal output maintaining means outputs the measurement signal to the storage means and the counting means; and the storage means stores the signal of the width portion of the object to be measured outputted by the correction signal output means for each scan. , a counting means for comparing and counting the signal of the width portion of the object to be measured for each scan outputted by the correction signal output means and the correction signal for the width portion of the object to be measured before the scanning stored in the storage means; The above-mentioned problems are solved by providing a measuring device characterized by the following.

(e) Effect The signal generating means inputs a signal from which the measurement means measured the object to be measured and an address signal indicating the measurement object position of the input signal, and depending on the measurement object measurement position of the signal, A correction signal is output from multiple output terminals. Next, the output signal of the signal generating means is input to at least one of the logical operation means and the signal output maintaining means. Each logic operation means inputs the output signal of the signal generation means, performs an input operation on the signal maintained as an output by the corresponding signal output maintenance means, and outputs the result to the corresponding signal output maintenance means. The signal output maintaining means, which inputs the output signal of the signal generating means, receives the signal and stops outputting the signal that has been maintained until now, and continues to output the newly input signal until the next signal is input. . The other signal output maintaining means inputs the signal from the logic operation means, stops outputting the signal that has been maintained until now, maintains the output of the newly input signal until the next signal input, and outputs at least one signal. The output maintaining means outputs a measurement signal. Further, the output signal of the signal output maintaining means that outputs the measurement signal is outputted to the storage means and the counting means, and the storage means outputs the stored signal to the counting means and the signal output maintaining means outputs the measurement signal. The counting means compares and calculates the signal for the width of the object to be measured for each scan with the stored signal for the width of the object for each scan. Output the calculation result.

(f) Examples The present invention will be described below based on drawings showing examples of the invention.

Fig. 1, Fig. 2 showing the parts diagram, Fig. 3 showing the arrow view of Fig. 1, Fig. 4 showing the measurement situation of the measurement object,
Figure 5, Figure 6 explaining the situation of pixel missing, Figure 7 explaining the correction circuit, Figures 8a and 8b representing the measurement signal sequence, and Figure 8 comparing the measurement signal sequence and the correction signal sequence. Figure 9a, Figure 9b, Figure 10 showing the counting section,
The counting method will be explained with reference to FIG. 11.

1 is a light source that emits light, which is a measurement medium.
Light source 1 is a linear light source.

Reference numeral 2 denotes a light receiving section which is a measuring means, and the light receiving section 2 further emits light from the light source 1 vertically above the light source 1 so as to maintain a distance between the light source 1 and the light receiving section 2 that allows the object to be measured to pass through. It is installed in a state where there is nothing blocking the light from reaching the light receiving part 2. In this embodiment, light source 1
The light receiving unit 2 is installed vertically above the light source 1, and the linear direction of the light source 1 is installed perpendicular to the direction in which the object to be measured is transported.
Measurement is possible if the mutual positional relationship is such that the light irradiated by the two passes through the object to be measured and reaches the light receiving section 2, which is the measuring means.

3 is a transport device, and 4 is an object to be measured. The transport device 3 is installed so that the object to be measured 4 can be transported in a direction intersecting the light source 1 and the light receiving section 2 . Measured object 4
is an electronic circuit board in this embodiment, and has a plurality of through holes 6 on its surface to be measured.

5 is a light receiving element. As shown in FIG. 2, which is a view of the light receiving section 2 in the direction of the light source 1, the light receiving element 5 is provided at the end of the light receiving section 2 on the light source 1 side so as to be able to receive light equal to or more than the width of the object to be measured 4. The total width of the light receiving element 5 is
As shown in the figure, the width is narrower than the width of the light receiving element 5 of the object to be measured 4 in the array direction, and the irradiation light from the light source 1 for the four widths of the object to be measured is concentrated within the entire width of the light receiving element 5 of the light receiving section 2. The light reaches the light receiving element 5. Therefore, the object to be measured 4
is placed on the transport device 3 and moved by the transport device 3 so as to intersect with the linear direction of the light source 1. In this embodiment, the direction in which the transport device 3 transports the object to be measured 4 is perpendicular to the linear direction of the light source 1.
The object to be measured 4 is transported between the light source 1 and the light receiving section 2,
In the part of the object to be measured 4 where the hole 6 is not open, the light source 1
The hole 6 blocks the light from the light source 1 and prevents it from reaching the light receiving section 2.
reach. At this time, the light receiving unit 2 can receive light corresponding to the width of the measured object 4 on the measured object 4 in a direction perpendicular to the traveling direction of the measured object 4, and the measured object 4 is sequentially moved by the conveying device 3. Since it moves, the light receiving section 2 scans the entire surface of the object 4 to be measured. Light receiving part 2
Now, let the object to be measured 4 be a collection of dots, and only the presence or absence of light for each dot is digitized by each light receiving element 5 as 1 when receiving light and 0 when not receiving light. Send. Hereinafter, the signals transmitted by each light-receiving element 5 will be referred to as a pixel.

At this time, as shown in FIG. 4, in the hole 6a located near the center of the object to be measured 4 in the conveyance direction, the axial direction connecting the hole 6a and the light receiving element 5 for measuring the hole 6a,
Since the axial direction of a is substantially the same direction, the light receiving part 2
The measured diameter of the hole 6a is such that the apparent diameter of the overlapping portion of the hole 6a on the light receiving part 2 side and the light source 1 side from the direction of the light receiving element 5 is approximately the diameter of the hole 6a. Therefore, the light that passes through the hole 6a and reaches the light receiving element 5 that measures the hole 6a is transmitted through the hole 6 to the light receiving element 5.
Only the amount of light corresponding to the diameter of a is received. However, as shown in FIG. 5, in the hole 6b located near the end of the object 4 in the scanning direction, the axial direction connecting the hole 6b and the light receiving element 5 for measuring the hole 6b matches the axial direction of the hole 6b. Therefore, the light receiving element 5 and the hole 6 for measuring the hole 6b are
The apparent diameter of the overlapping portion of the light-receiving part 2 side periphery and the light source 1 side periphery of the hole 6b in the axial direction connecting the holes 6b is smaller than the diameter of the hole 6b, and the object passes through the hole 6b and measures the hole 6b. The light that reaches the light receiving section 2 passes through the hole 6 in the light receiving element 5.
It is not possible to receive light corresponding to the diameter b, and the light receiving unit 2 measures the apparent diameter of the hole 6b to be smaller (hereinafter referred to as pixel missing). Also, the apparent diameter is small because
each on the edge side of the object to be measured 4 in the scanning direction;
The center side of the object to be measured 4 in the transport direction represents the position of the hole 6. Set the signal per photodetector 5 (per pixel) to be 0.1〓mm〓, and set the hole 6 diameter.
1.0〓mm〓, and the thickness of the measured object 4 is 0.8
〓mm〓, 1.0〓mm〓, 1.2〓mm〓, 1.6〓mm〓, and the distance between the object to be measured 4 and the light receiving element 5 is 85〓mm.
The distance from the center of the object to be measured 4 in the conveying direction and the change in the apparent hole diameter are shown in the sixth chart. Therefore, the thickness of object 4 in the same table is set to 1.2〓mm.
For example, when the distance from the center of the object 4 in the conveyance direction is 108.3 mm, the diameter of the hole 6 is measured to be one pixel, that is, 0.1 mm. Furthermore, at a position where the distance of the hole 6 from the center of the object to be measured 4 in the conveying direction is 216.5〓mm〓, 2 pixels,
In other words, it will be measured to a small diameter of 0.2〓mm〓.

Therefore, as described below, the erroneous measurement of the hole 6 having a small diameter is corrected.

The following is the measurement target 4 under each condition shown in Figure 6.
This is an explanation when measuring the hole 6 when the thickness of the hole 6 is 1.2 mm.

7 is a correction circuit. As shown in FIG. 7, the correction circuit 7 is a circuit for correcting the aforementioned pixel missing, and includes a determination unit 8 that determines whether the signal from the light receiving unit 2 is a signal obtained by measuring the hole 6; It is composed of a signal generation section 9 that generates a signal to be corrected, and a correction signal output section 10 that processes the signal generated by the signal generation section 9.

11 is an instruction signal generating section. The instruction signal generating unit 11 detects the position of the signal currently being scanned by the light receiving unit 2 on the object 4 in the scanning direction perpendicular to the transport direction (hereinafter, "scanning direction" refers to the "scanning direction perpendicular to the transport direction"). generates an address signal that instructs the Furthermore, the discriminating section 8, the signal generating section 9, and the correction signal outputting section 10 each generate a shift clock signal that instructs the timing of signal processing.

The determining section 8 includes a shift register 12 and an AND gate 13. The shift register 12 is capable of sequentially inputting and storing signals transmitted from the light receiving section 2 for three pixels, and can input and store the first pixel signal and input and store the second pixel signal. When the third pixel signal is input and stored, the first
The pixel signals from the second pixel signal to the third pixel signal are synchronized and output to the AND gate 13.

Next, while erasing the memory of the first pixel signal, the fourth pixel signal is input and stored, and the second pixel signal is input and stored.
The pixel signals from the fourth pixel signal to the fourth pixel signal are synchronized and output to the AND gate 13. Then the second
At the same time as erasing the memory of the th pixel signal, the 5th pixel signal is input and stored, and the 3rd pixel signal to the 5th pixel signal are synchronized and output to the AND gate 13.

In this manner, the shift register 12 synchronizes the pixel signals from the light receiving section 2 three by three pixels in the order in which they are input, and sequentially transmits the three pixels simultaneously to the AND gate 13. AND gate 13 is shift register 1
The signal measured that all three pixel signals transmitted from 2 are from hole 6, that is, the pixel signals are all 〓1〓
If so, it is determined that the measured hole 6 is the hole 6, and a signal of 〓1〓 is output. Otherwise, a signal of 〓0〓 is output. As described above, the shift register 12 and the AND gate 13 are configured such that the pixel signal is 1 for one pixel alone or for two pixels.
It functions as a so-called low-pass filter that only consecutive pixels exist, and when three or more pixels are not consecutive, it is judged as noise and is cut out. The discriminating section 8 may be provided as necessary, and in this embodiment, the discriminating section 8
is provided to determine that it is a hole 6 when there are three or more consecutive pixels, but the determination section 8, which is a low-pass filter, is not provided, and the pixel signal from the light receiving section 2 is input directly to the signal generation section 9. When the signal determines that one pixel is a hole 6, the signal generating means 9
may also output a correction signal, and the discriminator 8 is merely an additional part in the present invention. For example, if two or more consecutive pixels are to be determined as hole 6, a signal is output from the AND gate 13 when 1 is input to the shift register 12 for two or more consecutive pixels. It is sufficient if the shift register 12 can input and store two pixels. In this way, the shift register 12 can determine the amount that can be input and stored depending on the number of pixels determined to be noise. Furthermore, if noise does not occur and the hole 6 to be measured has an extremely small diameter, or if noise is not a concern, the pixel signal from the light receiving part 2 can be directly received without providing the discrimination part 8. This is done by inputting it to the signal generator 9.

The correction signal output section 10 includes an OR gate 14 which is a logic operation means, and a flip-flop circuit 15 which is a signal output maintenance means. or gate 14
has two input terminals, and input the signal 〓1〓 determined to be the hole 6 to either input terminal, or input the signal 〓1〓 determined to be the hole 6 to both input terminals. If so, output the signal 〓1〓,
If the signals at both input terminals are 0, which indicates that the area is outside the hole 6, the signal 0 is output. As shown in FIG. 7, the OR gates 14b to 14g have one input terminal capable of inputting a signal from the signal generator 9, and at the same time, the other input terminal is connected to the corresponding flip-flop circuit 15.
Output signals of a to 15f can be input. Furthermore,
Flip-flop circuits 15a-15g can receive output signals from corresponding OR gates 14a-14g, respectively. The OR gate 14a always maintains a state in which the input signal of one of the input terminals is inputted as 〓0〓, and the signal from the signal generator 9 can be input to the other input terminal.
a outputs a signal 1 when the signal input from the signal generator 9 is a signal 1 which is determined to be the hole 6 which is the measurement target, and a signal which is determined to be a part other than the hole 6 In the case of 〓0〓, the signal 〓0〓 is output, so that the same effect as when the signal from the signal generator 9 is directly inputted to the flip-flop circuit 15a without going through the OR gate 14a is achieved.

The signal generating section 9 receives the signal from the determining section 8 as well as an address signal indicating the position in the scanning direction of the object 4 at which the signal input from the determining section 8 was measured. In the signal generator 9, when the shift clock signal is input, the AND gate 13 is
When the input signal from the AND gate 13 is 〓1〓, the number of signals 〓1〓 equal to the number of input signals of the AND gate 13 plus the signal of the number of pixels to be corrected is generated, and the corresponding output logic shown in Fig. 7 is generated. It is output to the calculation means 14a to 14g. At this time, the 3 pixels are OR gate 14c
The OR gate 14 generates a signal of 1 for ~14e and outputs a signal corresponding to the number of pixels to be corrected.
is the measured object 4 of the signal input to the AND gate 13
Determined by the position from the center in the conveyance direction. Therefore, the signal from the AND gate 13 is transmitted to the object to be measured 4.
If the signal is on the scanning progress side in the scanning direction centered on the transport direction, that is, if the part where pixel loss occurs is on the scanning progress side in the scanning direction, a signal is generated to the OR gates 14a and 14b, and the transport When the center is on the side opposite to the scanning direction in the scanning direction, that is, when the portion where pixel loss occurs is on the opposite scanning direction, a signal of 1 is generated at the OR gates 14f and 14g. In this embodiment, since the pixel loss that occurs is up to 2 pixels, OR gate 1
4a to 14g, but the number of OR gates 14 can be increased or decreased depending on the pixel loss that occurs. For example, if the output signal from the AND gate 13 is 2 pixels and the amount of pixel loss that causes pixel loss is at most 4 pixels, ,
Ten OR gates 14 are required, and two pixel signals are output to the two central OR gates 14, and the number of pixels to be corrected is input to the other OR gates 14. Furthermore, the object to be measured 4 whose hole 6 is to be measured
If the above measurement position does not need to be determined as an accurate position, measurement can be performed by providing the number of OR gates 14 equal to the number of pixels determined by the determination unit 8 plus the maximum amount of missing pixels. Furthermore, even though the signal generating section 9 receives the shift clock signal from the instruction signal generating section 11, if the signal input from the AND gate 13 is 0, all the OR gates 14 receive the signal 0. Output. The flip-flop circuit 15 connects the OR gate 14 to
When the signal 〓 is received, the signal 〓1〓 is continued to be sent to the OR gate 14 to which the output section is connected until the next signal is received, and when the signal 〓0〓 is received from the OR gate 14, , 〓0〓 signal continues to be transmitted until the next signal is input. The output terminal of the flip-flop circuit 15a is connected to the other input (hereinafter referred to as the lower input terminal) of the OR gate 14b, which is not on the signal generating section 9 side, so as to output a signal. Similarly, the output terminal of the flip-flop circuit 15b is also connected to the lower input terminal of the OR gate 14c, and the flip-flop circuits 15c to
Similarly, the output terminal of 15f is connected to the OR gate 14d~
Connect 14g. flip-flop circuit 15g
connects its output terminal to the storage section 16. or,
In this embodiment, the number of flip-flop circuits 15 is seven (15a to 115g), but they are provided depending on the number of OR gates 14 required.

Next, for example, the signal generating unit 9 determines that the distance from the center of the object 4 in the conveying direction is 216.5 mm in the scanning direction.
A processing method will be explained when a signal sequentially scanned from the signal at the position 〓 is input. The distance from the center of the object to be measured 4 in the transport direction is 216.5 mm in the scanning direction.
An explanatory diagram of the signal scanned from the position is shown in FIG. 8a. Signal a at the left end of the signals in FIG. This is a signal received by the adjacent light-receiving element 5, and is a signal scanned at a position 216.5〓mm〓 from the center of the object to be measured 4 in the conveying direction in the scanning direction. Similarly, signal c is 216.7〓mm〓, and signal d is 216.7〓mm〓. 216.8〓
The signal t is a signal of 218.4 mm, and the signal u is a signal of 28.5 mm. In Figure 8a,
Of each signal, 〓1〓 is a signal generated by the light receiving section 8 when measuring the hole 6 of the object to be measured 4, and 〓0〓 is a signal generated by the light receiving section 8 when measuring a part other than the hole 6. It is.

Therefore, the signals a and b sent from the light receiving section 2 have already been input to the shift register 12, and are subjected to signal processing in the next stage and thereafter.
The signals 5a to 15g that continue to be output will be explained from the state of 〓0〓. Shift register 12 for signal c
When input, the previously input signals a, b and signal c
and simultaneously transmit it to the AND gate 13. In the AND gate 13, when the transmitted signals are all 1, therefore, if it is determined that all holes are 6, it outputs 1, and otherwise it outputs 0.
Since the signals a and b are 0, the output signal is 0 in this case. When the signal generator 9 inputs the signal from the AND gate 13, when the address signal is input, the output signal of the AND gate 13 is 〓0〓, so all the OR gates 14
Outputs the signal 〓0〓. Then, each of the OR gates 14a to 14g inputs 〓0〓 to the input terminal (hereinafter referred to as the upper input) of the signal generating section 9, and at the same time, in the OR gates 14b to 14g, the flip-flop circuits 15a to 15f have already output 〓0〓. Therefore, the signal 〓0〓 is input from the lower input terminal, and in the OR gate 14a, the lower input terminal always inputs 〓0〓.

Therefore, each OR gate 14a to 14g when the signals a, b, and c are judged by the AND gate 13
The output signal of is 〓0〓, and the flip-flop circuits 15a to 15g have 〓0〓 since the input signal is 〓0〓.
The output signal of the flip-flop circuit 15g which continues to output 〓 and outputs a signal to the storage section 16 is 〓
It becomes 0〓. Signals a, b, c are connected to AND gate 13
At the moment after the signal d is output, the signal d is input to the shift register 12, and the shift register 12 synchronizes the signals b, c, and d and outputs them to the AND gate 13 at the same time. In the AND gate 13, the signal b is 0
Since 0 is output to the signal generating section 9.
Since the signal generator 9 receives the signal 〓0〓, the signal generator 9, the OR gates 14a to 14g, and the flip-flop circuits 15a to 15g receive the signals a, b,
The operation is the same as when the AND gate 13 judges c, and therefore, in order from the flip-flop circuit 15g, 0, 0, 0, 0, 0,
The flip-flop circuit 15g continues to output 〓0〓 and 〓0〓, and outputs 〓0〓 to the storage section 16.

Next, as a result of the judgment of the signals b, c, and d by the AND gate 13, the flip-flop circuit 15g outputs a signal to the storage section 16, and at the next instant, the shift register 12 inputs the signal e, and the shift register 1
2 synchronizes the signals c, d, and e and outputs them to the AND gate 13 at the same time. In the AND gate 13, the signals c, d, and e are all 1, so the signal generator 9
Output 〓1〓 to. The signal generator 9 inputs the signal 〓1〓 from the AND gate 13, and also simultaneously receives the signal cd, which is currently being processed based on the address signal.
e is from the center of the object to be measured 4 in the transport direction to the scanning direction.
The signals are at distances of 216.7〓mm〓, 216.8〓mm〓, and 26.9〓mm〓, and it is detected that the number of pixels to be corrected is 2 pixels in the scanning direction (in Figure 5, the substrate thickness
See column 1.2mm, 216.5mm. ), the signal for 5 pixels is output as 〓1〓 to the OR gates 14a to 14e, and the OR gates 14f and 14g are output as 〓0〓.
Output. The upper input of the OR gate 14g is the signal 0 from the signal generator 9, and the lower input is the signal b, c, d from the flip-flop circuit 14f.
A signal generated during a series of circuit operations that processed
Since the signal is 0, the signal 0 is output to the flip-flop circuit 15g. Then, the flip-flop circuit 15g receives 0 from the OR gate 14g, so it continues to output 0 to the storage unit 16 until the next signal is input. Or Gate 14f
The upper input is 〓0〓, and the lower side input is the signal 〓0〓 generated when the flip-flop circuit 14e processes the signals b, c, and d, so the output signal is 〓0〓. Flip-flop circuit 15f
inputs the signal 0 from the OR gate 14f, so it continues to output the signal 0 until the next signal is input. The OR gate 14e inputs the signal 1 from the signal generator 9 to its upper input terminal, and the flip-flop circuit 15d to its lower input terminal.
Since the signal 〓0〓 generated when the signals b, c, and d are processed is inputted, the output signal 〓1〓 is obtained, and the flip-flop circuit 15e inputs the signal 〓1〓 output from the OR gate 14e. , continues to output 〓1〓 until the next signal is input. The OR gate 14d inputs the signal 〓1〓 from the signal generator 9 to its upper input terminal, and the flip-flop circuit 15c inputs the signal 〓1〓 from the signal generator 9 to its lower input terminal.
Since the signal 〓0〓 which has been generated since processing c and d is input, the output signal becomes 〓1〓, and the flip-flop circuit 15d inputs the signal 〓1〓 output from the OR gate 14d.
It continues to output the signal 〓1〓 until the next signal is input. Similarly to the OR gate 14d, the upper input of the OR gates 14c to 14a is the signal 〓1〓 from the signal generator 9, so the output signal is 〓1〓.
〓, and the flip-flop circuits 15c to 15a
also input the signals 〓1〓 from the OR gates 14c to 14a, respectively, so the output signals are 〓1〓
, and continues to output 1 until the next signal is input. Therefore, by a series of circuit operations after the shift register 12 inputs the signal e, the flip-flop circuits 15g to 15a are activated by the shift register 12.
inputs the next signal f and performs a series of circuit operations until the flip-flop circuit 15 inputs the signal.
From flip-flop circuit 15g, 〓0〓,〓
0〓,〓1〓,〓1〓,〓1〓,〓1〓,〓1〓
continues to output the signal. Flip-flop circuit 1
5g continues to output the signal [0〓 to the storage unit 16 until the next input signal is received, and the output signals of the other flip-flop circuits 15f to 15a are outputted from the series of signals after the shift register 12 inputs the signal f. As the lower input of the OR gate 14 during circuit operation,
It continues to output until the next signal is input.

Next, the signals c, d, and e are synchronized and input to the AND gate 13 at the same time. As a result, at the next moment when the flip-flop circuit 15g outputs the signal to the storage section 16, the shift register 12 inputs the signal e and outputs the signal. At the next moment when c, d, and e are synchronized and simultaneously output to the AND gate 13, the shift register 1
2 inputs the signal f 〓1〓, synchronizes the previously input signals e and d with the signal f, and outputs them to the AND gate 13 at the same time. In the AND gate 13, since the signals d, e, and f are all 〓1〓, the signal 〓1〓
Output. Then, the signal generator 9 inputs the signal 〓1〓, and similarly to the processing of the signal generator 9 during the series of processing of signals c, d, and e, the number of pixels to be supplemented by the address signal is 2 pixels. It detects this and outputs 〓1〓 to the OR gates 14e to 14a, and outputs 〓0〓 to the OR gates 14g to 14f.
The upper input of the OR gate 14g is the signal generator 9.
The lower input is the signal c,
Since the signal 〓0〓 is outputted by the flip-flop circuit 15f during the series of circuit operations that processed d and e, the signal 〓0〓 is outputted by the flip-flop circuit 15f.
Since the flip-flop circuit 15g receives the signal 0 from the OR gate 14, it continues to output the signal 0 until the next signal is input. The upper input of the OR gate 14f receives the signal 〓0〓 from the signal generator 9, and the lower input receives the signal 〓 which continues to be output from the flip-flop circuit 15e during a series of circuit operations that processed the signals c, d, and e.
1〓 is input, so the signal 〓1〓 is output to the flip-flop circuit 15f, and the flip-flop circuit 15f receives the signal 〓1〓 from the OR gate 14f.
is input, and the resulting signal 〓1〓 continues to be output until the next signal is input. Similarly, Orgate 14
In e to 14a, either or both of the upper input terminal and the lower input terminal has a signal of 1, so all output signals thereof are 1.
Since the input signals of the flip-flop circuits 15e to 15a which receive the output signals of the OR gates 14e to 14a are 1, respectively, they continue to output the signal 1 until the next signal is input. Therefore,
A shift register 12 synchronizes the signals d, e, f,
Flip-flop circuits 15g to 1 based on a series of circuit operations after simultaneously outputting to the AND gate 13
The output signals of the flip-flop circuit 5a are 0, 1, 1, 1, 1 in order from the flip-flop circuit 15g.
〓, 〓1〓, 〓1〓, and the memory unit 16 stores 〓0.
Outputs 〓.

Next, the shift register 12 inputs the signal f and synchronizes the signals d, e, f and outputs them to the AND gate 13 at the same time.
2 inputs the signal g 〓0〓, synchronizes with the already input signals e and f, and at the same time, AND gate 1
Output to 3. Since the signal g is 0, the AND gate 13 outputs the signal 0 to the signal generator 9. Although the number of corrected pixels detected by the signal generating section 9 is two pixels, the input signal from the AND gate 13 is 0, so it outputs a signal 0 to all OR gates 14g to 14a.
The upper input signal of the OR gate 14g is the signal 〓0〓 from the signal generator 9, and the lower input signal is
Since the flip-flop circuit 15f continues to output the signal 〓1〓 during a series of circuit operations after the shift register 12 inputs the signal f, the output signal of the OR gate 14g becomes 〓1〓. The flip-flop circuit 15g inputs the output signal 〓1〓 of the OR gate 14g, and continues to output the signal 〓1〓 until the next signal is input. or gate 14
The upper input signal of f is the signal 〓0〓 output by the signal generator 9, and the lower input signal is the output of the flip-flop circuit 15e during a series of circuit operations after the shift register 12 inputs the signal f. Since the signal 〓1〓 continues, the output signal of the OR gate 14f is 〓1〓. Flip-flop circuit 1
5f inputs the output signal 〓1〓 of the OR gate 14f, and continues to output the signal 〓1〓 until the next signal is input. Similarly below, or gate 14e~1
Since the upper input signal of 4b is 0 and the lower input signal is 1, their output signals are 1 and the flip-flop circuits 15e to 15
Since the input signal of b is the signal 〓1〓 output from the OR gates 14e to 14b, the signal 〓1〓 continues to be outputted until the next signal is input.
The upper input signal of the OR gate 14a is the signal 〓0〓 outputted by the signal generator 9, and the lower side input signal is also always 〓0〓, so its output signal is 〓0〓, and the flip-flop circuit 15a outputs the signal 〓0〓. Input the output signal 〓0〓, stop the output of the signal 〓1〓 that has been outputting until now, and output the signal 〓
Continue outputting 0〓 until the next signal is input. Therefore, the shift register 12 synchronizes the signals e, f, and g and simultaneously outputs them to the AND gate 13. Through a series of circuit operations, the flip-flop circuit 15
The output signals of the flip-flop circuits g to 15a are 1, 1, 1, and 1 in order from the flip-flop circuit 15g.
〓, 〓1〓, 〓1〓, 〓0〓, and the storage unit 16
Output 〓1〓 to.

Next, at the next moment when the flip-flop circuit 15g outputs the signal 〓1〓 to the storage section 16 as a result of the judgment of the signals e, f, and g by the AND gate 13,
The shift register 12 inputs the signal h, and furthermore,
The previously input signals f and g and the signal h are synchronized and output to the AND gate 13 at the same time. In the AND gate 13, the signals g and h are 〓0〓, and the signal h is 〓1〓, so the signal 〓0〓 is sent to the signal generator 9
Output to. In the signal generating section 9, the AND gate 13
As a result of inputting the signal from the AND gate 13, it is detected that the number of pixels to be corrected is 2 pixels by the address signal, but since the signal from the AND gate 13 is 〓0〓, all the OR gates 14g to 14a are , outputs a signal 〓0〓. Therefore, the upper input signals of the OR gates 14g to 14a are all 〓0〓, and the lower input signals of the OR gates 14g to 14a are all 〓0〓.
Since 〓1〓 in c, or gate 1
The output signals of 4g to 14c are 1, respectively, and each flip-flop circuit 15g corresponds to the output.
~15c inputs the signal 〓1〓 and continues to output 〓1〓 until the next signal is input. or gate 1
The lower input signal of 4b is the signal that the flip-flop circuit 15a continues to output during a series of circuit operations after the shift register 12 inputs the signal g.
0〓, and both the upper side input signal and the lower side input signal are 〓0〓, so the output signal is 〓0〓. Since the flip-flop circuit 15b receives the signal 0 which is output from the OR gate 14b, its output signal is 0, and it continues to output 0 until the next signal is input. Or gate 14a
Since the lower input signal of the circuit is always 〓0〓 and the upper side input signal is also 〓0〓, its output signal becomes 〓0〓, and the flip-flop circuit 15a inputs the output signal 〓0〓 of the OR gate 14a, and then Continue outputting 〓0〓 until a signal is input. Follow. During a series of circuit operations after the shift register 12 synchronizes the signals f, g, and h and simultaneously outputs them to the AND gate 13, the signals output from the flip-flop circuits 15g to 15a are sequentially from the flip-flop circuit 15g to 1, 〓1〓,〓1〓,〓1〓,〓1
〓, 〓0〓, 〓0〓, and goes to the storage unit 16〓1〓
Output.

Next, the shift register 12 inputs the signal h and synchronizes the signals f, g, h and outputs them to the AND gate 13 at the same time.
2 inputs the signal i 〓1〓, synchronizes with the already input signals g and h, and at the same time inputs the AND gate 1
Output to 3. In the AND gate 13, the signals g,
Since h is 0 and the signal i is 1, the signal 0 is output to the signal generator 9. Signal generator 9
The number of corrected pixels detected by the address signal is 2 pixels, but the input signal from the AND gate 13 is 0, so all OR gates 14g to 14a
Outputs the signal 〓0〓. Orgate 14g
In this case, the upper input signal is the signal from the signal generator 9 =0
〓, and the lower input signal is the shift register 12
Since this is the signal 〓1〓 which continues to be outputted by the flip-flop circuit 15f during a series of circuit operations after inputting the signal h, the output signal of the OR gate 14g becomes 〓1〓. The flip-flop circuit 15g inputs the output signal 〓1〓 of the OR gate 14g, and continues to output the signal 〓1〓 until the next signal is input. The upper input signal of the OR gate 14f is the signal [0〓 output from the signal generator 9, and the lower input signal is the output of the flip-flop circuit 15e during a series of circuit operations after the shift register 12 inputs the signal h. Since the signal continues to be 〓1〓, the output signal of the OR gate 14f is 〓1〓. The flip-flop circuit 15f receives the output signal 〓1〓 of the OR gate 14f, and continues to output the signal 〓1〓 until the next signal is input. Similarly, since the upper input signal of the OR gates 14e and 14d is 0 and the lower input signal is 1, their output signals are 1, respectively, and the signals input to the flip-flop circuits 15e and 15d are the OR gates. 14e and 14d output the signal 〓1〓, and each continues to output the signal 〓1〓 until the next signal is input. The lower input signal of the OR gate 14c is the signal 〓0〓 that the flip-flop circuit 15b continues to output during a series of circuit operations after the shift register 12 inputs the signal h; Since both signals are 〓0〓, the output signal is 〓0〓. Since the flip-flop circuit 15c receives the signal 〓0〓 output from the OR gate 14c, it continues to output 〓0〓 until the next signal is input. or gate 1
Similar to the OR gate 14c, the upper input signal and the lower input signal of the OR gate 4b are both 0, so the output signal is also 0, and the flip-flop circuit 15
Similarly to the flip-flop circuit 15c, the input signal for b is 0, so it remains 0 until the next signal is input.
Continue to output 0〓. The upper input signal of the OR gate 14a is the signal 〓0〓 outputted by the signal generator 9, and the lower side input signal is also always 〓0〓, so its output signal is 〓0〓, and the flip-flop circuit 15a outputs the signal 〓0〓. Output signal 〓0〓
is input, and the signal 〓0〓 continues to be output until the next signal is input. Therefore, the shift register 12 synchronizes the signals g, h, i, and at the same time the AND gate 13
Through a series of circuit operations after the output to the flip-flop circuits 15g to 15a, the output signals of the flip-flop circuits 15g to 15a are sequentially output from the flip-flop circuit 15g to
〓, 〓1〓, 〓1〓, 〓0〓, 〓0〓, 〓0〓, and output 〓1〓 to the storage section 16.

Next, at the next moment when the shift register 12 inputs the signal i and simultaneously outputs the signals g, h, and i to the AND gate 13, the shift register 12 inputs the signal j, 〓1〓, It is synchronized with the signals h and i that have already been input, and is output to the AND gate 13 at the same time. In the AND gate 13, the signal h
Since is 0, the signal 0 is output to the signal generator 9. Although the number of corrected pixels detected by the signal generating section 9 is two pixels, the input signal from the AND gate 13 is 0, so it outputs a signal 0 to all OR gates 14g to 14a. The upper input signal of the OR gate 14g is the signal 〓0〓 from the signal generator 9, and the lower input signal is the flip-flop circuit 15 during a series of circuit operations after the shift register 12 inputs the signal i.
Since the signal 〓1〓 continues to be outputted by f, the output signal of the OR gate 14g becomes 〓1〓. Then, the flip-flop circuit 15g inputs the output signal 〓1〓 of the OR gate 14g, and continues to output the signal 〓1〓 until the next signal is input. The upper input signal of the OR gate 14f is the signal 〓0〓 output from the signal generator 9, and the lower input signal is the output of the flip-flop circuit 15e during a series of circuit operations after the shift register 12 inputs the signal i. Since the signal continues to be 〓1〓, OR gate 1
The output signal of 4f is 〓1〓. The flip-flop circuit 15f inputs the output signal 〓1〓 of the OR gate 14f, and keeps the signal 〓〓until the next signal is input.
Continue to output 1〓. Similarly, or gate 14e
Since the upper input signal is 0 and the lower input signal is 1, the output signal is 1, and the input signal of the flip-flop circuit 15e is the signal 1 output from the OR gate 14e. Therefore, the signal 1 continues to be output until the next signal is input. The lower input signal of the OR gate 14d is
The flip-flop circuit 15c continues to output the signal 〓0〓 during a series of circuit operations after the shift register 12 inputs the signal i, and both the upper input signal and the lower input signal become 〓0〓. Its output signal is 〓0〓. The flip-flop circuit 15d receives the signal =0 output from the OR gate 14d.
Since 〓 is input, its output signal continues to output 〓0〓 until the next signal is input. or gate 1
Similarly to the OR gate 14d, both the upper input signal and the lower input signal of the flip-flop circuits 4c and 14b are 0, so their output signals are 0, and the flip-flop circuits 15c and 15b are also the same as the flip-flop circuit 15d.
Similarly, since the input signal is 0, it continues to output 0 until the next signal is input. The upper input signal of the OR gate 14a is the signal 〓0〓 output from the signal generator 9, and the lower side input signal is always 〓0〓.
Therefore, the output signal is 0, and the flip-flop circuit 15a inputs the output signal 0 of the OR gate 14a and continues to output the signal 0 until the next signal is input. Therefore, by a series of circuit operations after the shift register 12 synchronizes the signals h, i, and j and simultaneously outputs them to the AND gate 13, the signals output from the flip-flop circuits 15g to 15a are sequentially output from the flip-flop circuit 15g to 1. 〓,〓1〓,〓1〓,〓0〓,〓0〓,
〓0〓, 〓0〓, and output 〓1〓 to the storage section 16.

Next, the shift register 12 inputs the signal j and synchronizes the signals h, i, and j and outputs them to the AND gate 13 at the same time.
2 inputs the signal k 〓0〓, synchronizes with the already input signals i and j, and at the same time, AND gate 1
Output to 3. Since the signal k is 0, the AND gate 13 outputs the signal 0 to the signal generator 9. Although the number of corrected pixels detected by the signal generating section 9 is two pixels, the input signal from the AND gate 13 is 0, so it outputs a signal 0 to all OR gates 14g to 14a.
The upper input signal of the OR gate 14g is the signal 〓0〓 from the signal generator 9, and the lower input signal is
Since the flip-flop circuit 15f continues to output the signal 〓1〓 during a series of circuit operations after the shift register 12 inputs the signal j, the output signal of the OR gate 14g becomes 〓1〓. The flip-flop circuit 15g inputs the output signal 〓1〓 of the OR gate 14g, and continues to output the signal 〓1〓 until the next signal is input. Or gate 14f
, the upper input signal is the signal 〓0〓 output from the signal generator 9, and the lower input signal is the signal 〓0〓 output from the shift register 1.
Since 2 is the signal 〓1〓 that the flip-flop circuit 15e continues to output during a series of circuit operations after inputting the signal j, the output signal of the OR gate 14f is 〓1〓. Flip-flop circuit 15
f inputs the output signal 〓1〓 of the OR gate 14f, and continues to output the signal 〓1〓 until the next signal is input. The lower input signal of the OR gate 14e is applied to the flip-flop circuit 15 during a series of circuit operations after the shift register 12 inputs the signal j.
Since d is the signal 〓0〓 that continues to be output, and both the upper input signal and the lower input signal are 〓0〓,
Its output signal is 〓0〓. Since the flip-flop circuit 15e receives the signal 〓0〓 output from the OR gate 14e, the flip-flop circuit 15e receives the signal 〓0〓 output from the OR gate 14e, so until the next signal is input,
Continue to output 0〓. Or gate 14d~14b
Similarly to the OR gate 14e, both the upper input signal and the lower input signal are 0, so the output signal is also 0, and the flip-flop circuits 15d to 1
Similarly to the flip-flop circuit 15e, the input signal to the flip-flop circuit 5b is 0, so it continues to output 0 until the next signal is input. The upper input signal of the OR gate 14a is the signal 〓0〓 output from the signal generator 9.
Since the lower input signal is always 0, the output signal of the OR gate 14a is 0, and the flip-flop circuit 15a inputs the output signal 0 of the OR gate 14a, and then outputs the signal 0. Continue outputting until input. Therefore, through a series of circuit operations after the shift register 12 synchronizes the signals i, j, and k and simultaneously outputs them to the AND gate 13, the signals output from the flip-flop circuits 15g to 15a are sequentially output from the flip-flop circuit 15g to 1. 〓,〓1〓,〓0〓,〓0〓,〓0〓,〓
0〓,〓0〓, and outputs 〓1〓 to the storage section 16.

Next, the shift register 12 inputs the signal k and synchronizes the signals i, j, k and outputs them to the AND gate 13 at the same time.
2 inputs the signal l 〓1〓, synchronizes with the already input signals j and k, and at the same time, AND gate 1
Output to 3. Since the signal k is 0, the AND gate 13 outputs the signal 0 to the signal generator 9. Although the number of corrected pixels detected by the signal generating section 9 is two pixels, the input signal from the AND gate 13 is 0, so it outputs a signal 0 to all OR gates 14g to 14a.
The upper input signal of the OR gate 14g is the signal 〓0〓 from the signal generator 9, and the lower input signal is
Since the flip-flop circuit 15f continues to output the signal 〓1〓 during a series of circuit operations after the shift register 12 inputs the signal k, the output signal of the OR gate 14g becomes 〓1〓. The flip-flop circuit 15g inputs the output signal 〓1〓 of the OR gate 14g, and continues to output the signal 〓1〓 until the next signal is input. Or Gate 14f
The lower input signal of the shift register 12 is the signal k
The signal 〓0〓 that the flip-flop circuit 15e continues to output during a series of circuit operations after inputting
, and both the upper input signal and the lower input signal are 0.
〓, so the output signal is 〓0〓. Since the flip-flop circuit 15f receives the signal 〓0〓 output from the OR gate 14f, it continues to output 〓0〓 until the next signal is input. or gate 14
Similarly to the OR gate 14f, the upper input signal and the lower input signal of e-14b are also 0, so the output signal thereof is 0, and the flip-flop circuits 15e-15b also have an input signal of 0, similar to the flip-flop circuit 15f. Therefore, it continues to output 〓0〓 until the next signal is input. The upper input signal of the OR gate 14a is the signal 〓0〓 outputted by the signal generator 9, and the lower side input signal is always 〓0〓, so the output signal is 〓0〓, and the flip-flop circuit 15a outputs the signal 〓0〓. The output signal 〓0〓 is input, and the signal 〓0〓 continues to be output until the next signal is input. Therefore, by a series of circuit operations after the shift register 12 synchronizes the signals j, k, and l and outputs them to the AND gate 13 at the same time, the signals output from the flip-flop circuits 15g to 15a are sequentially output from the flip-flop circuit 15g to 1. 〓、〓0〓、〓0〓、〓0〓、〓0〓、〓
0〓,〓0〓, and outputs 〓1〓 to the storage section 16.

Next, the shift register 12 inputs the signal l and synchronizes the signals j, k, l and outputs them simultaneously to the AND gate 13. At the next moment, the shift register 1
2 inputs the signal m, 〓1〓, synchronizes with the already input signals k and l, and at the same time, AND gate 1
Output to 3. Since the signal k is 0, the AND gate 13 outputs the signal 0 to the signal generator 9. Although the number of corrected pixels detected by the signal generating section 9 is two pixels, the input signal from the AND gate 13 is 0, so it outputs a signal 0 to all OR gates 14g to 14a.
The lower input signal of the OR gate 14g is the signal 〓0〓 that the flip-flop circuit 15f continues to output during a series of circuit operations after the shift register 12 inputs the signal l; Since both signals become 〓0〓, the output signal is 〓0〓. Since the flip-flop circuit 15g receives the signal 〓0〓 output from the OR gate 14g, its output signal continues to output 〓0〓 until the next signal is input. Or Gate 14f~1
Similar to the OR gate 14g, the upper input signal and the lower input signal of the OR gate 4b are both [0], so the output signal is also 0, and the flip-flop circuit 15
Similarly to the flip-flop circuit 15f, the input signal of f to 15b is [0], so it continues to output 0 until the next signal is input. or gate 14
The upper input signal of a is the signal 〓0〓 outputted by the signal generator 9, and the lower side input signal is always [0], so the output signal is 〓0〓, and the flip-flop circuit 15a outputs the signal 〓0〓 from the OR gate 14a. Input the output signal 〓0〓 and continue outputting the signal 〓0〓 until the next signal is input. Therefore, by a series of circuit operations after the shift register 12 synchronizes the signals k, l, and m and simultaneously outputs them to the AND gate 13, the signals output from the flip-flop circuits 15g to 15a are sequentially output from the flip-flop circuit 15g to
0〓,〓0〓,〓0〓,〓0〓,〓0〓,〓0
〓, 〓0〓, and output 〓0〓 to the storage section 16.

Next, the shift register 12 inputs the signal n, synchronizes the signals l, m, and n, and simultaneously outputs them to the AND gate 13.
The array of signals up to is the signal k below the signals d, e, and f.
The signals l, m,
The circuit operation up to the signal s below n is the same as the circuit operation up to the signal k below d, e, f.
The output signal to will also be the same signal sequence. Furthermore, the circuit operation when the shift register 12 inputs the signal t, synchronizes the signals r, s, and t, and outputs them to the AND gate 13 at the same time is as follows: The shift register 12 inputs the signal l, and synchronizes the signals j, k, and l. The circuit operates in the same way as when both are simultaneously output to the AND gate 13, and 〓1〓 is output to the storage section 16. Further, the circuit operation when the shift register 12 inputs the signal u is similar to the circuit operation when the shift register 12 inputs the signal m, and the output signal to the storage section 16 becomes 〓0〓. A comparison of the signal input to the storage section 16 as described above and the signal transmitted from the light receiving section 2 to the shift register 12 is as shown in FIG. 9a. Signal string A in FIG. 9a is a signal string output from the light receiving section 2, and signal string B is a signal string inputted to the storage section 16. In the signal sequence A, the signal c is the signal 〓1〓 which detects that the hole 6 is present, and in the corresponding signal sequence B, the signal 〓 〓 when the signal e′ is detected as the hole 6.
This signal is inputted to the storage unit 16 as 1〓.
Therefore, the input signal to the storage section 16 is input two pixels later than the signal input to the light receiving section 2.
Furthermore, a signal string below signal c of signal string A and signal string B
When comparing the signal sequence below signal e', the signal sequence A
In this case, the signal for 4 pixels below signal c is the signal that detected hole 6, and in the corresponding signal part of signal sequence B, the signal for 6 pixels below signal e' is the signal for detecting hole 6. Yes, the measurement object 4 is output after being corrected by an increase of two pixels toward the scanning direction from the center in the conveyance direction. Therefore, the hole 6 exists on the traveling direction side from the center in the transport direction, and the diameter apparently becomes smaller from the center in the transport direction to the edge side of the object to be measured 4, so that the hole 6 increases by two pixels toward the edge side of the object to be measured 4. The corrected diameter of the hole 6 is output.

Next, for example, the signal generating unit 9 determines that the distance from the center of the object 4 in the transport direction is 218.5〓 in the counter-scanning direction.
A processing method will be described in the case where a signal scanned sequentially toward the center of the object to be measured 4 in the conveying direction is input from a signal at a position of mm〓. FIG. 8b shows an explanatory diagram of a signal that is scanned from a position at a distance of 218.5 mm in the counter-scanning direction from the center of the object to be measured 4 in the conveying direction. The signal a at the left end of the signals in FIG. 8b is a signal obtained by scanning a position 218.5 mm in the counter-scanning direction from the center of the object 4 in the conveyance direction, and the signal b is a signal obtained by scanning the light receiving element 5 that receives the signal a. It is a signal received by the light receiving element 5 adjacent to , and is a signal scanned at a position of 218.4〓mm〓 from the center of the conveyance direction of the object to be measured 4 in the counter-scanning direction. d is 218.2〓
The signal t is a signal of 216.6 mm, and the signal u is a signal of 216.5 mm. In Figure 8b,
Of each signal, 〓1〓 is a signal generated by the light receiving section 8 when measuring the hole 6 of the object to be measured 4, and 〓0〓 is a signal generated by the light receiving section 8 when measuring a part other than the hole 6. It is.

Therefore, the signals a and b transmitted from the light receiving section 2 have already been input to the shift register 12, and are subjected to signal processing in the next stage and thereafter, and all the signals that the flip-flop circuits 15a to 15g continue to output are 0. Let's start with the state. When the shift register 12 inputs the signal c, the previously input signals a and b
and signal c are synchronized and transmitted to the AND gate 13.
In the AND gate 13, when all the transmitted input signals are 〓1〓, therefore, when it is determined that all the input signals are 〓1〓, it outputs 〓1〓, and otherwise 〓
In order to output 0〓, the signals a and b are 〓0〓, so in this case, the output signal becomes 〓0〓. Signal generator 9 that inputs the signal from AND gate 13
Since the output signal of the AND gate 13 is 〓0〓 when the address signal is input, the signal 〓0〓 is output to all the OR gates 14. Then, each of the OR gates 14a to 14g inputs 〓0〓 to the input terminal (hereinafter referred to as upper input) of the signal generating section 9, and at the same time, in the OR gates 14b to 14g, the flip-flop circuits 15a to 15f have already input 〓0〓.
Since it continues to output 0〓, input the signal 〓0〓 from the lower input terminal, and also input the signal 〓0〓 to the OR gate 14a.
In this case, the lower input terminal always inputs 〓0〓. Therefore, the signals a, b, and c are connected to the AND gate 13.
Each or gate 14a-1 when judged by
The output signal of the flip-flop circuit 4g is 〓0〓, and the input signal of the flip-flop circuits 15a to 15g is 〓0〓.
〓,〓0〓,〓0〓,〓0〓,〓0〓,〓0〓,
The output signal of the flip-flop circuit 15g which continues to output 〓0〓 and outputs a signal to the storage section 16 is 〓0〓.
becomes. The output signals of the flip-flop circuits 15a to 15f generated as a result of the input and judgment of the signals a, b, and c by the AND gate 13 are
3 determines the signals b, c, and d, the OR gates 14b to 14b simultaneously generate the signals generated by the signal generator 9.
This is the signal input to the lower input terminal of 14g.

Then, the shift register 12 receives the signals a, b, c.
At the next moment after outputting the signal d to the AND gate 13, the signal d is input to the shift register 12, and the shift register 12 synchronizes the signals b, c, and d and outputs them to the AND gate 13. Since the signal b is 0, the AND gate 13 outputs 0 to the signal generator 9. Since the signal generator 9 inputs the signal 〓0〓, the signal generator 9 and the OR gates 14a to 14
g, the flip-flop circuits 15a to 15g operate in the same way as when the AND gate 13 judges the signals a, b, and c, and therefore, the flip-flop circuits 15g and 15g operate in the same way as 〓0〓, 〓0〓, 〓0〓, 〓 0
The flip-flop circuit 15g continues to output the signals 〓, 〓0〓, 〓0〓, 〓0〓, and the flip-flop circuit 15g sends the signal 〓0〓 to the storage section 16.
Outputs 〓.

Next, as a result of the judgment of the signals b, c, and d by the AND gate 13, the flip-flop circuit 15g outputs a signal to the storage section 16, and at the next instant, the shift register 12 inputs the signal e, and the shift register 1
2 synchronizes signals c, d, e, and gate 13
Output to. In the AND gate 13, the signals c, d,
Since all values of e are 1, the signal generator 9 receives 1
Output. The signal generator 9 inputs the signal 〓1〓 from the AND gate 13, and at the same time, the signals c, d, and e to be currently processed are 218.3〓 from the center of the conveyance direction of the object to be measured 4 in the counter-scanning direction.
mm〓, 218.2 [mm〓, 218.1〓mm〓] It is detected that the number of signals to be corrected is 2 pixels on the anti-scanning direction side, so the signal for 5 pixels is 〓1〓 is output to the OR gates 14c to 14g, and 0 is output to the OR gates 14a and 14b. The upper input of the OR gate 14g is the signal 〓1〓 from the signal generator 9, and the lower input is the signal 〓0〓 generated when the flip-flop circuit 15f processes the signals b, c, and d.
〓 is output to the flip-flop circuit 15g. Then, the flip-flop circuit 15g receives the signal 1 from the OR gate 14g, so it continues to output the signal 1 to the storage section 16 until the next signal is input. The upper input of the OR gate 14f is the signal 〓1〓
The lower input is a flip-flop circuit 15e.
Since this is the signal 〓0〓 generated when the signals b, c, and d are processed, its output becomes 〓1〓. The flip-flop circuit 15f is an OR gate 14f.
Since the signal 〓1〓 is input from , the signal 〓1〓 continues to be output until the next signal is input. Or gate 14e, 14d, 14c is also or gate 14f
Similarly, the upper input from the signal generator 9 is the signal 〓1〓
, and the lower input is a flip-flop circuit 15.
Since d, 15c, and 15b are the signals 〓0〓 generated when signals b, c, and d are processed, they output 〓1〓 similarly to the OR gate 14f, and input the signals from the OR gates 14e, 14d, and 14c. Similarly to the flip-flop circuit 15f, the output signals of the flip-flop circuits 15e, 15d, and 15c are 1
〓, and continues outputting the signal 〓1〓 until the next signal is input. The OR gate 14b receives the signal 〓0〓 from the signal generator 9 at its upper input, and the flip-flop circuit 15a receives the signals b, c,
Since the signal 〓0〓 obtained when processing d is input, the output of the OR gate 14b becomes 〓0〓. The upper input of the OR gate 14a receives the signal 0 from the signal generator 9, and the lower input is always 0, so the output signal is 0. Therefore, the output signals of the flip-flop circuits 15b and 15a are
Since the input signals from the OR gates 14b and 14a are 〓0〓, the output becomes 〓0〓 and continues to be output until the next signal is input. Therefore, by a series of circuit operations after the shift register 12 inputs the signal e, the flip-flop circuits 15g to 1
5a, the shift register 12 inputs the signal f and performs a series of circuit operations, starting from the flip-flop circuit 15g in order until the signal is input to the flip-flop circuits 15g to 15a.
It continues to output the signals 〓, 〓1〓, 〓1〓, 〓0〓, 〓0〓. The output signal of the flip-flop circuit 15g is output to the storage unit 16 until the flip-flop circuit 15g inputs the next signal, and the output signals of the other flip-flop circuits 15f to 15a are outputted to the storage unit 16 until the flip-flop circuit 15g inputs the next signal. OR gate 14 in the operation of a series of circuits from
It is output as the lower input signal until the next signal is input.

Next, the signals c, d, and e are synchronized and input to the AND gate 13, and as a result, the flip-flop circuit 1
5g outputs a signal to the storage section 16, therefore, the shift register 12 inputs the signal e and outputs the signals e, d, and e to the AND gate 13 in synchronization. The register 2 inputs the signal f, 〓1〓, synchronizes the previously input signals d and e with the signal f, and outputs them to the AND gate 13 at the same time. In the AND gate 13, the signals d, e, f
Since all are 〓1〓, the signal 〓1〓 is output. Then, the signal generator 9 inputs the signal 〓1〓, and further, like the processing of the signal generator 9 during the series of processing of the signals c, d, and e, the number of pixels to be corrected in the counter-scanning direction is 2 according to the address signal. It detects that it is a pixel, and outputs 〓1〓 to the OR gates 14g to 14c, and outputs 〓0〓 to the OR gates 14a and 14b. Since the upper input of the OR gates 14g to 14c is 〓1〓, the flip-flop circuit 1
The output signal to 5g to 15c becomes 〓1〓. Further, the upper input from the signal generator 9 of the OR gate 14b receives the signal 〓0〓, and the lower side input receives the signal 〓0〓 generated by the flip-flop circuit 15a when processing the signals c, d, and e. Therefore, the output signal of the OR gate 14b becomes 〓0〓, and the flip-flop circuit 15b outputs the output signal of the OR gate 14b.
Since 〓0〓 is inputted, the generated signal becomes 〓0〓. In the OR gate 14a, the upper input receives 〓0〓 from the signal generator 9, and the lower input always receives 〓0〓, so its output signal becomes 〓0〓, and the flip-flop circuit 15a receives 〓0〓 from the OR gate 14a. is input, the generated signal becomes 〓0〓, and the signal continues to be output until the next signal is input. Therefore, the shift register 12 synchronizes the signals d, e, f and the AND gate 1
The signals output from the flip-flop circuits 15g to 15a by a series of circuit operations after the output from the flip-flop circuit 15g are sequentially 〓1〓,〓
1〓,〓1〓,〓1〓,〓1〓,〓0〓,〓0〓
Therefore, 〓1〓 is output to the storage section 16.

Next, as described above, the shift register 12 inputs the signal g, synchronizes with the signals e and f, and outputs the AND gate 1.
Output to 3. The signals e and f are both 〓1〓, but the signal g is 〓0〓, so the AND gate 13 becomes 〓
The signal generator 9 which outputs 0〓 and inputs the signal from the AND gate 13 outputs the signal 〓0〓 to all the OR gates 14 because the input signal is 〓0〓.
The upper input of the OR gate 14g which inputs 0 from the signal generator 9 is 0, but the lower input receives the signal from the flip-flop circuit 15f during operation of a series of circuits that processed the signals d, e, and f. Since it continues to output 〓1〓, 〓1〓 is input, and its output signal becomes 〓1〓. Similarly, Orgate 14
For f, the upper input is 0, the lower input is 1, and the output is 1, which is the OR gate 14.
For e and 14d, the upper input is 0 and the lower input is 1, so they output 1. The flip-flop circuits 15g to 15d are connected to the OR gate 14.
Since the input signals from g to 14d are each 1, the signal [1] continues to be output. or gate 1
4c, the upper input signal from the signal generator 9 is
0〓, and the lower input signal from the flip-flop circuit 15b is also 〓0〓, so its output signal becomes 〓0〓, and the OR gates 14b and 14a also have both upper and lower inputs as 〓0〓.
The output becomes 0, and since the flip-flop circuits 15c to 15a receive the signal 0 from the corresponding OR gates 14c to 14a, they continue to output the signal 0. Therefore, the flip-flop circuit 15g is generated by a series of circuit operations after the shift register 12 inputs the signals e, f, and g.
The signals output by ~15a are 〓1〓, 〓1〓, 〓1
〓, 〓1〓, 〓0〓, 〓0〓, 〓0〓, which is the output signal of the flip-flop circuit 15g.
〓 is output to the storage unit 16.

Next, as described above, the shift register 12 inputs the signal h, synchronizes with the signals f and g, and outputs the AND gate 1.
Output to 3. The signal f is 〓1〓, but the signal g,
Since h is 〓0〓, AND gate 13 is 〓0〓
The signal generator 9 which has input the signal from the AND gate 13 outputs the signal 0 to all the OR gates 14 because its input is 0. OR gate 14 inputting 〓0〓 from signal generating section 9
As for g, the upper input is 〓0〓, but the lower input inputs the signal 〓1〓 which the flip-flop circuit 15f continues to output during the operation of the series of circuits that processed the signals e, f, and g. , its output signal is 〓1
〓 becomes. Similarly, the upper input of the OR gate 14f is 0, the lower input is 1, and the output is 1. Similarly, the upper input of the OR gate 14e is 0, and the lower input is 1. Since 〓1〓, 〓1〓 is output. Flip-flop circuits 15g to 15e are OR gates 14g to 14e.
Since the input signals from are each 〓1〓, the signal 〓
Continue to output 1〓. In the OR gate 14d, the upper input signal from the signal generator 9 is 〓0〓,
Since the lower input signal from the flip-flop circuit 15c is also 〓0〓, its output signal is 〓0〓, and since both the upper and lower inputs of the OR gates 14c to 14a are 〓0〓, their outputs are 〓0〓. 〓, and the flip-flop circuits 15c to 1
5a is an OR gate 14c corresponding to each input.
The signal 〓0〓 from ~14a is inputted, and 〓0〓 is continued to be output until the next signal is inputted. Therefore, the signals output from the flip-flop circuits 15g to 15a by a series of circuit operations after the shift register 12 inputs the signals f, g, and h are 1
〓,〓1〓,〓1〓,〓0〓,〓0〓,〓0〓,
0, and the output signal 1 of the flip-flop circuit 15g is output to the storage section 16.

Next, as described above, the shift register 12 inputs the signal i, 〓1〓, and outputs it to the AND gate 13 in synchronization with the signals g and h. AND gate 1 where signal i is 〓1〓 but signals g and h are 〓0〓
3 outputs 〓0〓, and the signal generator 9 which inputs the signal from the AND gate 13 outputs the signal 〓0〓 to all the OR gates 14 since the input signal is 〓0〓. The upper input of the OR gate 14g which inputs 0 from the signal generator 9 is 0, but the lower input is the output of the flip-flop circuit 15f during operation of a series of circuits that processed the signals f, g, h. Since the continuous signal 〓1〓 is input, the output signal becomes 〓1〓. Similarly, Orgate 14
For f, the upper input is 0, the lower input is 1, and the output is 1. The flip-flop circuits 15g and 15f have OR gates 14g and 1
Since the input signals from 4f are respectively 1, the signal 1 continues to be output. In the OR gate 14e, the upper input is the signal from the signal generator 9.
0〓 is input, and the lower input inputs the signal 〓0〓 that continues to be output from the flip-flop circuit 15d during the operation of the series of circuits that processed the signals f, g, and h, so the output signal is 〓0〓. It is. Similarly, for the OR gate 14d, the upper input signal from the signal generator 9 is 〓0〓, and the flip-flop circuit 15
Since the lower input signal from c is also 〓0〓, its output signal becomes 〓0〓, and the OR gate 14c~
14a also has each upper input and lower input = 0
Therefore, the respective outputs become 0, and the flip-flop circuits 15d to 15a input the signals from the OR gates 14d to 14a, and each continues to output 0 until the next signal is input. Therefore, the output signals of the flip-flop circuits 15g to 15a due to a series of circuit operations after the shift register 12 inputs the signals g, h, and i are 〓1〓, 〓
1〓,〓0〓,〓0〓,〓0〓,〓0〓,〓0〓
Then, the output signal 〓1〓 of the flip-flop circuit 15g is outputted to the storage section 16.

Next, in the same manner as described above, the shift register 12 inputs the signal j, synchronizes with the signals h and i, and outputs the AND gate 1.
Output to 3. The signal h is 〓0〓, and the signal i,
Since j is 1, the AND gate 13 is 0
Since the signal generator 9 inputs the signal from the AND gate 13 and outputs the signal 0, it outputs the signal 0 to all the OR gates 14. The OR gate 14g inputs the signal 〓0〓 from the signal generator 9,
The upper input is the signal 〓0〓, but the lower input is the signal 〓1〓, which the flip-flop circuit 15f continues to output as the signal 〓1〓 during the operation of the series of circuits that processed the signals g, h, and i. The flip-flop circuit 15g inputs the output signal <1> of the OR gate 14g and continues to output the signal <1> until the next signal input. In the OR gate 14f, the upper input receives the signal 〓0〓 from the signal generator 9, and the lower input receives the output signal of the flip-flop circuit 15e during operation of a series of circuits that processed the signals g, h, and i. 〓
Since 0〓 is input, the output signal is 〓0〓. Similarly, in the OR gate 14e, the upper input signal from the signal generator 9 is 0, and the lower input signal from the flip-flop circuit 15d is also 0, so the output signal is 0, and the OR gate 14d Since the upper and lower inputs of ~14a are also 0, the output thereof is 0.
Therefore, the output signals of the flip-flop circuits 15g to 15a resulting from a series of circuit operations after the shift register 12 inputs the signals h, i, and j continue to output the output signals of the OR gates 14g to 14a corresponding to the inputs. 〓1〓、〓0〓、〓
0〓,〓0〓,〓0〓,〓0〓,〓0〓,
This is the output signal of the flip-flop circuit 15g.
1 is output to the storage unit 16.

Next, in the same manner as described above, the shift register 12 inputs the signal k, synchronizes with the signals i and j, and outputs the AND gate 1.
Output to 3. Signals i and j are 〓1〓, but signal k is 〓0〓, so the AND gate 13 is 〓0〓.
Since the signal generator 9 outputs the signal 〓 and inputs the signal from the AND gate 13, it outputs the signal 〓0〓 to all the OR gates 14. OR gate 14 into which signal 〓0〓 is input from signal generator 9
The upper input of g is the signal from the signal generator 9〓0〓
is input, and the lower input is the operating flip-flop circuit 1 of a series of circuits that processed the signals h, i, and j.
Since the signal 〓0〓 which continues to be output from 5f is inputted, the output signal is 〓0〓. Similarly, in the OR gate 14f, the upper input signal from the signal generator 9 is
0〓, and the lower input signal from the flip-flop circuit 15d is also 〓0〓, so its output signal becomes 〓0〓, and since both the upper and lower inputs of the OR gates 14e to 14a are 〓0〓, Its output signal becomes 〓0〓. Therefore, the flip-flop circuit 1 is controlled by a series of circuit operations after the shift register 12 inputs the signals i, j, k.
The output signals of 5g to 15a are 〓0〓, 〓0〓, 〓0
〓, 〓0〓, 〓0〓, 〓0〓, 〓0〓, and the flip-flop circuit 15g outputs the signal 〓0〓.
is output to the storage section 16.

Next, the shift register 12 inputs the signal l, synchronizes it with the signals j and k, and outputs it to the AND gate 13. The signal output by the AND gate 13 is the signal k
Since is 〓0〓, it is 〓0〓. and gate 13
The output signal of the flip-flop circuits 15g to 15a in a series of circuit operations in which signals i, j, and k are processed are all 0.
Therefore, similarly to the operation after the shift register 12 synchronizes and outputs the signals i, j, and k, the outputs of the flip-flop circuits 15a to 15g are all 0.
〓 becomes.

Next, the shift register 12 inputs the signal m, synchronizes the signals k and l, and outputs them. Since the signal k is 〓0〓, the signals i, j, k
Similarly, when signal processing is performed, the output signals of the flip-flop circuits 15a to 15g all become 〓0〓.

Next, the shift register 12 inputs the signal n, synchronizes the signals l, m, and n and outputs them to the AND gate 13, and then continues the circuit operation and sequentially inputs the signals.
The circuit operation continues by inputting the signal u and synchronizing the signals s, t, and u and outputting them to the AND gate 13.
The operation of the circuit until the flip-flop circuits 15a to 15g output signals is performed by the shift register 12.
inputs the signal f, synchronizes the signals d, e, and f, and outputs them to the AND gate 13, then inputs the signals sequentially to continue the circuit operation, inputs the signal m, synchronizes the signals k, l, and m, and outputs them to the AND gate 13. By outputting to flip-flop circuit 13, a signal similar to that output by flip-flop circuits 15a to 15g is output.

As described above, after the shift register 12 inputs the signal a, the flip-flop circuits 15a to 15g output the signal by inputting the signal u.
Comparing the signals outputted by the light receiving section 2 with the signals a to u obtained by scanning the object 4 to be measured, the results are shown in FIG. 9b. In the figure, signal train A indicates that the object to be measured 4 is connected to the light receiving section 2.
are the scanned signals a to u, and the signal sequence B is the output signal from the flip-flop circuit 15g, which is a signal corrected by the correction circuit 7. signal train A,
Comparing B, the signal c that is the first measurement of the hole 6 of the object 4 in the signal string A appears two pixels later than the signal string B that is input to the storage section 16, so the signal e' in the signal string B is However, pixel missing occurs in the opposite scanning direction, so the signal measured before the signal measured for hole 6 appears is always corrected, and the signal 〓0〓 is changed to the signal 〓0〓 by the pixel missing correction. Since the correction is made to 1〓, it appears as a signal obtained by measuring the hole 6 from the signal c' of two pixels before, which is the pixel missing correction amount. Furthermore, the signal 〓1〓 obtained by measuring the hole 6 of the object to be measured 4 in the signal train A has four pixels from the signal c to the signal f, whereas the signal 〓1〓 in the signal train B has four pixels appearing from the signal c'. The six pixels up to the signal h' represent the signal 〓1〓 obtained by measuring the hole 6 of the object 4. In this way, the flip-flop circuit 15g outputs a signal that is actually measured by the light receiving section 2, corrected for the apparent hole diameter due to missing pixels. Furthermore, since the corresponding part of the scanned signals a to u exists on the opposite scanning direction side from the center of the conveyance direction of the object 4, the correction direction is determined by first measuring the hole 6 among the signals c to f. The corresponding signals c' to h' of the signal sequence B are corrected to 〓1〓 from the signal measured two pixels before the signal c, and the light receiving section 2 After actually measuring and after a series of circuit operations, the signal output from the flip-flop circuit 15g is input to the storage section 16 two steps faster than the signal outputted from the flip-flop circuit 15g.
Enter. Furthermore, signals i and j that are continuous for two pixels, which are obtained by measuring the hole 6 of the object 4 in the signal sequence A, do not appear in the corresponding signal sequence B, k' and l'.
If it is not the hole 6, for example, it is determined to be noise, and it is erased from the output signal. As the scanning progresses further and the light receiving unit 2 again outputs the signals l to n of the signal train A that measured the hole 6, the corresponding signals n' to p' of the signal train B and further signals n' to p' Signals l' and m' corresponding to the number of pixels appearing and to be corrected are also output to the storage unit 16 as 〓1〓.

As described above, the signals corrected for missing pixels by the correction circuit 7 are sequentially outputted by the flip-flop circuit 15g, and the storage section 16 sequentially stores the signals transmitted from the flip-flop circuit 15g for each width of the object to be measured 4. put. In this embodiment, the storage unit 16 stores one line of input signals, assuming that one line is a collection of dots in the width direction of the object to be measured 4, but it does not necessarily have to be one line, and more than one line can be stored. If possible, it is possible to count hole 6,
Furthermore, by using a filter or the like for the signal from the flip-flop circuit 15g in the present invention, it is also possible to perform processing on the shape of the hole. 17 is a counting section, and the counting section 17 is composed of an AND gate 18, flip-flop circuits 19a, 19b, a counter 20, and a display device 21, as shown in FIG. Therefore, the signal currently being transmitted by the flip-flop circuit 15g and the signal one line before, stored in the storage section 16, are synchronized and input to the counting section 17. At that time, the storage unit 16
Then, the signal of one line before is transmitted to the counting section 17 and its memory is erased, and at the same time, the signal currently being transmitted by the flip-flop circuit 15g is sequentially stored. In the counting section 17, when the currently transmitted signal changes from 0 to 1, the flip-flop circuit 19a generates a count pulse and adds 1 to the counter 20. Also, the currently transmitted signal is synchronized with the signal one line before, and is input to the AND gate 18, and when the output signal of the AND gate 18 changes from 1 to 0, the flip-flop circuit 19b generates a subtraction signal. A count pulse is generated and 1 is subtracted from the counter 20. By performing this operation for all lines on the object to be measured 4 and displaying it on the count display section 21, the number of holes 6 can be counted and displayed. Further, in this embodiment, the object to be counted of the object to be measured 4 allows the light from the light source 1 to reach the light receiving section 2, and the part of the object to be measured 4 that is not the object to be counted blocks the light from the light source 1. As an example, even if the object to be counted in the object to be measured 4 blocks the light from the light source 1 and the part of the object to be measured 4 that is not the object to be counted allows the light from the light source 1 to reach the light receiving part 2. good. In this case, the object to be measured increases from the center of the object in the transport direction to the end of the object, so the signal generating section 9 of the correction circuit 7 The input signal must be generated less than that signal. Furthermore, in the direction in which the signal generation section 9 generates less signal, if the object to be measured exists on the scanning direction side of the center of the object conveyance direction, a signal that measures the object in the measurement signal sequence appears. The measured signal is corrected to the signal when the measurement target is not being measured, and if the measurement target of the measurement target exists on the opposite scanning direction side of the center of the measurement target transport direction, the measurement target of the measurement signal train Starting with the last signal in which a measured signal appears consecutively, that signal is corrected to a signal that does not measure the measurement target. Furthermore, in the counting section,
When the currently scanned signal changes from 1 to 0, the flip-flop circuit 19a generates a count pulse and adds 1 to the counter 20.
Also, the signal currently being scanned and the signal one line before are synchronized and input to the AND gate 18, and when the output signal of the AND gate 18 changes from 0 to 1, the flip-flop circuit 19b subtracts the signal. A count pulse, which is a signal, is generated and the counter 20 is subtracted by 1.

Furthermore, as an example, holes 6 of arbitrary shapes on the object to be measured 4 shown in FIG. 11 will be counted based on the example. The line of the signal currently being scanned and transmitted is A, the signal from one line before is B, and the object to be measured 4
Let's try to correspond to the above. Reference numerals 10 denote holes drilled on the object 4 to be measured. As shown in FIG. 11a, when the current scanning signal advances and reaches point a, the signal changes from 0 to 1, and the flip-flop circuit 19a generates a count pulse and the counter 20 outputs 1. Add the count display section 21
Display 〓1〓 on . At this time, the signal A currently being scanned and the signal B from one line before are input to the AND gate and when they are ANDed, the result is 0 and is not counted. When the scanning progresses further and the state shown in FIG. 11b is reached, when the currently scanning signal A reaches point (b), the signal changes from 0 to 1, and the flip-flop circuit 19a outputs a count pulse. is generated, 1 is added to the counter 20, and 〓2〓 is displayed on the count display section 21. When the scanning progresses further and reaches point (c), the signal A currently being scanned and the signal B one line before are each 〓1〓, so the output signal of the AND gate 18 becomes 〓1〓, and further (d ), the output signal of the AND gate 18 becomes 0
The flip-flop circuit 19b generates a count pulse, subtracts 1 from the counter 20, and displays 1 on the count display section 21 in the same way as it displayed in the state shown in FIG. 11a. In the scanning from FIG. 11b to FIG. 11c, the same counting as in FIG. 11b is repeated, so the count display section 21
〓1〓 is displayed in the same manner as when it was displayed in the state shown in Fig. 11a. As the scanning progresses further, the state shown in FIG. 11c is reached. When the currently scanning signal A shown in FIG. In addition, the count display section 21 displays 〓2〓.
As the scanning progresses further and reaches point (f), the signal A currently being scanned and the signal B one line before are respectively 〓
1〓, which is input to the AND gate 18, the output signal of the AND gate 18 becomes 〓1〓, and when the scanning progresses further and reaches point (g), the output signal of the AND gate 18 changes from 〓1〓 to 〓0〓. Then, the flip-flop circuit 19b generates a count pulse, subtracts 1 from the counter 20, and displays the count display section 2.
1 displays 〓1〓. When the scanning progresses further and reaches point (h), the signal A currently being scanned becomes 1, the flip-flop circuit 19a generates a count pulse, adds 1 to the counter 20,
The count display section 21 displays 〓2〓. Furthermore, the 11th
Since the counting performed in FIG. 11b is repeated up to FIG. 11d, the count display section 21 displays 〓2〓 immediately before FIG. 11d. As the scanning progresses further and at point (i) in FIG. The addition count display section 21 is 〓3〓
At the same time, the signal A currently being scanned and the signal B one line before are both 〓1〓, and the output of the AND gate 18 becomes 〓1〓. When the scanning progresses further and reaches point (j), both the currently scanning signal A and the signal B one line before are 0.
〓, the output signal of the AND gate 18 changes from 〓1〓 to 〓0〓, a count pulse is generated from the flip-flop circuit 19b, 1 is subtracted from the counter 20, and the count display section 21 displays 〓2〓, and the scanning progresses further. When the point (k) is reached, the signal B one line before becomes 〓1〓, the output signal of the AND gate 18 is 〓1〓, the count display section 21 still displays 〓2〓, and When the scanning progresses and reaches point (l), both the current scanning signal A and the signal B from one line before become 0, and the output signal of the AND gate 18 changes from 1 to 0. A count pulse is generated from the flip-flop circuit 19b,
1 is subtracted from the counter 20, and the count display section 21 displays 〓1〓. Further scanning is performed, and Fig. 11e
In the state of , when the point (m) is reached, the signal A currently being scanned is 0, and the signal B one line before is 〓1
However, the output signal of the AND gate 18 is [0], and the count display section 21 still displays 〓1〓. As the scanning progresses further, at point (n), the output signal of the AND gate 18 is 0, and the count display section 21 is displaying 1, and when the hole 6 has been scanned, the counter 20 is 1 is counted,
The count display section 21 shows the number of holes 〓1〓. When the object to be measured 4 has been completely scanned by the method described above, the count display section 21 displays the total number of holes on the object to be measured 4, and the counting ends.

As described above, the correction circuit 7 in this embodiment increases or decreases the input signal and outputs the signal to the next stage, and can be applied to other measuring instruments or signal processing. Furthermore, the width of the hole 6 in the scanning direction can also be measured by counting the amount of the continuous signal 〓1〓 of the measured hole 6.

(G) Effect According to the method described above, since the width of the measuring means in the scanning direction is smaller than the width of the object to be measured in the scanning direction, the diameter of the hole becomes smaller as the distance from the center of the object in the transport direction to the end in the scanning direction increases. This eliminates the possibility of erroneous measurements due to the apparent small diameter of the object, and it is possible to count using a relatively simple method without using complicated means. It also becomes possible to measure

[Brief explanation of the drawing]

Fig. 1 shows an embodiment of the present invention, Fig. 2 shows the same parts, Fig. 3 is a view in the direction of Fig.
Figure 5 shows the measurement situation of the measurement target, Figure 6 is a diagram explaining the situation of missing pixels, Figure 7 is an illustration of the correction circuit, and Figure 8 shows the measurement signal sequence. , FIG. 9 is a comparison explanatory diagram of the measurement signal train and the correction signal train, and FIG. 10 shows the counting section, and the 11th
The figure is an explanatory diagram of the counting method. 2... Light receiving section which is a measurement means, 4... Substrate which is an object to be measured, 5... Light receiving element, 6... Hole which is a measuring object, 9... Signal generating section, 10... Correction signal outputting section, 14...OR gate serving as logical operation means, 15...Flip-flop circuit serving as signal output maintaining means, 16...memory section, 17...counting section.

Claims (1)

[Claims] 1. When the object to be measured passes, it scans one-dimensionally in a direction intersecting the direction of movement of the object to be measured, and detects the presence or absence of the object to be measured at the scanning point of the object. A measurement means that digitizes and transmits a signal, and an address signal that instructs the measurement target position of the object in a one-dimensional scanning direction of the input signal as well as the signal output from the measurement means is input, and the measurement means If the signal from is a digitized signal that detects that the measurement target is "present", the measurement target is sent to the predetermined output.
Depending on the measurement target position of the measured object in the scanning direction that intersects the traveling direction of the measured object, the digitized signal that detects that the measured object is "present" is outputted as a predetermined signal. a signal generating means having a plurality of outputs which are outputted after increasing the number of outputs;
The signal output maintaining means inputs the same signal as one of the signals output by the signal generating means that detects the measurement target as "presence" or "absence", maintains the output to the logic operation means of 1, and outputs the signal of 1. When the logical operation means inputting the signal output from the maintaining means simultaneously inputs another output signal from the signal generating means, and at least one of the signals is a signal that detects that the measurement target is "present", outputs a signal that detects the measurement target as “present” to the next signal output maintenance means, and in other cases outputs a signal that detects the measurement target as “absent” to the next signal output maintenance means, The signal output maintaining means inputting the signal output from the first logic operating means is connected to the next logic operating means so as to maintain the output of the input signal,
A measuring device characterized in that a plurality of other logic operation means and signal output maintaining means are connected in the same way in sequence, and the final signal output maintaining means comprises correction signal output means for outputting a measurement signal. 2 When the object to be measured passes, it scans one-dimensionally in the direction of movement and intersecting the object to be measured, detects the presence or absence of the object at the scanning point of the object, digitizes it, and sends a signal. A measuring means to be measured, a signal output from the measuring means is inputted, and an address signal indicating the applicable position of the object to be measured in the one-dimensional scanning direction of the input signal is inputted, and the signal from the measuring means is inputted to the measurement object. In the case of a digitized signal that is detected as "present", the measurement target is sent to the specified output as "present".
Depending on the measurement target position of the measured object in the scanning direction that intersects the traveling direction of the measured object, the digitized signal that detects that the measured object is "present" is outputted as a predetermined signal. a signal generating means having a plurality of outputs which are outputted after increasing the number of outputs;
The signal output maintaining means inputs the same signal as one of the signals output by the signal generating means that detects the measurement target as "presence" or "absence", maintains the output to the logic operation means of 1, and outputs the signal of 1. One logic operation means which inputs the signal output from the maintenance means simultaneously inputs another output signal from the signal generation means, and if at least one of the signals is a signal that detects that the measurement target is "present", A signal that detects that the measurement target is "present" is output as a signal to the next signal output maintaining means, and in other cases, a signal that detects that the measurement target is "absent" is output as a signal to the next signal output maintaining means, The signal output maintaining means inputting the signal output from one logic operating means is connected to the next logic operating means so as to output and maintain the input signal, and the other plural logic operating means and signal output maintaining means are sequentially connected in the same manner. correction signal output means, which are connected to each other, and the final signal output maintenance means outputs the measurement signal to the storage means and the counting means; and storage means, which stores the signal of the width portion of the object to be measured outputted by the correction signal output means for each scan. and a counting means for comparing and counting the signal for the width portion of the object to be measured for each scan outputted by the correction signal output means and the correction signal for the width portion of the object to be measured for the previous scan stored in the storage means. A measuring device characterized by comprising: