JPH0524592B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides an MIS memory circuit, particularly a data line potential setting circuit that shifts the potential state of a pair of data lines holding mutually different potentials from a first potential state to a second potential state. The present invention relates to an MIS memory circuit comprising:

In general, in an insulated gate transistor memory circuit (hereinafter simply referred to as an MIS memory circuit) in which writing and reading are performed via a pair of common data lines, the potential state of the common data line (first It is necessary to shift the potential state (potential state) to the potential state (second potential state) required at the time of reading, and a data line potential setting circuit is used to shorten the time.

MIS using such a data line potential setting circuit
The memory circuit will be explained with reference to FIG.

In the same figure, 1 is a memory cell MS ₁₁ ~ _{MS no}
This is a memory matrix in which data is arranged in m rows and n columns. Reference numeral 2 denotes a row selection address decoder which selects each row of the memory matrix using row address signals W ₁ to W _n . 3 is a column gate means for connecting a pair of digital lines D ₀₁ , D ₁₁ to _{D 0o} , D _1o arranged in each column to a common common data line CD ₀ to CD ₁ ; It has a pair of column gate switching elements Q ₅ , Q ₆ to _{Q 5} ′, Q ₆ ′. 4 is the pair of column gate switching elements Q ₅ ,
This is a column selection address decoder that selects _Q6 to _Q5 ' and _Q6 ' using column gate signals _CL1 to _CLO . Reference numeral 5 denotes a load means for supplying current to a pair of digital lines D ₀₁ , D ₁₁ to D _0o , D _1o in each column, and each column consists of a pair of MISFETs _{Q 7} , Q ₈ to Q ₇ ′, Q ₈ ′. . 6 is
This write circuit is controlled by the CSX signal, WED signal, and WE' signal, and amplifies write data from the input/output terminal I/O and transmits the amplified data to the pair of common data lines. Reference numeral 7 denotes a readout circuit which is controlled by the CSX signal, WE signal, and ``signal, and amplifies the data read out to the common data lines CD ₀ and CD ₁ and transmits it to the input/output terminal I/O.
8 is a data line potential setting circuit connected to a pair of common data lines, MISFETQ ₉ ', Q ₉ is connected between common data line CD ₀ and bias source Vcc, and common data line CD ₁ and bias source Vcc are connected. The circuit has a circuit configuration in which MISFETQ ₁₀ ' and Q ₁₀ are connected to the source Vcc, and the MISFETQ ₉ and Q ₁₀ are controlled by the '' signal.
MS ₁₁ , cross-connected as shown in MS _no .
MISFETQ ₃ , Q ₄ , Q ₃ ', Q ₄ ', their cross connection points A, B, A', B' and digital lines D ₀₁ , D ₁₁ , D _0o ,
D _1o and the row address signal W ₁ ~
MISFETQ ₁ , Q ₂ , Q ₁ ′, Q ₂ ′ to which W _n is applied,
Bias source Vcc and the cross-connection points A, B, A',
The load elements R ₁ , R ₂ , R ₁ ′,
R ₂ ′, and a high level (hereinafter referred to as H level) at one cross-connection point.
It has a function of statically storing and holding data so that a low level (hereinafter referred to as L level) is generated at the other cross-connection point. In addition, the write circuit 6 includes MISFETQ ₄₂ , Q ₄₃ ,
A bush pull amplification stage consisting of _Q49 , _Q50 , _Q56 ,
MISFETQ ₄₂ ' connected between the bush pull amplification means and the pair of common data lines CD ₀ and CD ₁ ;
A transmission means consisting of Q ₄₉ ′ and MISFETQ ₄₄ , Q ₄₅ ,
A first inverter waveform shaping means consisting of _Q51 , _Q52 , _Q57 , a second inverter waveform shaping means consisting of _MISFETQ46 , _Q47 , _Q53 , _Q54 , _Q56 ,
It is composed of input buffer means consisting of MISFETQ ₄₈ , Q ₅₅ , and Q ₅₉ , the transmission means is connected to the WE' signal, the push-pull amplification means is connected to the WED signal,
Furthermore, by controlling the first and second inverter waveform shaping means and input buffer means using CSX signals, the write data from the input/output terminals is amplified and applied to the pair of common data lines CD ₀ and CD ₁ . .

Note that the level of the write data transmitted to the common data line is as follows when the bias source Vcc is 4.5V.
One is 3.8V “H” level, the other is 0.3V
This is the “L” level. Also, the MISFETQ ₄₄
~Q ₄₃ is a deflation type, and the others are enhancement types.

Further _, as shown in _{FIG .} 3, the readout circuit 7 has _a first
a first differential amplifying means drive control means consisting of MISFETQ ₆₂ , Q ₆₃ , Q ₇₆ , and a first differential amplifying means driving control means consisting of MISFETQ ₆₄ , Q ₆₅ , Q ₇₇ , Q ₇₅ , Q ₇₉ , Q ₈₀ ; 2 differential amplification means and MISFETQ ₆₆ ,
A second differential amplification drive level control means consisting of Q ₆₇ , Q ₈₁ and MISFETQ ₆₂ , Q ₆₄ , Q ₆₈ ,
A first push-pull amplification means consisting of _Q83 , _Q85, and a second push-pull amplification means consisting of _MISFETQ86 , _Q70 , _Q87 , _Q71 .
Push-pull amplification means, MISFETQ ₉₀ , Q ₉₁
TTL signal level driving inverter means consisting of;
The first and _second differential amplifying means and the level control means for driving the first and _second differential amplifying means are controlled by a CSX signal. By controlling the first and second push-pull amplification means with the ``signal'' and the tri-state means with the _WE1 signal,
The data read out to the common data lines CD ₀ and CD ₁ is amplified and taken out to the input/output terminals.

Note that the optimal level of the signal applied to the first differential amplification means is, when the bias source Vcc is 4.5V,
One is 3.8V “H” level, the other is 3.5V
is at the "L" level, and the level difference is about 0.3V. Furthermore, the above MISFETs Q ₆₀ and Q ₇₁ are of the depletion type, and the other MISFETs are of the enhancement type.

In the MIS memory circuit shown in FIG. 1 having the above configuration, suppose that data is written to the memory cell MS ₁₁ and immediately thereafter data is read from the memory cell MS _no in the same chip _. How the potential state at the time of writing ₁ (first potential state) is transferred to the potential state required at the time of reading (second potential state) will be explained with reference to the timing chart in FIG.

In addition, in the same figure, signal, signal, Ai
The signals Din/Dour are applied from outside the IC chip, and the other signals are generated inside the IC chip.

At timing _t1 , the signal goes to "L" level, thereby entering the chip selection state,
An external address signal Ai is applied to the row and column selection address decoders. As a result, memory cell _MS11 is selected, and digital lines _D01 and _D11 are connected to a pair of common data lines _D0 and _D1 via column gate switching elements _Q5 and _Q6 . Also
Since MISFETQ ₁ and Q ₂ are also ON, the cross-connection points A and B are connected to the pair of digital lines D ₀₁ and D ₁₁ .

At timing _t2 , since the WE' signal is at the "L" level, the write circuit 6 in FIG. 1, 2
The inverter waveform shaping means and the input buffer means are each in operation, thereby amplifying the write data DiN applied from the input/output terminal and transmitting the amplified data to the pair of common data lines CD ₀ and CD ₁ .

Now, when DiN is set to the "H" level, the potential of the common data line _CD0 , V _eDO , becomes the "H" level ( _V1H ) of approximately 3.8V, and the potential of the common data line _CD1 , V _CD1 , becomes approximately It becomes “L” level (V _1L ) of 0.3V.
The levels of V _1H and V _1L indicate the first potential state.

The first potential states V _1H and V _1L of the pair of common data lines CD ₀ and CD ₁ are controlled by column switching means Q ₅ ,
Q ₆ and a pair of digit wires D ₀₁ , D ₁₁ and
It is also transmitted to the cross-connection points A and B of the memory cell MS ₁₁ via the MISFETs Q ₁ and Q ₂ .

Now the load means of memory cell MS ₁₁ MISFETQ ₇ ,
Since the current driving ability of Q ₈ and the load resistance elements R ₁ and R ₂ is smaller than the current driving ability of the push-pull amplification means of the write circuit 6, the levels of the cross-connection points A and B become V _IH and V _IL . Furthermore, at this point, the above-mentioned V _IH and V _IL are also accumulated in the parasitic capacitances C ₀ and C ₁ existing on the common data lines CD ₀ and CD ₁ . Note that a plurality of pairs of digit lines D ₀₁ , D ₁₁ to _{D 0o} ,
Since the common data lines CD ₀ and CD ₁ are commonly used for D _1o , their line lengths are long, and therefore the parasitic capacitances C ₀ and C ₁ are very large.

At timing _t2 , the "L" level of the WE' signal is applied to the transmission means of the write circuit 6, so the common data lines _CD0 and _CD1 are connected to the write circuit 6.
Although electrically disconnected from the capacitance
The level is maintained at the first potential state by C ₀ and C ₁ .

At this point, the load means Q ₇ , Q ₈ and the load resistance elements R ₁ , R ₂ can supply bias to the cross-connection points A and B without being restricted by the push-pull amplification means of the write circuit 6. becomes.
In addition, when the signal " becomes "H" level, the data line potential setting circuit 8 also starts operating.

Of the data line potential setting circuit 8,
Since the common data line CD ₀ of MISFETQ ₉ ′ and Q ₉ is V _IH , the potential difference between the gate and source is less than the threshold voltage (approximately 0.7V), so each is turned off.
Also, for MISFETQ ₁₀ ′, Q ₁₀ , the common data line CD ₁ is V _IL
Therefore, the potential difference between the gate and source is above the threshold voltage (approximately 0.7V), so each is turned on. Thereby, the capacitance C ₁ through MISFETQ ₁₀ ′, Q ₁₀
, and gradually raise the level of common data line CD ₁ .

On the other hand, the cross-connection point A of the memory cell MS ₁₁ operates so that the level determined by the load means Q ₇ , MISFETQ ₁ and Q ₃ becomes V _2H from the above V _IL . Further, the cross-connection point B remains at V _2H at the time of writing.

Further, since the current driving capability of the load means _{Q 7 and} Q ₈ of the memory cell MS 11 is larger than that of the data line potential setting circuit 8, the level of the common data line is set at the cross connection points A and B of the memory cell MS ₁₁ . It is fixed at the level determined by . By this, in Fig. 4
During the period indicated by T ₁ , the level of common data line CD ₁ V _CD1
is from V _1L to V _2L , and the level of common data line CD ₀ is
V _1H becomes substantially the same potential as V _2H , and the level difference is about 0.3V.

It would be possible to switch the address signal Ai to select the next memory cell MS _no when the level difference of the common data lines reaches about 0.3V, but in reality there is a slight delay and the switch is switched at timing _t5. It will be done. From timing _t4 to timing _t5 , the levels of the common data lines _CD0 and _CD1 are each held at the second potential state.

At timing _t5 , when address signal Ai switches, memory cell MS _no is selected, thereby causing common data lines _CD0 and _CD1 to be connected to a pair of data lines through column gate switching elements _Q5 ' and _Q6 '. It is connected to the digital lines D _0o and D _1o . Now, at the cross-connection point A′ of the memory cell MS _no , there is a load means Q ₇ ′,
Potential V _2H determined by MISFETQ ₁ ′, Q ₃ ′
However, B′ also has load means Q ₈ ′, MISFETQ ₂ ′,
There exists a potential V _2L determined by Q ₄ ′,
Data opposite to the data written in memory cell _MS11 is stored and held. Therefore, memory cell MS _no has the level of common data lines CD ₀ and CD ₁ .
Reverse from V _2H and V _2L to V _2L and V _2H .

At timing t ₆ , the common data lines CD ₀ ,
The potential states V _2L and V _2H necessary to read the data of memory cell MS _no to CD ₁ , that is, V _2L is 3.5V,
When V _2H reaches 3.8, the read circuit 7 amplifies the level difference of 0.3 V between the common data lines CD ₀ and CD ₁ in an optimal state and reads the data from the input/output terminal I/O.
Read D _OUT . In this case, read data D _OUT
is at "L" level. Note that at timing _t6 , the readout circuit 7 is operational because the CSX signal is at the "H" level and the _WE1 signal is at the "L" level.

The operation of the MIS memory circuit shown in FIG. 1 has been described above, and by using the data line potential setting circuit 8 in the same drawing, the write recovery time can be shortened. However, at present, there is a demand in the market to further shorten the write recovery time.
It has become necessary to satisfy the specifications.

Therefore, an object of the present invention is to provide a data line potential setting circuit that can more rapidly obtain a level difference between second potential states.

Another object of the present invention is to provide a data line potential setting circuit that can obtain a level difference between the second potential state at a position closer to the second potential state.

Furthermore, it is an object of the present invention to provide a data line potential setting circuit that does not supply current when the potential state of a pair of data lines approaches the second potential state.

Furthermore, it is an object of the present invention to provide a data line potential setting circuit that can clamp the level of a pair of data lines near the second potential state when the potential state of the pair of data lines approaches the second potential state. .

Although the basic constituent elements of the present invention are as described in the claims, the present invention will be explained in detail below with reference to Examples.

FIG. 5 shows an MIS memory circuit using the data line potential setting circuit 9 according to the present invention.
The first example except that a data line potential setting circuit 9 according to the present invention is used instead of the data line potential setting circuit 8, and a write recovery signal generating circuit 10 is added.
Its configuration is the same as the MIS circuit shown in the figure. 1st
The same numbers and signals are used for parts common to the figures. Further, since the explanation of these common parts has already been mentioned above, the explanation will be omitted here.

In FIG. 5, the readout circuit 7' has the same circuit configuration as the readout circuit 7 used in the MIS memory circuit of FIG. 1, but as will be described later, the readout circuit 7' is The readout levels "H" level and "L" level are lower values than in the conventional case. (For example, if the bias source is 4.5V, the optimal value for "H" level and "L" level is 2.8V,
It is 2.5V. ) Further, each cross-connection point of each memory cell is at the "H" level when it matches the optimum level for reading in the storage state, and the other is at the "L" level.

In FIG. 5 above, the data line potential setting circuit 9 according to the present invention is connected between the common data lines.
switching means 9' consisting of MISFETQ ₁₁ ;
Current supply means 9'' consisting of MISFETQ ₉ and Q ₁₀ connected between the bias source Vcc and each common data line,
It is composed of a clamping means 9 consisting of depletion type MISFETs _{Q 12} and Q ₁₃ and enhancement type MISFETs _{Q 14} to Q ₂₀ .

The write recovery signal generation circuit 10 includes CSA ₁ and WED shown in the timing chart of FIG.
A first write recovery signal φ _WR1 and a second write recovery signal φ _WR2 are generated by being controlled by the signal.

The switching means 9' is controlled by the first write recovery signal _φWR1 .
MISFETQ ₁₁ operates in the non-saturation region.

The current supply means 9'' is controlled by the second write recovery signal _φWR2 , and _MISFETQ9 ,
Q ₁₀ operates in the saturation region.

In the clamping means 9, MISFETQ ₁₈
is controlled by the WE signal shown in the timing chart in Figure 7, MISFETQ ₁₉ is controlled by the CSA ₂ signal, and MISFETQ ₂₀ is controlled by the bias source.
Because it is connected to Vcc, MISFETQ ₁₈ , Q ₂₀
The means consisting of converts the level of the bias source Vcc,
Apply that voltage to MISFETQ ₁₆ and Q ₁₇ .
MISFETQ ₁₃ and Q ₁₄ are each controlled by the ' signal. Therefore, MISFETQ ₁₃ , Q ₁₅ ,
The means consisting of Q ₁₇ and the means consisting of MISFETs _{Q 12} , Q ₁₄ and Q ₁₆ respectively bring the common data lines CD ₀ and CD ₁ to an intermediate level between the second potential states V _2L and V _2H .

Note that FIG. 6 shows a specific circuit diagram of the write recovery signal generation circuit 10.

In the figure, MISFETQ ₂₁ to _{Q 27} are depletion type MISFETs, and MISFETQ ₂₈ to _{Q 41} and Q ₂₉ ′ to _{Q 30} ′ are enhancement type MISFETs.
It is MISFET.

MISFETQ ₂₁ and Q ₂₈ are the first inverters,
The WED signal is applied to its input and the output is P ₁ . MISFETQ ₂₉ ′, Q ₂₂ Q ₂₆ is the second inverter, to whose input P ₁ is applied and the output is P ₂
It is.

In addition, MISFETQ ₂₉ ′ is set to ₁ , MISFETQ _{25 ′ is}
A signal P ₅ inverted at Q ₃₄ is applied.
MISFETQ ₃₀ ′, Q ₂₈ , Q ₃₀ is a third inverter, to whose input P ₂ is applied and whose output is P ₃ .

In addition, MISFETQ ₂₅ is set to ₁ for MISFETQ ₃₀ ′,
A signal P ₅ inverted at Q ₃₄ is applied.

MISFETQ ₂₄ , Q ₃₂ is the fourth inverter,
Its input receives said P ₃ signals and ₁ signal
The output of MISFETQ ₃₁ is _P4 , which is connected to the output terminal of the second write recovery signal _φWR2 .

Furthermore, _P4 receives the WED signal.
Also controlled by MISFETQ ₃₃ .

MISFETQ ₂₆ and Q ₃₅ are the first delay means,
P ₃ is applied to its input and its output is P ₀ .

MISFETQ ₃₀ and Q ₃₇ are second delay means,
MISFETQ ₃₆ has the above P ₆ , MISFETQ ₃₇ has P ₃
are applied respectively, and the output is _P7 .
Said P ₇ is also controlled by MISFETQ ₃₅ which receives the WED signal.

MISFETQ ₂₇ , Q ₃₉ is the fifth inverter,
It receives P ₇ as its input and its output is P ₈ .

_MISFETQ40 , _Q41 and capacitor CB are boost strap means, and _P8 is applied to _MISFETQ41 . In addition, a bootstrap capacitor CB is connected between the gate and source of MISFETQ ₄₀ .
P ₇ on one charge and on the other electrode
Earth level via MISFETQ ₄₁ or
Vcc is applied through _MISFETQ40 . A first write recovery signal _φWR1 is taken out from one electrode of the capacitor CB.

The operation of the write recovery signal generation circuit 10 will be briefly explained.

First, when ₁ is at the "H" level and WED is at the "H" level, _P1 is at the "L" level, _P2 is in the open state, _P3 is at the "L" level, and _P4 is at the "L" level. Therefore, the second write recovery signal is at "L" level, _P6 is at "H" level, _P7 is at "L" level, _P8 is at "H" level, and _P9 is at "H" level.
is at the "L" level, so the first write recovery signal is also at the "L" level.

Next, ₁ goes to “L” level and WED goes to “H”
When _P1 is at the "L" level, _P2 is at the "H" level, _P3 is at the "L" level, and _P4 is at the "L" level, so the second write recovery signal φ _WR2
is at "L" level. Also, P ₆ is “H” level, P ₇ is “L” level, P ₈ is “H” level, P ₉
is at the "L" level, so the first write recovery signal _φWR1 is also at the "L" level.

Furthermore, ₁ is “L” level, WED is “L”
When the level is reached, P ₁ is “H” level, P ₂
is “L” level, P ₃ is “H” level, P ₄ is “L”
However, since the WED signal is delayed by the first, second, and third inverters, the level of _P4 is initially “H” level, and the WED signal is delayed by the first, second, and third inverters.
The write recovery signal _φWR2 generates a level of about Vcc.

When the level of P ₃ becomes "H" level, the level of P ₄ becomes "L" level, so at that point, the second write recovery φ _WR2 signal changes to "L" level. That is, the second write recovery signal φ _WR2 is activated at the time when WED becomes “L” level.
will generate a one-shot "H" level.

When _P3 is still at the "L" level, _P6 is at the "H" level and _P7 is at the "H" level. P ₆ is P _7
In response _to
A current flows through the capacitor CB, and charge is supplied to the capacitor CB.

Next, when _P8 becomes completely "L" level
Since MISFETQ ₄₁ turns OFF, the level of P ₉ becomes Vcc. As a result, the capacitance CB is bootstrapped, and one electrode has a high “H” of about 2·Vcc−Vth.
level as the first write recovery signal _φWR1 .

Next, when the level of P ₃ becomes completely "H" level, P ₆ becomes "L" level and P ₇ becomes "L" level, so that the first write recovery signal φ _WR1 becomes “L” level.

Therefore, the first write recovery signal φ _WR1
will output a one-shot "H" level from the time the WED signal becomes "L" level.

The configurations of the data line potential setting circuit 9 and the write recovery signal generating circuit 10 according to the present invention in the MIS memory circuit shown in FIG. 5 have been explained above.
When using , the first potential state at the time of writing is
The operation of how quickly the second potential state necessary for reading is made will be explained with reference to the timing chart of FIG. 7.

In the MIS memory circuit shown in Fig. 5, first write the "H" level of _DiN to the memory cell _MS11 , and immediately after that write the D _OUT from the memory cell MS _no in the same chip.
Assume that the "L" level is read out.

Therefore, since the conditions are the same as those of the MIS memory circuit of FIG. 1, the explanation will be given from timing _t3 in the timing chart of FIG. 7. In Fig. 7, Signal, Signal, Ai signal, and D _IN /D _OUT each indicate a signal taken in from outside the IC chip or a signal taken out to the outside, and other signals are generated inside the IC chip. It is something that

At timing _t3 , the WE' signal goes to "L" level, so that the write circuit 6 is electrically disconnected from the common data lines _CD0 and _CD1 . However, the capacitance of common data lines CD ₀ and CD ₁
C ₀ and C ₁ have respective potential states at the time of writing, that is, V _1H and V _1L .

At this point, both the 2 and WED signals are
Since it is at the "L" level, the second write recovery signal φ _WR2 from the write recovery signal generation circuit 10 has a potential of approximately the bias source Vcc (indicated by V _WR2 in FIG. 7). A first write recovery signal φ _WR1 having a voltage of 2·Vcc−Vth (indicated by V _WR1 in FIG. 7) is generated.

Thereby, first of all, the switching means 9'
MISFETQ ₁₁ electrically connects common data lines CD ₀ and CD ₁ , so the charge of capacitor C _{0 is}
are discharged to the capacitor C1 through the capacitor _C1 , causing charge dispersion with each other. As a result, the level of the common data line CD ₀ decreases, and the level of the common data line CD ₁ increases. Note that this rise and fall are performed with almost the same characteristics.

In addition, since the first write recovery signal φ _WR1 of MISFETQ ₁₁ is 2·Vcc-Vth, approximately 8.3V, the non-saturation region shown by Z ₁ in the output voltage-output current characteristics of MISFET shown in Fig. 12. The operating resistance is extremely low.

Therefore, the fall of the level of the common data line CD ₀ and the fall of the level of the common data line CD ₁ are steep, and the common data line
CD ₀ and CD ₁ rapidly approach near the second potential state from the first potential state.

Furthermore, since the second write recovery signal φ _WR2 is applied to the current supply means 9″, the MISFETQ ₁₀
is ON, and MISFETQ ₉ is connected to the common data line CD ₀ .
It is off because it is at V _1H of 3.8V. MISFETQ ₁₀
Since charge is supplied to the capacitor C ₁ from
Common data line CD ₁ by switching means 9'
It will help you raise your level.

Therefore, the level difference in the second potential state can be obtained earlier.

Therefore, at timing _t4 , the common data lines CD ₀ and CD ₁ change from the first potential states V _1H and V _1L to near the second potential states V _2H ′ and V _2L ′, and (this second (In the potential state of , both V _2H ′ and V _2L ′ have lower values than in the conventional case.) The level difference is also about 0.3V.

At this point, it would be ideal if the first write recovery signal and the second write recovery signals φ _WR1 and φ _WR2 were set to the "L" level, respectively, but since they become "L" level with a slight delay, the timing t By ₅ , V _2L ′ is changed to V _2L ″ by the current supply means 9″,
Change V _2H ′ to V _2H ″.

From the time when timing t ₅ is reached, the clamping means 9
begins to operate substantially. That is, the clamping means 9 inverts the signal of WE'.
WE′ signal is “H” level, CSA2 signal is “H”
This is because the current driving ability is lower than that of the current supply means 9'', although it is already operating at the time when the current supply means 9'' reaches the level.

By this clamping means 9, the common data line
V _2H ″ and V _2L ″ of CD ₀ and CD ₁ are brought to states V _2H ″ and V _2L ″ that are closer to V _2H and V _2L .

That is, the clamping means 9 is connected to the common data line.
It acts to bias the levels of CD ₀ and CD ₁ to near the level V ₀ intermediate between the second potential states V _2H and V _2L and clamp them to that level.

Therefore, if the first and second write recovery signals φ _WR1 and φ _WR2 have a level difference in the second potential state,
Even if it becomes "L" level before 0.3V is obtained, that level is guaranteed by the clamping means 9,
It can even go down to 0.3V.

Memory cell MS _no is selected by switching address signal Ai at timing _T6 .

The memory cell MS _no has a potential V _2H at its cross-connection point A′ determined by the load means Q ₇ ′, MISFETQ ₁ ′, Q ₃ ′.
is the load means Q ₈ ′, MISFETQ ₂ ′,
The potential V _2L determined by Q ₄ ′ is stored in memory.

Therefore, the state is completely opposite to that of the common data lines CD ₀ and CD ₁ .

The V _2H and V _2L of the common data lines CD ₀ and CD ₁ are set to V _2H and V _2L in the memory cell MS _no , and are inverted to V _2L and V _2H .

Incidentally, since the above-mentioned V _2H and V _2L are almost equal to V _2H and V _2L , the level correction in the memory cell MS _no is faster than that in the MIS memory circuit of FIG. 1.

At timing t ₇ , the common data lines CD ₀ ,
CD ₁ as read data of memory cell MS _no .
Since V _2L and V _2H are obtained, the read circuit 7' amplifies them and outputs "L" level D _OUT as read data from the input/output terminal I/O.

In addition, in the readout circuit of the present invention, when the bias source Vcc is set to 4.5V, for example, 2.5V and 2.8V are obtained as V _2L and V _2H , respectively, so a TTL logic level output from the readout circuit can be easily obtained. .

The operation of the MIS memory circuit using the data line potential setting circuit 9 according to the present invention has been described above, and the object of the present invention can be achieved for the following reasons.

1. Switching means 9' is connected between the common data lines, and the charge of the capacitance of one common data line is discharged to the capacitance of the other common data line via the switching means 9'. By lowering and raising the line level, the difference in level between the two is brought closer. (According to the conventional circuit, the levels of both common data lines are brought close to each other by only raising the level of the other common data line.) Furthermore, the switching means 9' outputs the first write recovery signal. Since a potential of 2.Vcc-Vth is applied to the gate by _.phi.WR1 , it operates in a non-saturated state, and its operating resistance is small, so that the rise and fall described above are steep. Furthermore, since electric charge is supplied to the capacitance of the other common data line by the current means 9'', the rise of the level of the other common data line becomes faster together with that of the switching means 9'.
As a result, the levels between both common data lines approach each other faster. From the above, the level difference in the second potential state can be obtained faster than the conventional data line potential setting circuit.

2. A switching means 9' is connected between the common data lines, and the charge of the capacitance of one common data line is discharged to the capacitance of the other common data line via the switching means 9', and the switching means 9' Since it is possible to operate in a non-saturated state, the falling characteristics of one common data line and the rising characteristics of the other common data line can be made almost the same, and as a result, the level difference in the second potential state is reduced. This is obtained approximately in the vicinity of the second potential state.

Therefore, the time required to bring the memory cell into the second potential state can be shortened.

3 The switching means 9' and the current supply means 9'' do not operate because the first and second write recovery signals φ _WR1 and φ _WR2 become "L" level when the level between the common data lines approaches the second potential state. Therefore, the level of the common data line does not rise to a level higher than the second potential state.

4 After the switching means 9' and the current supply means 9'' raise the level of the common data line above the second potential state and stop the operation, the switching means 9' and the current supply means 9'' raise the level to the second potential state.
Since the clamping means 9 is provided to lower the potential level to around the potential state of the memory cell, there is no need to lower the level of the memory cell itself, and as a result, the second potential state is obtained quickly.

As another embodiment of the present invention, data line potential setting circuits shown in FIGS. 8 to 10 can be considered.

In the embodiment shown in FIGS. 8a to 8f, a data line potential setting circuit is constructed using only switching means 9' and current supply means 9''.

The data line potential setting circuit of FIG. 8a is obtained by removing the clamping means 9 from the data line potential setting circuit 9 of FIG. As a result, the second potential state can be obtained more quickly than in the conventional data line potential setting circuit shown in FIG.

The data line potential setting circuit of FIG. 8b sets the value of the bias source connected to the current supply means to a second potential state.
The MISFET threshold voltage (approximately 0.7V) when the V _2H level is at the V _2L level or an intermediate level.
It is approximately equal to the sum of Note that MISFETQ ₉ and Q ₁₀ are enhancement types.
Assuming that it is a MISFET and is operating in the saturation region, the level of the common data line will not rise above the second potential state. Therefore, it is not necessary to use the clamping means 9 in this case.

The data line potential setting circuit shown in FIG. 8c is configured to apply the first write recovery signal φ _WR1 to the switch means 9' and the current supply means 9, and MISFETQ ₉ , Q of the current supply means 9''. By operating the common data line ₁₀ in a non-saturated state, charging of one common data line is rapidly performed together with the switching means 9'.

The data line potential setting circuit shown in FIG. 8d is the bias source of the data line potential setting circuit shown in _FIG.
The level of the common data line is set to be approximately equal to the level of _V2L , or a level in between, and the level of the common data line is prevented from rising above the level of the second potential state.In this circuit, Neither the clamping means 9 nor the clamping means 9 need be used.

The data line potential setting circuit in FIG. 8e is a current means 9.
The bias source is the first or second write recovery signal φ _WR1 , φ _WR2 , and in this case as well, the same effects as in FIGS. 8 a to 8 d can be obtained.

The data line potential setting circuit shown in FIG. 8f is such that the current means 9'' is always operated.
In this case as well, the second potential state can be obtained more quickly than in the conventional data line potential setting circuit due to the action of the switching means 9'. However, in the case of this circuit, the driving ability of the current supply means needs to be smaller than that of the circuit means (for example, the write circuit 6) that brings the data line to the first potential state.

The bias sources Vcc _' and Vcc'' used in _the data line potential setting circuits shown in FIG. be able to.

The data line potential setting circuit shown in FIG. 9 includes switching means 9', current supply means 9'', and clamping means 9.
This is another embodiment in which the switching means 9' and the current supply means 9'' are the circuit shown in FIG. 8c, and is substantially equivalent to the data line potential setting circuit shown in FIG. In addition, in this kind of combination, the effects shown in Fig. 8b,
Naturally, it is possible to construct a data line potential setting circuit by adding clamping means to the circuits d and e.

The data line potential setting circuit shown in FIG. 10 is constructed of only switching means 9' and clamping means 9''. In this case, during the period T ₂ ' shown in FIG. 9'' can prevent the potential level of the data line from rising undesirably.

Note that although MISFET is used as the switching means 9', a bipolar transistor may also be used. Further, the number of elements formed between the common data lines is not limited to one, but may include a plurality of logic circuits.

The current supply means 9'' is composed of an enhancement type MISFET, but a depletion type may also be used.Furthermore, it may be a current supply means such as a bipolar transistor, a diode, a resistor, etc. other than the MISFET. It may include a plurality of elements connected between the bias source and the data line.

Further, the clamping means 9 is not limited to the one shown in FIG. 5, and various modified circuits having the same function can be considered.

[Brief explanation of drawings]

Figure 1 is a schematic diagram using the data line potential setting circuit.
MIS memory circuit diagram, Figure 2 is a write circuit diagram used in the MIS memory circuit, Figure 3 is a read circuit diagram used in the MIS memory circuit, Figure 4 is the timing of the MIS memory circuit in Figure 1. Chart diagram, FIG. 5 is a schematic MIS memory circuit diagram using the data line potential setting circuit according to the present invention, FIG. 6 is a write recovery signal generation circuit diagram, and FIG. 7 is a diagram of the write recovery signal generation circuit.
Timing chart diagrams of the MIS memory circuit, FIGS. 8a, b, c, d, e, f, FIGS. 9 and 10 are data line potential setting circuit diagrams according to other embodiments of the present invention, and FIG. 11 is the voltage conversion circuit diagram, and Figure 12 is the voltage conversion circuit diagram.
FIG. 3 is a characteristic diagram showing the output voltage (V _DS )-output current (I _DS ) characteristics of MISFET. 1...Memory matrix, 2...Row selection address decoder, 3...Column gate means, 4...
Column selection address decoder, 5... Load means, 6...
...Writing circuit, 7', 7...Reading circuit, 8
...Conventional data line potential setting circuit, 9...Data line potential setting circuit according to the present invention, 10...Write recovery signal generation circuit, 11... Potential conversion circuit.

Claims (1)

[Claims] 1. A memory matrix, a column gate means, a pair of common data lines coupled to the memory matrix via the column gate means, and an input coupled to the pair of common data lines. A differential amplifier circuit having a terminal, a write recovery pulse signal generation circuit that responds to a write control signal and forms a write recovery pulse of a predetermined pulse width at the end of a data write operation, and the pair of common data lines. It includes a switching means operated by the write recovery pulse, and applies a predetermined bias voltage to the pair of common data lines in the operating state, and changes the potential between the pair of common data lines to the high level and low level of the complementary data signal. and a potential setting circuit that forces the voltage to a level between
memory circuit. 2 The switching means includes a pair of first switching devices provided between the output of the bias voltage forming means and the pair of common data lines.
Claim 1, characterized in that the switching MISFET comprises a MISFET and a second switching MISFET provided between the pair of common data lines and operated together with the first switching MISFET.
MIS memory circuit.