JPH0526760B2 - - Google Patents
Info
- Publication number
- JPH0526760B2 JPH0526760B2 JP21288284A JP21288284A JPH0526760B2 JP H0526760 B2 JPH0526760 B2 JP H0526760B2 JP 21288284 A JP21288284 A JP 21288284A JP 21288284 A JP21288284 A JP 21288284A JP H0526760 B2 JPH0526760 B2 JP H0526760B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- temperature
- superlattice
- heat treatment
- crystal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000013078 crystal Substances 0.000 claims description 27
- 238000010438 heat treatment Methods 0.000 claims description 23
- 229910052782 aluminium Inorganic materials 0.000 claims description 12
- 238000002109 crystal growth method Methods 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 5
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 18
- 238000005424 photoluminescence Methods 0.000 description 11
- 239000012535 impurity Substances 0.000 description 8
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 7
- 238000000034 method Methods 0.000 description 7
- 229920000379 polypropylene carbonate Polymers 0.000 description 7
- 238000002300 pressure perturbation calorimetry Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 235000012431 wafers Nutrition 0.000 description 5
- 238000000407 epitaxy Methods 0.000 description 4
- 230000000704 physical effect Effects 0.000 description 4
- 238000011109 contamination Methods 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 239000010408 film Substances 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- 239000000470 constituent Substances 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 239000003779 heat-resistant material Substances 0.000 description 2
- 238000001534 heteroepitaxy Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 230000000737 periodic effect Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000001276 controlling effect Effects 0.000 description 1
- 230000002596 correlated effect Effects 0.000 description 1
- 230000000875 corresponding effect Effects 0.000 description 1
- 238000007872 degassing Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 125000005842 heteroatom Chemical group 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 230000002085 persistent effect Effects 0.000 description 1
- 238000000103 photoluminescence spectrum Methods 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
- 238000005979 thermal decomposition reaction Methods 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Landscapes
- Crystals, And After-Treatments Of Crystals (AREA)
- Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
- Recrystallisation Techniques (AREA)
Description
【発明の詳細な説明】
(産業上の利用分野)
この発明は−化合物半導体のエピタキシヤ
ル結晶成長技術に関する。この発明の方法を採用
することにより、結晶品質の向上、結晶組成の制
御あるいは結晶成長炉に対する設計自由度の向上
がなされる。DETAILED DESCRIPTION OF THE INVENTION (Industrial Field of Application) The present invention relates to a technology for epitaxial crystal growth of compound semiconductors. By employing the method of the present invention, it is possible to improve crystal quality, control crystal composition, and increase the degree of freedom in designing a crystal growth furnace.
(従来技術とその問題点)
近年、分子線エピタキシヤル成長法(MBE
法:Molecular Beam Epitaxy)や有機金属の
熱分解による気相成長法(MOCVD法:Metal
Orgenic Chemical Vapour Deposition)が薄膜
エピタキシヤル層の層厚制御に有効なところから
盛んに研究がなされている。これらの結晶成長法
の最大の特徴は数10Å以下の薄膜エピタキシーの
製作を可能にしたところにあろう。この点から、
これらの結晶成長法は超格子や量子井戸構造等の
超薄膜構造のヘテロエピタキシーやいわゆる選択
ドーピング結晶を製作する上で最も特徴を発揮す
るものである。(Prior art and its problems) In recent years, molecular beam epitaxial growth (MBE)
method: Molecular Beam Epitaxy) and organic metal thermal decomposition vapor phase growth method (MOCVD method: Metal
Orgenic Chemical Vapor Deposition) has been actively researched as it is effective in controlling the thickness of thin film epitaxial layers. The greatest feature of these crystal growth methods is that they enable the production of thin film epitaxy of several tens of angstroms or less. From this point,
These crystal growth methods are most effective in producing heteroepitaxy of ultra-thin film structures such as superlattices and quantum well structures, and so-called selectively doped crystals.
しかし、これら極薄膜のヘテロエピタキシーで
は結晶成長温度を上昇するとヘテロ界面での母体
構成元素の相互拡散が生じたり、選択ドーピング
することを意図した結晶層中からドーピング不純
物が隣接層中に拡散し、所定の構造が得られない
といつた問題が生じる。また、MBE法で特に問
題となる点であるが結晶成長温度を上昇するとエ
ピタキシー室の温度上昇等による器壁からの脱ガ
ス等が生じ、結晶の純度の低下が生じる。さらに
エピタキシー室内の構成素材は成長温度の上昇と
共に耐熱性素材に限られ、エピタキシー室系を構
成する素材の選択をきわめて限定する。 However, in heteroepitaxy of these ultrathin films, when the crystal growth temperature is increased, interdiffusion of host constituent elements occurs at the hetero interface, and doping impurities from the crystal layer intended for selective doping diffuse into adjacent layers. Problems arise when a predetermined structure cannot be obtained. Furthermore, which is a particular problem in the MBE method, when the crystal growth temperature is increased, degassing from the chamber wall occurs due to an increase in the temperature of the epitaxy chamber, resulting in a decrease in the purity of the crystal. Furthermore, as the growth temperature increases, the materials constituting the epitaxy chamber are limited to heat-resistant materials, which extremely limits the selection of materials for constituting the epitaxy chamber system.
しかるに結晶成長温度をできるだけ下げたいと
いう要求が生まれる。例えば、厚さ数10Åの
GaAs層にのみSiをドーピングし、やはり厚さ十
数ÅのアンドープAlAs層とからなる超格子構造
は混晶AlGaAs層中に見られる深い準位の生成が
ないため2次元電気ガスで動作する電界効果トラ
ンジスタの電子供給層としてきわめて期待される
ものであるが、結晶成長温度としては550℃程度
以下で行なわないと前記超格子構造はその構造固
有の強いフオトルミネツセンス(PL)強度が得
られない等の現象が観察され、結晶性等に難があ
る。すわわち、要約するならばヘテロ界面におけ
る相互拡散、選択ドーピングにおけるドーピング
不純物の拡散、あるいは残留不純物による汚染等
の防止には低温での結晶成長が望ましいが、低温
成長では結晶品質に問題が生じる場合が多い。 However, there is a demand to lower the crystal growth temperature as much as possible. For example, a film with a thickness of several tens of Å
The superlattice structure, which consists of only the GaAs layer doped with Si and an undoped AlAs layer with a thickness of several tens of angstroms, does not generate the deep levels seen in the mixed crystal AlGaAs layer, so the electric field operated by a two-dimensional electric gas Although it is highly expected to be used as an electron supply layer for effect transistors, the superlattice structure has a strong photoluminescence (PL) intensity inherent to that structure unless the crystal growth temperature is about 550°C or lower. Phenomena such as "no crystallinity" were observed, and problems such as crystallinity were observed. In other words, to summarize, crystal growth at low temperatures is desirable in order to prevent interdiffusion at heterointerfaces, diffusion of doping impurities in selective doping, and contamination by residual impurities, but low-temperature growth causes problems with crystal quality. There are many cases.
(発明の目的)
本発明の目的は周期100Å以下で少なくとも1
周期のAlyGa1-yAsとAlxGa1-xAs(x≠y、Al組
成X=0.2〜1.0)層を交互に積みかさね多層構造
を有する結晶層を含んだ半導体ウエーハ結晶成長
する場合にこの多層構造のヘテロ界面における相
互拡散等の問題を確実に防止することができ、か
つ高品質なエピタキシヤル結晶を得ることのでき
る結晶成長法を提供するにある。(Object of the invention) The object of the present invention is to provide at least one
A semiconductor wafer containing crystal layers having a multilayer structure is grown by alternately stacking periodic Al y Ga 1-y As and Al x Ga 1-x As (x≠y, Al composition X = 0.2 to 1.0) layers. It is an object of the present invention to provide a crystal growth method that can reliably prevent problems such as interdiffusion at the hetero-interface of a multilayer structure and that can obtain high-quality epitaxial crystals.
(発明の構成)
本発明の骨子は周期100Å以下で少なくとも1
周期のGaAsとAlGaAs(Al組成X=0.2〜1.0)層
を交互に積みかさね多層構造を有する結晶層を含
んだ半導体ウエーハ結晶成長する場合にまず、基
板温度として520℃以下の低温で成長すること、
しかる後、570〜630℃の温度で熱処理を行なうこ
とを特徴とする結晶成長方法にある。(Structure of the Invention) The gist of the present invention is that at least one
Semiconductor wafers containing crystal layers with a multilayer structure in which periodic GaAs and AlGaAs (Al composition ,
Thereafter, the crystal growth method is characterized in that heat treatment is performed at a temperature of 570 to 630°C.
(実施例)
以下、この発明を実施例に基づき詳細に説明す
る。(Examples) Hereinafter, the present invention will be described in detail based on Examples.
ここではSiをドーピングしたGaAs層とアンド
ープAlAs層とからなる超格子構造をエピタキシ
ヤル成長する場合の実施例について示す。 Here, an example will be described in which a superlattice structure consisting of a Si-doped GaAs layer and an undoped AlAs layer is epitaxially grown.
形成しようとする超格子の構造を含んだウエー
ハの断面図を第1図に示す。第1図で11は
GaAs基板、12はGaAs基板からの不純物汚染
等を避けるためのバツフアー層と呼ぶことにする
AlGaAs層、13は高純度GaAs層であり、14
がGaAsとAlAs極薄膜からなる超格子層である。
実施例における各層の厚みはバツフアー層である
AlGaAs層12が0.5μm、高純度GaAs層13は
1μmおよび超格子層14は0.5μmである。超格子
層14の層構造のほぼ1周期分のバンド図を概念
的に第2図に示す。第2図に示されるように超格
子層14の層構造を構成するGaAs層21の中央
部23にはSiが3x1018cm-3ドーピングしてあり、
これを挟むように作られたアンドープGaAs層2
4からなつている。この第2図に示された超格子
層14の形成が520℃以下の低温で行なわれた場
合には、Si、Te、Se等のドナーがドーピングさ
れたAlxGa1-xAs(Al組成比X≧0.2)混晶で普遍
的に観測されるDXセンターと呼ばれる深い準位
の濃度は極めて低くなり、よく知られたPPC
(Persistent Photoconductivity)と呼ばれる深
い準位に相関すると考えられる光伝導現象も殆ど
見られない。こうしたことから混晶AlGaAsでは
ドナー不純物をドーピングしても高いキヤリア濃
度を持つた結晶層が得られないのに反し、前記超
格子構造ではキヤリア濃度を容易に高めることが
できる。 FIG. 1 shows a cross-sectional view of a wafer containing the superlattice structure to be formed. 11 in Figure 1 is
The GaAs substrate, 12 will be called a buffer layer to avoid impurity contamination etc. from the GaAs substrate.
AlGaAs layer, 13 is a high purity GaAs layer, 14
is a superlattice layer made of ultrathin films of GaAs and AlAs.
The thickness of each layer in the examples is the buffer layer.
The AlGaAs layer 12 is 0.5 μm thick, and the high purity GaAs layer 13 is
1 μm and the superlattice layer 14 is 0.5 μm. A band diagram for approximately one period of the layer structure of the superlattice layer 14 is conceptually shown in FIG. As shown in FIG. 2, the central portion 23 of the GaAs layer 21 constituting the layer structure of the superlattice layer 14 is doped with 3x10 18 cm -3 of Si.
Undoped GaAs layer 2 made to sandwich this
It consists of 4. When the superlattice layer 14 shown in FIG. 2 is formed at a low temperature of 520°C or lower, Al x Ga 1-x As (Al composition (ratio
A photoconductivity phenomenon called (persistent photoconductivity), which is considered to be correlated with deep levels, is also hardly observed. For this reason, in mixed crystal AlGaAs, a crystal layer with a high carrier concentration cannot be obtained even when doped with donor impurities, whereas in the superlattice structure, the carrier concentration can be easily increased.
一方、520℃より高温での成長ではキヤリア濃
度の約1/2以上に相当するDXセンターの発生あ
るいはPPCの発生が観測にかかりはじめ、成長
温度の上昇に伴い、いずれも増加し、ドーピング
量を増してもキヤリア濃度が思つたように増加し
ない。現時点ではDXセンター、あるいはPPCの
起源については不明であるが、これら深い準位の
発生はSiドナーがAlAs層22に拡散するか、あ
るいはAlAs層22とGaAs層21との界面におけ
るAlとGaの相互拡散等、さらには両者が同時進
行することにより生じること等、いずれにしても
界面における相互拡散が関係していることは明白
である。520℃より高温で成長した超格子は以上
の説明で明らかなように第2図に示したような超
格子構造とはならずに界面での母体構成元素の相
互拡散、あるいはドナーSiの拡散または両者が起
こつていると考えられる。 On the other hand, when growing at temperatures higher than 520°C, the occurrence of DX centers or PPCs, which correspond to approximately 1/2 or more of the carrier concentration, began to be observed, and as the growth temperature rose, both increased and the amount of doping increased. Even if the carrier concentration is increased, the carrier concentration does not increase as expected. At present, the origin of the DX center or PPC is unknown, but the generation of these deep levels is due to the diffusion of Si donors into the AlAs layer 22, or the formation of Al and Ga at the interface between the AlAs layer 22 and GaAs layer 21. In any case, it is clear that mutual diffusion at the interface is involved, such as mutual diffusion, or even the simultaneous progress of both. As is clear from the above explanation, the superlattice grown at a temperature higher than 520°C does not have the superlattice structure shown in Figure 2, but rather due to interdiffusion of host constituent elements at the interface, diffusion of donor Si, or It is likely that both are occurring.
従つて、第2図で示したような超格子構造の製
作には520℃以下の低温での結晶成長を行なう必
要がある。ところがこうした低温でエピタキシヤ
ル成長した場合には必ずしも良好な結晶性が得ら
れない。例えば超格子構造に固有と考えられる強
いPL強度は得られず、またPL強度の経時変化が
しばしば観測され、結晶の安定性に問題があるこ
とがわかる。また、超格子構造ではキヤリア濃度
を容易に高めるこができると前記したがこれも十
分ではない。 Therefore, in order to produce a superlattice structure as shown in FIG. 2, it is necessary to perform crystal growth at a low temperature of 520° C. or lower. However, when epitaxial growth is performed at such low temperatures, good crystallinity is not necessarily obtained. For example, strong PL intensity, which is considered to be unique to a superlattice structure, cannot be obtained, and changes in PL intensity over time are often observed, indicating a problem with crystal stability. Moreover, although it was mentioned above that the carrier concentration can be easily increased with a superlattice structure, this is also not sufficient.
すなわち、第3図および第4図には520℃以下
の基板温度でMBE成長した第1図の構造を持つ
たエピタキシヤルウエーハをH2中で30分間、各
種温度で熱処理した場合における超格子層の物性
の変化を示した。第3図はフオトルミネツセンス
(PL)スペクトルを示したものであるが650℃以
上の熱処理を受けた場合にはPLピーク波長が変
化しており、かつPL強度が著しく減少している
ことがわかる。800℃での熱処理試料でのPL強度
は同様なSiドーピングを行なつて作られた混晶
AlGaAsと同等となつており、650℃以上の熱処
理ではAlとGaの相互拡散が進行することは明瞭
である。 That is, FIGS. 3 and 4 show the superlattice layers obtained when epitaxial wafers having the structure shown in FIG. 1 grown by MBE at a substrate temperature of 520°C or less were heat-treated in H 2 for 30 minutes at various temperatures. showed changes in physical properties. Figure 3 shows the photoluminescence (PL) spectrum, and it can be seen that the PL peak wavelength changes and the PL intensity decreases significantly when heat treated at 650°C or higher. Recognize. The PL intensity of the heat-treated sample at 800°C is similar to that of a mixed crystal made with similar Si doping.
It is equivalent to AlGaAs, and it is clear that interdiffusion of Al and Ga progresses with heat treatment at 650°C or higher.
さらに、第3図では600℃以下の熱処理によつ
ては熱処理温度の上昇に伴うPL強度の増加があ
ることは注目に値する。第4図はキヤリア濃度、
DXセンター濃度(a図)、および77Kで測定した
PPC濃度(nPPC 77K)および77Kおよび300Kで測定し
たキヤリア濃度、それぞれn77K、およびn300K(b
図)の熱処理温度T依存性を示したものである
が、熱処理温度Tの上昇に伴うキヤリア濃度の増
加が約650℃以下でも見られる。但し、第4図b
でそれぞれのキヤリア濃度は添加Siの量(CSi)
で規格化してある。このように650℃以下の低温
でもDXセンター濃度およびPPC濃度共に増加し
てはいるが、この量はキヤリア濃度の1/10以下で
あり実用上問題とはならない。第4図における
650℃未満の低温熱処理でのPPC濃度の僅かな減
少およびキヤリア濃度の増加は第3図で示した低
温熱処理におけるPL強度の増加傾向によく対応
するものである。以上の結果から、こうした低温
熱処理により、結晶性の改善あるいは不活性であ
るドーピング不純物の活性化が生じていることを
示している。 Furthermore, it is worth noting that in FIG. 3, when heat treatment is performed at 600°C or lower, the PL intensity increases as the heat treatment temperature increases. Figure 4 shows carrier concentration,
DX center concentration (figure a), and measured at 77K
PPC concentration (n PPC 77K ) and carrier concentration measured at 77K and 300K, respectively n 77K and n 300K (b
Figure) shows the dependence on heat treatment temperature T, and as the heat treatment temperature T rises, the carrier concentration increases even below about 650°C. However, Fig. 4b
Each carrier concentration is the amount of added Si (C Si )
It has been standardized. Although both the DX center concentration and the PPC concentration increase even at low temperatures below 650°C, this amount is less than 1/10 of the carrier concentration and does not pose a practical problem. In Figure 4
The slight decrease in PPC concentration and increase in carrier concentration during low-temperature heat treatment below 650°C correspond well to the increasing trend of PL intensity during low-temperature heat treatment shown in FIG. The above results indicate that such low-temperature heat treatment improves crystallinity or activates inactive doping impurities.
さらに、詳細な熱処理温度の依存性を検討した
結果によれば熱処理温度の上限としては約630℃
付近にあり、熱処理が有効に働く熱処理温度の下
限は570℃である。もちろん、熱処理時間を増加
するならば570℃以下でも結晶性改善の効果が見
られることは当然の結果である。また、上限の温
度としても700℃程度の10秒間程度の瞬間熱処理
では超格子構造の物性を大きく変化することはな
い。しかし、通常の熱処理時間として考えられる
30分程度では約570℃から630℃の範囲の温度で熱
処理すれば超格子構造の物性を損なうことなく、
しかも結晶性の改善を計ることができる。 Furthermore, according to the results of a detailed study of heat treatment temperature dependence, the upper limit of heat treatment temperature is approximately 630℃.
The lower limit of the heat treatment temperature at which heat treatment is effective is 570°C. Of course, if the heat treatment time is increased, it is natural that the effect of crystallinity improvement can be seen even below 570°C. Furthermore, instantaneous heat treatment at an upper limit temperature of about 700° C. for about 10 seconds does not significantly change the physical properties of the superlattice structure. However, it can be considered as normal heat treatment time
Heat treatment at a temperature in the range of approximately 570°C to 630°C for about 30 minutes will not damage the physical properties of the superlattice structure.
Furthermore, it is possible to improve crystallinity.
以上に述べた結果をまとめるならば、周期100
Å以下で少なくとも1周期のAlyGa1-yAsとAlx
Ga1-xAs(x≠y、Al組成X=0.2〜1.0)層を交互
に積みかさね多層構造すなわち超格子構造を有す
る結晶層を含んだ半導体ウエーハ結晶成長する場
合に超格子構造の製作には520℃以下の温度で結
晶成長を行ない、後に570〜630℃で熱処理を行な
うという方法をとることにより、優れた物性を示
す超格子構造が再現性良く得られることを示し
た。 To summarize the results mentioned above, the period 100
Al y Ga 1-y As and Al x with at least one period less than Å
Ga 1-x As (x≠y, Al composition showed that a superlattice structure with excellent physical properties could be obtained with good reproducibility by growing crystals at temperatures below 520°C and then heat-treating them at 570-630°C.
本発明は100Å以下の周期を持つた超格子に効
果が顕著であり、これ以上の周期を持つた超格子
を作る場合に本発明のごとく、低温成長という手
段を用いる必要があまりない。しかし、こうした
100Å以上の長周期の超格子を作成したり、たと
え周期は長くとも超格子層を構成する一方の材料
層が数10Åといつた100Å以下の場合には本発明
が有効であることはいうまでもない。 The present invention has a remarkable effect on superlattices with a period of 100 Å or less, and when creating a superlattice with a period of more than 100 Å, it is not necessary to use low-temperature growth as in the present invention. However, these
Needless to say, the present invention is effective when creating a superlattice with a long period of 100 Å or more, or even if the period is long, when one material layer constituting the superlattice layer is several tens of Å or less than 100 Å. Nor.
なお、実施例ではGaAsとAlAsからなる超格子
層の例について述べたが、本発明は一般にAly
Ga1-yAsとAlxGa1-xAs(x≠y、0.2≦x≦1.0)
からなる超格子層にも有効である。また他の材料
の組み合わせによる超格子層に対しても材料に応
じて成長温度および後の熱処理温度が異なるもの
の本発明の低温成長後にそれよりも高い温度で熱
処理する方法が適用され有効である。 In addition, in the embodiment, an example of a superlattice layer made of GaAs and AlAs was described, but the present invention generally relates to a superlattice layer made of GaAs and AlAs.
Ga 1-y As and Al x Ga 1-x As (x≠y, 0.2≦x≦1.0)
It is also effective for superlattice layers consisting of Furthermore, although the growth temperature and subsequent heat treatment temperature differ depending on the material, the method of the present invention of heat treatment at a higher temperature after low-temperature growth can be applied to superlattice layers made of other combinations of materials, and is effective.
(発明の効果)
この発明を適用することにより、周期100Å以
下で少なくとも1周期のAlyGa1-yAsとAlxGa1-x
As(x≠y、Al組成X=0.2〜1.0)層を交互に積
みかさね多層構造を有する結晶層、すなわち超格
子層を再現性良く製作することができる。すなわ
ち、(1) 超格子層を製作する場合に問題となつて
いたAlyGa1-yAsとAlxGa1-xAs(Al組成X=0.2〜
1.0)層の界面における相互拡散にもとづく構造
の乱れが防止される。しかも(2) 相互拡散の問題
を防止するために低温成長法が取られるが、この
場合の低い結晶品質の問題をも回避されることが
できる。さらに(3) 超格子層を製作する場合には
低温成長ができるために結晶成長時の汚染が少な
く、かつ成長装置内の耐熱材料等に対する制約が
解かれるため成長装置の設計自由度が増す。(Effect of the invention) By applying this invention, at least one period of Al y Ga 1-y As and Al x Ga 1-x with a period of 100 Å or less
A crystal layer having a multilayer structure, that is, a superlattice layer, can be manufactured with good reproducibility by stacking layers of As (x≠y, Al composition X=0.2 to 1.0) alternately. That is, (1) Al y Ga 1-y As and Al x Ga 1-x As (Al composition X = 0.2 ~
1.0) Structural disturbances due to interdiffusion at layer interfaces are prevented. Moreover, (2) a low-temperature growth method is taken to prevent the problem of interdiffusion, but the problem of low crystal quality in this case can also be avoided. Furthermore, (3) when producing a superlattice layer, low-temperature growth is possible, so there is less contamination during crystal growth, and restrictions on heat-resistant materials, etc. in the growth apparatus are removed, increasing the degree of freedom in designing the growth apparatus.
第1図は本発明の効果を示した実験に用いた超
格子層を含むウエーハの断面構造をしめす模式
図、第2図は第1図中の超格子層のほぼ1周期に
相当する模式的バンド図、第3図は熱処理前後で
のフオトルミネツセンススペクトルを示すグラ
フ、第4図aは超格子層の正味イオン化不純物濃
度とDXセンサー濃度の熱処理温度T依存性を示
すグラフ、第4図bは添加Si濃度(CSi)で規格
化したキヤリア濃度とPPC濃度の熱処理温度T
依存性を表わす図。
11;GaAs基板、、12;バツフアーAlGaAs
層、13;高純度GaAs層、14;超格子層、2
1;超格子層を形成するGaAs、22;超格子層
を形成するAlAs、23;超格子層を形成する
GaAsのうちSiが添加された領域、24;超格子
層を形成するGaAsのうち不純物が無添加の領
域。
Figure 1 is a schematic diagram showing the cross-sectional structure of a wafer containing a superlattice layer used in experiments demonstrating the effects of the present invention, and Figure 2 is a schematic diagram corresponding to approximately one period of the superlattice layer in Figure 1. Band diagram, Fig. 3 is a graph showing the photoluminescence spectra before and after heat treatment, Fig. 4 a is a graph showing the dependence of the net ionized impurity concentration of the superlattice layer and the DX sensor concentration on the heat treatment temperature T, Fig. 4 b is the heat treatment temperature T for the carrier concentration and PPC concentration normalized by the added Si concentration (C Si )
A diagram showing dependence. 11; GaAs substrate, 12; buffer AlGaAs
Layer 13; High purity GaAs layer 14; Superlattice layer 2
1; GaAs forming a superlattice layer, 22; AlAs forming a superlattice layer, 23; forming a superlattice layer
A region of GaAs doped with Si; 24; a region of GaAs forming a superlattice layer to which no impurities are added;
Claims (1)
Ga1-yAsとAlxGa1-xAs(x≠y、Al組成X=0.2
〜1.0)層を交互に積みかさね多層構造を有する
結晶層を成長する場合にまず、基板温度として
520℃以下で成長すること、しかる後、570〜630
℃の温度で熱処理を行なうことを特徴とする結晶
成長法。1 At least one period of Al y with a period of 100 Å or less
Ga 1-y As and Al x Ga 1-x As (x≠y, Al composition X=0.2
~1.0) When growing a crystal layer with a multilayer structure by stacking layers alternately, first, the substrate temperature is
Grow below 520℃, then 570~630
A crystal growth method characterized by heat treatment at a temperature of °C.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21288284A JPS6191097A (en) | 1984-10-11 | 1984-10-11 | Crystal growth |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21288284A JPS6191097A (en) | 1984-10-11 | 1984-10-11 | Crystal growth |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6191097A JPS6191097A (en) | 1986-05-09 |
| JPH0526760B2 true JPH0526760B2 (en) | 1993-04-19 |
Family
ID=16629818
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21288284A Granted JPS6191097A (en) | 1984-10-11 | 1984-10-11 | Crystal growth |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6191097A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2555885B2 (en) * | 1989-05-26 | 1996-11-20 | 日本電気株式会社 | Germanium / gallium arsenide junction manufacturing method |
| JP3082719B2 (en) * | 1997-09-03 | 2000-08-28 | 日本電気株式会社 | Method for manufacturing semiconductor device |
-
1984
- 1984-10-11 JP JP21288284A patent/JPS6191097A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6191097A (en) | 1986-05-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100424759B1 (en) | A METHOD OF GROWING AN AlN SINGLE CRYSTAL LAYER AND PRODUCING METHOD OF GROUP Ⅲ NITRIDE COMPOUND SEMICONDUCTOR DEVICE INCLUDING THEREOF | |
| CN108352306B (en) | Epitaxial substrate for semiconductor element, semiconductor element, and manufacturing method of epitaxial substrate for semiconductor element | |
| US7323764B2 (en) | Buffer structure for modifying a silicon substrate | |
| US5608229A (en) | Quantum box semiconductor device | |
| US8603898B2 (en) | Method for forming group III/V conformal layers on silicon substrates | |
| US20040108500A1 (en) | Semiconductor device having a nitride-based hetero-structure and method of manufacturing the same | |
| JPH0562452B2 (en) | ||
| US4960728A (en) | Homogenization anneal of II-VI compounds | |
| KR20010090165A (en) | Semiconductor Device with Quantum dot buffer in heterojunction structures | |
| JPH033364A (en) | Semiconductor device | |
| JPH03188619A (en) | Method for heteroepitaxially growing iii-v group compound semiconductor on different kind of substrate | |
| US4789421A (en) | Gallium arsenide superlattice crystal grown on silicon substrate and method of growing such crystal | |
| US9543392B1 (en) | Transparent group III metal nitride and method of manufacture | |
| Kim et al. | Interdiffusion problems at CdTe/InSb heterointerfaces grown by temperature gradient vapor transport deposition | |
| Foxon et al. | Arsenic-doped GaN grown by molecular beam epitaxy | |
| JPH0526760B2 (en) | ||
| KR100281939B1 (en) | Semiconductor epitaxial substrate | |
| JPS6394615A (en) | Manufacture of vertical type semiconductor super lattice | |
| JPH0458439B2 (en) | ||
| Nanishi et al. | Plasma-excited MBE—Proposal and achievements through R&D of compound semiconductor materials and devices | |
| JP2000068497A (en) | GaN-based compound semiconductor device | |
| JP4535935B2 (en) | Nitride semiconductor thin film and manufacturing method thereof | |
| US7473316B1 (en) | Method of growing nitrogenous semiconductor crystal materials | |
| JP3109149B2 (en) | Compound semiconductor crystal growth method | |
| JPH0714785A (en) | Semiconductor epitaxial substrate and method for manufacturing the same |