JPH0528507B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device having an integrated injection logic circuit (hereinafter referred to as I ² L) and a normal bipolar transistor on the same substrate. Regarding equipment.

[Conventional technology]

FIG. 3 shows a structural cross-sectional view of a conventional integrated circuit in which I ² L and bipolar transistors coexist. Part A is I ² L, and part B is a normal bipolar transistor that coexists with I ² L. That is, a P-type semiconductor substrate 1 has two N ⁺ -type first buried layers 2, and an N ^- type epitaxial layer 4 is formed thereon, and this N ^- type epitaxial layer 4 is a P-type semiconductor substrate. reach 1
It is separated into a plurality of regions by a P ⁺ type insulation isolation region 5. An N ⁺ type collar region 7 is formed to reach the N ⁺ type first buried layer 2, and a P ⁺ type injector region 8a and a P ⁺ type base region of a reverse operation NPN transistor are formed in the epitaxial layer 4 therein. 8c, and the surface of the N ⁺ type color region 7 has a reverse action.
It has an N ⁺ type emitter contact region 9a of an NPN transistor. Also, P ⁺ type base region 8c
It has an N ⁺ type collector region 9b of a reverse operation NPN transistor inside. These P ⁺ type injector region 8a, N ^- type epitaxial layer 4, P ⁺
The type base region 8c constitutes a lateral PNP transistor, and the N ^- type epitaxial layer 4, P ⁺ type base region 8c, and N ⁺ type collector region 9b constitute a vertical reverse operation.
It constitutes an NPN transistor (hereinafter abbreviated as reverse operation NPN transistor), and the collector region of the lateral PNP transistor and the base region of the reverse operation NPN transistor are common, and both elements constitute I ² L.

Further, in other regions of the epitaxial layer 4, a P ⁺ type base region 8d, an N ⁺ type collector contact region 9d, and an N ⁺ type emitter region 9c are formed. These are the N ⁺ type emitter region 9c, the P ⁺ type base region 8d, and the N ^- type epitaxial layer 4.
It constitutes an NPN transistor.

An oxide film 10 covers the surface, and through the openings provided in the oxide film 10, an injector electrode 11, an I ² L emitter electrode 12, a base electrode 13,
The collector electrode 14 and the emitter electrode 15, base electrode 16, and collector electrode 17 of a normal NPN transistor are taken out.

I ² L has many features such as a simple manufacturing process, a high degree of integration, and the ability to coexist with normal bipolar integrated circuits. However, conventional I ² L has the following drawbacks.

(1) The current amplification factor (hereinafter referred to as β _up ) of a reverse-acting NPN transistor is determined by the current amplification factor (hereinafter referred to as h _FE ) of a normal NPN transistor. In order to increase β _up , h _FE must be increased. As a result, the withstand voltage (hereinafter referred to as BV _CEO ) of a normal NPN transistor decreases.

(2) In order to secure the BV _CEO of a normal NPN transistor, the impurity concentration of the epitaxial layer is reduced, and the effective epitaxial layer thickness (hereinafter referred to as W _epi
) must be large, and as a result, the operation speed decreases due to the accumulation of holes.

The fourth measure to eliminate the above drawbacks is
I ² L with the structure shown in the figure was proposed. This structure is characterized in that the P ^- type first base region 6a, which serves as at least the internal base region of the reverse operation NPN transistor, is formed at a lower concentration and deeper than the P ⁺ type second base region 8b, which serves as the external base region. It is. Further, the injector region 8a and the second base region 8b of the reverse operation NPN transistor are formed at the same time as the base region 8d of the normal NPN transistor. This structure has the following advantages over conventional I ² L.

(1) The β _up of a reverse operation NPN transistor can be highly controlled independently of the h _FE of a normal NPN transistor.

(2) Since the first base region 6a of the reverse operation NPN transistor is formed with a low concentration, the junction capacitance can be reduced and the operating speed at low currents can be improved.

(3) Since the first base region 6a of the reverse operation NPN transistor is formed deeply, W _epi can be made small and the operation speed can be improved.

[Problem that the invention seeks to solve]

As described above, it shows superior characteristics compared to conventional I ² L, but there is a limit to further increasing the speed.
The reason for this is that low concentration reverse operation is required under the process conditions to minimize W _epi in I ² L and secure the BV _CEO of a normal NPN transistor.
The first base region of the NPN transistor is W _epi 0
This is because it cannot be formed so deep that it becomes . That is, since the first base region 6a cannot reach the buried layer 2, the accumulation of holes in the epitaxial layer directly under the first base region 6a of the reverse operation NPN transistor increases, and there is a limit to speeding up. .

[Means for solving problems]

The present invention has been improved to solve these problems, and it is an object of the present invention to provide a semiconductor device that achieves an improvement in the operating speed of I ² L without reducing the withstand voltage of a normal bipolar transistor.

The semiconductor device of the present invention includes a semiconductor substrate of one conductivity type, an epitaxial layer of another conductivity type formed on the semiconductor substrate, and a first conductivity type epitaxial layer formed on the semiconductor substrate.
an isolation region separated within the second island; a first buried layer of another conductivity type formed in a boundary region between the semiconductor substrate and the epitaxial layer within the first and second islands;
A normal bipolar transistor in which a base region and an emitter region formed in an island are overlapped, and an epitaxial layer in a second island is formed as a base region and spaced apart from each other in the lateral direction on the surface of the epitaxial layer. A lateral transistor in which a second region and a third region of one conductivity type are emitter collector regions, the epitaxial layer is an emitter region, the third region is an extrinsic base region, and the concentration is lower than that of the third region. A fourth region of one conductivity type, which is formed deeply and includes an internal base region inside at least a surface of the third region facing the second region, is defined as an internal base region, within the fourth region. a vertical transistor whose collector region is at least one fifth region of another conductivity type formed in the second island, and a second buried layer of another conductivity type formed on the first buried layer in the second island. It has a mixed layer.

〔Example〕

Hereinafter, the present invention will be explained with reference to the drawings.

FIG. 1 is a structural sectional view showing one embodiment of the present invention. First, an N ⁺ type first buried layer 2 is formed from the surface of a P ^- type substrate 1 by diffusion of, for example, Sb or As.
Next, an impurity having a larger diffusion coefficient than the impurity used to form the first buried layer 2, such as P, is ion-implanted from the surface of the first buried layer 2 in the I ² L portion to form an N-type second buried layer 3. Next, an N ^- type epitaxial layer 4 is grown, and from the surface of the epitaxial layer 4, for example,
BCl ₃ is diffused to form a P ⁺ type insulation isolation region 5;
Thereafter, ions of, for example, B are implanted into the surface of the epitaxial layer 4 in the I ² L portion to form a P ^-
A mold first base region 6a is formed. Next, for example, POCl ₃ is diffused from the surface of the epitaxial layer 4 in the I ² L portion to form an N ⁺ type collar region 7 . Furthermore, the first
The steps for the base region 6a and the color region 7 may be interchanged. Here, it is preferable that the first base region 7a and the second buried layer 3 are formed so as to be in contact with each other, but they do not necessarily have to be in contact with ^each _other . It would be good if it was at least smaller than _{the epi} . Next, for example, B is ion-implanted from the surface of the epitaxial layer 4 in the I ² L portion to form a P ⁺ -type second base region 8b with a higher concentration and shallower depth than the first base region 7a. At this time, P ⁺
A type injector region 8a and a P ⁺ type base region 8d of a normal NPN transistor are also formed at the same time.
Note that the first base region 6a is formed inside the surface _S1 of the second base region 8b that faces the injector region 8a. Next, for example, POCl ₃ is diffused from the surface of the epitaxial layer 4 to form the N ⁺ type emitter contact region 9a of the reverse operation NPN transistor, the N ⁺ type collector region 9b of the same transistor, and the normal
N ⁺ type emitter region 9c of the NPN transistor, N ⁺ type collector contact region 9 of the transistor
d at the same time. Thereafter, the oxide film 10 in predetermined contact opening areas of the injector region, the emitter, base, and collector regions of a reverse operation NPN transistor, and the emitter, base, and collector region of a normal NPN transistor is etched, and each electrode pattern 11, 12, 13 is etched. ,14,15,1
6, 17 are formed. In this manner, a semiconductor device according to an embodiment of the present invention is manufactured.

FIG. 2 is a structural sectional view showing another embodiment of the present invention. The injector area 8 is located inside the surface _S2 of the injector area 8a facing the second base area 8b.
P ^- type second injector region 6 deeper than a
A feature is that b is formed at the same time as the first base region 6a. Note that the second injector region does not need to be formed at the same time as the first base region, and may be formed, for example, at the same time as the insulating isolation region. The description of the other manufacturing steps is the same as in the case of FIG. 1, and will therefore be omitted.

〔Effect of the invention〕

According to the present invention, in I ² L, the internal base region of the vertical transistor is formed with a lower concentration and deeper than the external base region of the vertical transistor, and moreover, the internal base region of the vertical transistor is formed in the horizontal direction of the external base region of the vertical transistor. Since it is formed so that it is included inside the surface facing the emitter region of the transistor, the base width of the lateral transistor can be determined by the distance between the emitter region of the lateral transistor and the external base region of the vertical transistor. , ohmic contact can be made from the external base region to the base region of the vertical transistor, and the external base region reduces the base resistance between the emitter and base of the vertical transistor, making it effective. The drop in base-emitter voltage is suppressed, and as a result,
The number of I ² L fanouts can be increased. Furthermore, according to the present invention, since the second buried layer is further formed, W _epi becomes smaller, the accumulation of holes in the epitaxial layer directly under the first and second base regions is reduced, and the operation speed is increased. will improve. Furthermore, when the second buried layer is formed in contact with the first base region, W _epi becomes 0, which further improves the operating speed, and also increases the emitter injection efficiency of the reverse operation NPN transistor, so β _wp becomes even higher. . By forming a deeper second injector region, the lateral injection works effectively, increasing the current amplification factor α _pNp of the lateral PNP, and improving the operating speed at low current.

As before, it goes without saying that β _up of the reverse action NPN transistor can be controlled independently of h _FE of the normal NPN transistor and at a high level, and that the BV _CEO of the normal NPN transistor can be secured.

It should be noted that the present invention is not limited to the above-mentioned embodiments, and the same effect can be obtained even if the polarity is changed, for example.

[Brief explanation of the drawing]

Figure 1 shows an embodiment of the present invention, I ² L and ordinary
A cross-sectional view of the structure of an integrated circuit in which NPN transistors coexist. FIG. 2 is a cross-sectional view of a similar integrated circuit showing another embodiment of the present invention. FIG. 3 shows the coexistence of conventional I ² L and ordinary NPN transistors. FIG. 4 is a structural cross-sectional view of an integrated circuit in which a conventional improved I ² L and a normal NPN transistor coexist. DESCRIPTION OF SYMBOLS 1... P- type semiconductor substrate, 2... N ⁺ type first buried layer, 3... N type second buried layer, 4... N ^- type epitaxial layer, 5... P ⁺ type insulation isolation area, 6a
...P ^- type first base region of I ² L, 6b ... P ^- type second injector region, 7 ... N ⁺ type color region,
8a...P ⁺ type injector area, 8b... ^I2L
P ⁺ type second base region, 8c... P ⁺ type base region of I ² L, 8 d... P ⁺ type base region of a normal NPN transistor, 9a... I ² LN ⁺ type emitter contact region, 9b... ...N ⁺ type collector region of I ² L, 9c
...N ⁺ type emitter region of a normal NPN transistor, 9d...N ⁺ type collector contact region of a normal NPN transistor, 10...Oxide film, 11...
...Injector electrode pattern, 12, 13, 14
……I ² L emitter base collector electrode pattern,
15, 16, 17...Emitter-base-collector electrode pattern of a normal NPN transistor.

Claims (1)

[Claims] 1. A semiconductor substrate of one conductivity type, an epitaxial layer of another conductivity type formed on the semiconductor substrate, and a first region separating the epitaxial layer into first and second islands. a first buried layer of the other conductivity type formed in a boundary region between the semiconductor substrate and the epitaxial layer in the first and second islands;
A bipolar transistor formed within the island of
The epitaxial layer in the second island is used as a base region, and the second and third regions of one conductivity type, which are formed on the surface of the epitaxial layer and spaced apart from each other in the lateral direction, are respectively emitter collector regions. the epitaxial layer of the second island is an emitter region, the third region is an extrinsic base region, the epitaxial layer is formed at a lower concentration and deeper than the third region; The fourth region of one conductivity type formed to include an internal base region inside a surface facing the second region is an internal base region, and at least one of the fourth regions formed in the fourth region a vertical transistor whose collector region is a fifth region of another conductivity type, the semiconductor device comprising:
A semiconductor device comprising a second buried layer of the other conductivity type on the buried layer. 2. The semiconductor device according to claim 1, wherein the second buried layer is in contact with the fourth region. 3. Claims characterized in that the sixth region of the one conductivity type is formed deeper than the second region at least inside the surface of the second region that faces the third region. The semiconductor device according to item 1 or 2. 4. Claim 1, wherein the diffusion coefficient of impurities forming the second buried layer is larger than the diffusion coefficient of impurities forming the first buried layer.
The semiconductor device according to item 1, 2 or 3. 5 The impurity forming the second buried layer is As or P, and the impurity forming the first buried layer is
The semiconductor device according to claim 1, 2, 3, or 4, characterized in that the semiconductor device is made of Sb or As.