JPH0529953B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to an integrated circuit mask that determines the type, constant, and interconnection relationship of each element from mask pattern data for integrated circuit (LSI) mask pattern design verification. It relates to a design verification device.

[Technical background of the invention and its problems]

Mask pattern design for integrated circuits is an error-prone task that involves handling over tens of thousands of graphics. Therefore, when designing a mask pattern, it is necessary to verify it.

Conventionally, several methods have been considered as means for verifying mask patterns. The most commonly used method among these is the method shown in FIG.

That is, this method digitizes a design drawing of a mask pattern designed based on a logic diagram to obtain mask pattern data, and extracts a circuit consisting of elements and their interconnections from this mask pattern data. This method verifies the developed circuit using logic simulation, circuit simulation, etc. Another powerful method is
There is a method of comparing a circuit extracted in a similar manner with the circuit intended by the designer.

In either method, a circuit extraction unit that extracts a circuit from mask pattern data is important.
However, in the past, this circuit extracting section was constructed using software, and as the scale of circuits has become enormous, there was a problem in that the processing required an extremely large amount of time.

Therefore, it is conceivable to configure this circuit extracting section with a dedicated device, but in this case, there are problems such as an inability to expand when trying to handle many types of elements.

[Purpose of the invention]

The present invention has been devised in view of the above-mentioned conventional drawbacks, and its purpose is to provide an integrated circuit mask design verification device that is capable of high-speed processing and is highly expandable.

[Summary of the invention]

Integrated circuit design information is usually a mask pattern,
In other words, the data for creating a glass mask,
The data is summarized into two types: data related to the manufacturing process. Therefore, by using these two pieces of data, it is possible to reconstruct the design. This process is called circuit extraction from mask patterns, and is an important step in design verification. By the way, the information included in the mask pattern includes elements and their connections. There are many types of elements included in an integrated circuit, such as transistors, diodes, capacitors, and resistors. On the other hand, when analyzing these connections, it is possible to reduce the process to a single process of analyzing connections between terminals of elements.

Based on these points, the present invention is characterized in that a plurality of element extraction units corresponding to the types of elements and one connection analysis unit are coupled via a storage unit. Note that if the data used by the connection analysis section in the storage device section is all in the same storage format, it becomes possible to handle a plurality of types of elements.

〔Effect of the invention〕

According to the present invention, by separating the element analysis section and the connection analysis section, it becomes possible to easily add a new element analysis section when a new request occurs. Therefore, it is possible to improve expandability. Further, in all cases, only one connection analysis section is required, which is extremely economical. Moreover, as a result of separating the element extraction section and the connection analysis section, each section of the apparatus can be simplified and speeding up can be easily achieved.

[Embodiments of the invention]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, with reference to the drawings, a description will be given, in particular, of a circuit extraction section of an integrated circuit mask design verification apparatus according to an embodiment of the present invention.

As shown in FIG. 1, this circuit extraction section includes three storage device sections 1 ₁ , 1 ₂ , 1 ₃ , a plurality of element extraction sections 2 ₁ , 2 ₂ , ..., 2 _o , and an element connection analysis section. 3 and
It is composed of a control section 4 that controls these.

For example, a semiconductor memory, a magnetic disk, or the like is used for the storage device units 1 ₁ to 1 ₃ , but in order to operate at high speed, it is preferable to use a device with a short access time. In the storage unit ₁₁ , mask pattern data is stored as a set of closed figures for each mask pattern layer. Note that a closed figure is given by an ordered sequence of vertices.

The element extraction units 2 ₁ to 2 _o are provided corresponding to the types of target elements, respectively. In other words,
One element extraction section extracts one type of element. Here, first, a specific configuration example of the element extraction section 2 ₁ that extracts MOS transistors will be described.

That is, as shown in FIG. 2a, the MOS transistor consists of a diffusion region 11 and a polysilicon region 1.
It is defined as a common part of the two parts and has no contact hole or the like. In the element extraction section 2 ₁ ,
The MOS transistor defined in this way is extracted by graphic processing and is shown in Figure 2.
MOS transistor source/drain region 13,
Gate region 14, boundary portion (source/drain terminal) 15 where source/drain region 13 and gate region 14 contact, representative coordinates 16 of this boundary portion,
Extract the gate terminal 17 and the like. In addition, the electrical parameters of the device (e.g. transistor dimensions) are
Calculation is performed in a parameter extraction unit (not shown).
These results are stored in the storage unit ₁₂ .

Next, the specific configuration of this element extraction section 2 ₁ will be explained based on FIG. 3. That is, this element extracting section 2 ₁ receives the diffusion layer pattern file 21 and the polysilicon layer pattern file 22 of the memory device section 1 ₁ as input, and the polysilicon wiring layer pattern data file 23 of the memory device section 1 ₂ and the MOS transistor. gate pattern file 24,
The outputs are a boundary line segment file 25 indicating MOS transistor terminals, an element file 26 containing representative coordinate points of each element terminal and pointers to individual elements, and a diffusion wiring layer pattern data file 27.

This element extraction section 2 ₂ is roughly divided into two parts. The first half is for efficiently extracting pairs of mutually related patterns, and the second half is for recognizing MOS transistors.

The two input pattern files 21 and 22 are files in which the pattern data is sorted at the lower left point. The pattern at the lower left point is stored in each pattern data register 28, 29.
Each pattern data stored in the pattern data registers 28 and 29 is processed by a lower left point coordinate extraction circuit 30,
Only the lower left point data of the diffusion layer pattern and the polysilicon pattern are taken out by 31 and stored in registers 32 and 33.

The lower left point data stored in the registers 32 and 33 are compared by a lower left point coordinate comparator 34, and the leftmost pattern is selected. When the diffusion layer pattern is at the bottom left, the output of the bottom left point coordinate comparator 34 is “1”.
becomes.

The processing target pattern pair extraction circuits 35 and 36 are
A group of patterns related to the pattern data registers 28, 29 are extracted from each pattern buffer 37, 38. The pattern data deletion circuits 39 and 40 are
Pattern data that is no longer needed (no longer a target) is taken out from the pattern buffers 37 and 38 and output to pattern data files 23 and 27.

The common portion and boundary extraction circuits 41 and 42 extract the common portion between the polysilicon layer pattern and the diffusion layer pattern, further extract the boundary portion (corresponding to the source and drain terminals) of the common portion (corresponding to the gate pattern), and It is stored in the pattern file 24 and the boundary line segment file 25.

The representative coordinate extraction circuit 43 extracts representative coordinates as shown in FIG. Store.

The pattern addition circuits 44 and 45 take into consideration that the pattern data extracted by the non-common part extraction circuit 42 may be subject to processing again.
The pattern of the non-common portion is returned to the pattern buffers 37 and 38.

Note that 46, 47, and 48 in the figure are multiplexers for switching data as necessary.

The above is an explanation of the element extraction section ₂₁ for extracting a MOS transistor. However, when extracting a diffused resistance, the resistor main body 51 shown in FIG. 4 is extracted by a graphic processing circuit section (not shown) and the contact resistance The pattern 52 is embedded in consideration of the contact value. Here, the terminals 53 and 54 of the element can be calculated by dividing the contact resistance pattern 52 into meshes and using the finite element method or the finite difference method.

The element extraction section can be similarly configured for other types of elements. These element extraction section 2
Each data from ₁ to _2o is stored in the storage unit ₁₂ via the bus.

The storage unit ₁₂ stores extracted data from the element extraction unit, but in this case, the details of the stored data differ depending on the type of element. However, as shown in FIG. 5, this storage unit ₁₂ stores common data in a data structure consisting of the X and Y coordinates of a terminal and a pointer to an element table in which elements including the terminal are arranged. has been done. Therefore, a unified interface with the element connection analysis section can be realized. Inside the storage unit ₁₂ , the data shown in FIG. 5 is sorted by coordinate values or expressed in an appropriate tree structure, so that the next element connection analysis unit 3 can process it at high speed.

The element connection analysis section 3 extracts the connection relationship between elements by investigating the inclusion relationship between the terminal coordinates and the wiring pattern shown in FIG.

In this way, according to the present embodiment, the element extraction units 2 ₁ to 2 _o for each element and one element connection analysis unit 3
Since it connects the two using a common data format and realizes a unified interface between the two,
Only one connection analysis section 3 is required. As a result, the unique processing of each part can be performed in a distributed manner.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a circuit extraction section of an integrated circuit mask design verification apparatus according to an embodiment of the present invention, and FIG. 2 is a diagram for explaining a method for extracting MOS transistors in the circuit extraction section. , FIG. 3 is a block diagram showing the element extraction section of the MOS transistor in the circuit extraction section, FIG. 4 is a diagram for explaining the method of extracting the diffused resistance in the circuit extraction section, and FIG. 5 is the memory device section. _FIG. 6 is a flowchart for explaining the mask design verification procedure. 11... Diffusion region, 12... Polysilicon region, 13... Source/drain region, 14... Gate region, 15... Boundary portion, 17... Gate terminal, 51... Resistor body, 52... Resistor pattern ,
53, 54...terminals.

Claims (1)

[Scope of Claims] 1. In an integrated circuit mask design verification device that extracts element types and interconnection relationships between elements from mask pattern data of an integrated circuit and verifies a mask design, the mask is provided for each type of element. A plurality of element extraction units extracts corresponding elements from pattern data, a storage unit stores each element information extracted by these element extraction units, and a memory unit stores each element information from the element information stored in the storage unit. 1. An integrated circuit mask design verification device comprising: an element connection analysis section for determining connection relationships between the elements. 2. The storage unit stores information related to interconnection analysis of elements among the element information from each element extraction unit in the same data format. Integrated circuit mask design verification equipment.