JPH0531997B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a demodulator that demodulates a data modulation signal recorded multiplexed with an image signal, and is particularly applicable to an electronic still camera using a video floppy disk (hereinafter referred to as a sheet). The present invention relates to a data demodulator for a system.

BACKGROUND ART In an electronic still camera system, as shown in FIG. 7, the phases of the recorded image signal and data signal 1 are different between odd-numbered fields and even-numbered fields, and the data signal 1a in odd-numbered fields is different from the vertical synchronization signal 2. 28H (H: horizontal scanning period) from the leading edge of
The first bit starts from the point , and the first bit of the data signal 1b in the even field starts from the point 28.5·H. Also, since one bit is expressed in a period of 4.H, the start and end points of each bit coincide with the timing of the horizontal synchronizing signals 3, 3a, and 3b in either field.

FIG. 8 is a diagram showing the recording method of the above-mentioned image signal 4 and data signal 1, in which the image signal 4 is modulated by the recording process circuit 5 and the data signal 1 is combined with a carrier frequency of 13 _H ( _H : horizontal scanning frequency)
A signal modulated by a DPSK (Differential Phase Shift Keying) modulation circuit 6 is frequency-multiplexed by an adder circuit 7, and recorded on a sheet 10 via a recording amplifier circuit 8 and a recording head 9.

A configuration diagram of a demodulator that demodulates the data signal 11 from the sheet 10 multiplexed in this way is shown in FIG. 9.
As shown in the figure.

A multiplexed signal output 15 related to the image signal 14 and data signal 11 extracted from the sheet 10 through the reproduction head 12 and reproduction amplification circuit 13 is input to a band filter 16 matching the carrier frequency (13× _H ) of the data signal 11. The obtained DPSK signal 17 is input to first and second synchronous detection circuits 18 and 19. The other input terminal of the first synchronous detection circuit 18 is the oscillation output 21 of the VCO (voltage controlled oscillator) 20, and the other input terminal of the second synchronous detection circuit 19 is the oscillation output 21 of the 90 degree delay circuit 22. The delayed phase oscillation outputs 23 delayed by 90 degrees are respectively input.
first and second low-pass filters 24 to which the outputs of the respective synchronous detection circuits 18 and 19 are input, respectively;
The output of 25 is input to the third synchronous detection circuit 26, and the output thereof is input to the control terminal of the VCO 20. With such a configuration, the VCO 20 oscillates by following the frequency change regardless of the phase change of the DPSK signal 17. Also, DPSK signal 17 is delayed phase oscillation output 2
Around 0 degrees and ±180 degrees for 3, oscillation output 2
1, the phase is stable around +90 degrees and -90 degrees. Therefore, the output polarity of the second synchronous detection circuit 19 is different from that of the DPSK signal 17 with respect to the delayed phase oscillation output 23.
indicates whether it is in positive phase or in reverse phase, so if this is demodulated by the decoder circuit 27, the data signal 11
is reaped. The timing of the decoder circuit 27 is
Vertical synchronization signal 2 obtained from the reproduction process circuit 28 that demodulates the image signal 14 from the multiplexed signal output 15
9 and a horizontal synchronization signal 30.

Problems to be Solved by the Invention However, the vertical synchronization signal 29 and the horizontal synchronization signal 30
is susceptible to dropouts, noises, etc. that occur during the reproduction process, and the horizontal synchronizing signal 30, which is demodulated using a differential circuit, is particularly susceptible to these. Therefore, the conventional demodulation circuit shown in FIG.
The problem is that it is difficult to obtain.

Means for Solving the Problems The present invention uses a clock obtained by dividing the oscillation circuit output (VCO output) that oscillates following the carrier frequency of the data modulation signal (DPSK signal) to be reproduced as the demodulation clock of the demodulation circuit. Initial setting of the frequency division is performed using , and the phase thereof is between the phase of the data for the odd field and the phase of the data for the even field of the image signal. The demodulator is configured to perform this initial setting using a reproduced vertical synchronizing signal, a PG pulse indicating the rotational phase of the sheet, or a vertical synchronizing signal reproduced within a window created by the PG pulse.

Effects The present invention enables data demodulation that is more resistant to dropouts, noise, etc. than conventional systems due to the above-described configuration. Furthermore, the stability of demodulation does not change in either field.

Embodiment DPSK (Differential Phase Shift
(Keying) A block diagram of a demodulating device for a modulated data signal is shown in FIG.

The multiplexed signal output 15 related to the image signal 14 and data signal 31 extracted from the sheet 10 through the reproduction head 12 and reproduction amplifier circuit 13 is matched to the carrier frequency (13· _H , _H : horizontal scanning frequency) of the data signal 11. The DPSK signal 17 obtained by inputting it to the bandpass filter 16 is inputted to first and second synchronous detection circuits 18 and 19. The other input terminal of the first synchronous detection circuit 18 has a first frequency divided output obtained by dividing the oscillation output 33 of the VCO (voltage controlled oscillator) 32 by a 1/2 frequency divider circuit 34 operating at one edge. 35, the first frequency divided output 35 is connected to the other input terminal of the second synchronous detection circuit 19 by the 1/2 frequency dividing circuit 34
A first latch circuit 36 operates with an edge opposite to
The second frequency-divided output 37 whose phase is delayed by 90 degrees after being latched at is inputted. Outputs 40 of the first and second low-pass filters 24 and 25 to which the first and second synchronous detection outputs 38 and 39 are respectively input,
41 is input to the third synchronous detection circuit 26, and its output 42 is input to the control terminal of the VCO 32.
With this configuration, VCO32 receives DPSK signal 17.
It follows the frequency change regardless of the phase change and oscillates at twice the frequency.

Figure 2 shows the DPSK signal 17 and the first divided output 3.
5 and the second frequency-divided output 37, and the relationship between the output voltages of the first and second filter outputs 40, 41, and the third synchronous detection output 42. FIG.

The first low-pass filter output 40 in FIG.
It represents the phase difference between the DPSK signal 17 and the first frequency divided output 35. In addition, the second low-pass filter output 41
represents the phase difference between the DPSK signal 17 and the second frequency-divided output 37. In other words, it indicates whether the DPSK signal 17 is in positive phase or in negative phase. here
The first low-pass filter output 40 is subjected to third synchronous detection using the phase of the second low-pass filter output 41 so that the VCO 32 can stably oscillate even if the displacement of the DPSK signal 17 changes (data changes). A circuit 42 inverts the phase of the first low-pass filter output 40. As shown in the figure, the second low-pass filter output 41
The phase difference with the DPSK signal is from -90 degrees (270 degrees)
When the temperature is 90 degrees (-270 degrees), the third synchronous detection circuit 2
6 outputs the first low-pass filter output 40 to the VCO 32, and the second low-pass filter output 41 is set at 90 degrees (-
270 degrees) to 270 degrees (-90 degrees), the third synchronous detection circuit 26 inverts the first low-pass filter output 40 and outputs it to the VCO 32. The VCO 32 stably oscillates when the phase difference between the DPSK signal 17 and the first frequency-divided output 35 is ±90 degrees. Due to the above, VCO
32 can stably oscillate even if the phase of the DPSK signal changes.

Therefore, the second synchronous detection output 39 is transferred to the integrating circuit 43.
is input and integrated in units of data periods (4 H, H: 1 horizontal scanning period), and the integrated output 44 is formed into a shaped output 46 by a shaping circuit 45, and a latch output 48 of a second latch circuit 47. The data signal 31 is demodulated by inputting the exclusive OR output 50 of the exclusive OR circuit 49, which takes the input signal , to the shift register 51 and performing series-to-parallel conversion.

In addition, the oscillation output 33 is divided into 1/26 frequency divider circuit 52 and 1/4
The third frequency divided output 5 divided by the frequency dividing circuit 53
4 is used as a clock signal for the second latch circuit 47 and shift register 51. It is also used as a clock signal for a reset pulse generating circuit 56 that generates a reset pulse 55 for resetting the integrating circuit 43 every 4·H periods.

Here, the initial setting of the frequency division of the 1/26 frequency divider circuit 52 and the 1/4 frequency divider circuit 53 is that the vertical synchronization signal 57 is separated and outputted by the reproduction process circuit 28 that demodulates the image signal 14 from the multiplexed signal output 15. This is done by

Figure 3 is a waveform diagram showing the waveforms of each part.
The phase of the frequency divided output 54 is at the odd field.
It is set to be intermediate between the data phase of the DPSK signal 17a and the data phase of the DPSK signal 17b in an even field (details will be described later).

Therefore, when the phase of the DPSK signal 17a and the second frequency-divided output 37 during an odd number field changes as shown in the figure, the integral output 44a during an odd number field also changes as shown. Further, if the DPSK signal 17b for the even field is the same as the DPSK signal 17a for the odd field, but delayed by 0.5·H, as shown in the figure, the integral output 44b for the even field changes as shown in the figure. As is clear from the waveforms of both integral outputs 44a and 44b, the effective integration period is 3.75·H and the invalid integration period is 0.25·H, and the performance is the same regardless of whether it is an odd field or an even field.

FIG. 4 is a waveform diagram of the initial settings of the 1/26 frequency divider circuit 54 and the 1/4 frequency divider circuit 53 described above. As shown in the figure, if the leading edge of the vertical synchronizing signal 58c of the composite synchronizing signals 58a and 58b in odd or even fields is O _H , then the trailing edge of the separated vertical synchronizing signal 57 is 3.25H. A constant for sync isolation is set. Therefore, the output of the 1/26 frequency divider 52 and the output 54 of the 1/4 frequency divider 53 initialized by the vertical synchronization signal 57 change as shown in the figure.
At a predetermined timing, the second latch circuit 47, shift register 51, and reset pulse generation circuit 56 are activated.
is input.

In Figure 1, 1/26 frequency divider circuit 52 and 1/4 frequency divider circuit 5
3, the vertical synchronizing signal 57 separated and reproduced from the reproduction process circuit 28 is directly used for the initial setting, but as shown in FIG.
1, which is obtained by gating the vertical synchronization signal 57.
This can be converted to a method using the second set pulse 57a, or a method using a second set pulse 57b created from the PG signal 60 as shown in FIG.

In addition, in FIG. 1, the VCO 32 is oscillated at twice the frequency of the DPSK signal 17, and the oscillation output 33 is divided by 1/104 by the 1/26 frequency divider circuit 52 and the 1/4 frequency divider circuit 53. The third divided output 54 has a period of 4·H.
However, it is not necessary to be limited to the above method as long as the output of the oscillation circuit that oscillates in accordance with the DPSK signal 17 is frequency-divided to obtain pulses of the data period.

In addition, in FIG. 3, the phase of the third frequency division output 54 is set to be the midpoint of the data phase of the DPSK signal 17a for odd fields and the DPSK signal 17b for even fields, but there is a delay in each part. It may be set at a location other than the midpoint depending on time, etc., and is not necessarily limited to the midpoint.

Furthermore, although a rotating disc-shaped sheet is used as the recording/reproducing medium in FIG. 1, the same concept can be applied to demodulators using other recording/reproducing media by partially modifying the circuit.

Effects of the Invention As explained above, in the demodulation device according to the present invention, the demodulation clock is created by dividing the output of the oscillation circuit that oscillates following the carrier frequency of the data modulation signal. , or demodulation that is resistant to dropouts during playback.

Furthermore, since the phase of the demodulation clock is set between the respective data phases of the odd field and the even field, the stability of demodulation does not change in either field.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a demodulator according to the present invention, and FIG.
The figure is a diagram of its operating principle, Figures 3 and 4 are waveform diagrams of various parts, Figures 5 and 6 are waveform diagrams of other embodiments of the present invention, and Figure 7 is an operating principle diagram showing the modulation method. , FIG. 8 is a configuration diagram showing an example of a recording circuit, and FIG. 9 is a configuration diagram showing an example of a recording circuit.
The figure is a block diagram of a conventional demodulator. 17...DPSK signal, 32...VCO, 33...
...Oscillation output, 52...1/26 frequency divider circuit, 53...1/
4 frequency divider circuit, 54...Third frequency divider output, 31...
data signal.

Claims (1)

[Claims] 1. An image signal that constitutes one frame with two fields, an odd number field and an even number field, and the start position of the data for the vertical synchronization signal of the image signal, the odd number field is the scanning line position U, and the even number field is the scanning line position. a recording/reproducing medium on which a multiplexed signal of a data signal at position E, a data modulation signal obtained by modulating the data signal, and the image signal is recorded; a reproducing means for reproducing the image signal of the recording/reproducing medium; and the recording/reproducing medium. oscillation means that oscillates in accordance with a carrier frequency of a data modulation signal of a medium; a frequency division means that frequency divides the oscillation output of the oscillation means; and a data signal of the recording/reproducing medium using the output signal of the frequency division means. and an initial setting means for initializing the rise or fall of the output signal of the frequency dividing means to be between the scanning line position U and the scanning line position E of the data signal. Characteristic demodulator. 2. The demodulator according to claim 1, wherein the initial setting means is configured to initialize the frequency dividing means using a vertical synchronization signal obtained by synchronously separating the reproduction signal of the reproduction means. 3. The initial setting means gates a vertical synchronization signal obtained by synchronously separating the reproduction signal of the reproduction means with a gate signal using a position signal indicating the phase of rotation, etc. of the recording/reproduction medium, and uses this gate output to initialize the frequency dividing means. The demodulation device according to claim 1, characterized in that the demodulation device is configured to perform settings. 4. The demodulation device according to claim 1, wherein the initial setting means is configured to initialize the frequency dividing means using a position signal indicating the phase of rotation, etc. of the recording/reproducing medium.