JPH0532774B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to a state signal control circuit for a microcomputer.

[Prior art]

Conventionally, in microcomputers that have built-in ROM, RAM, etc., the number of program steps is limited by the built-in ROM, so it is necessary to expand and access memory externally. However, almost none of the conventional microcomputers with built-in ROM, RAM, etc. have a wait function. If there is no wait function, the external memory access time is
When the memory is slow compared to the CPU, the contents of the memory are not accepted by the CPU, the CPU is not as versatile as external memory, and can only use memory with a limited access time, and the CPU's operating speed is slowed down so that it runs faster. The drawback was that the characteristics of the CPU were not utilized.

Also, even if the CPU has a wait function,
It is controlled by an external additional circuit, and the disadvantage is that the memory cannot be expanded or accessed externally without using the additional circuit.

[Purpose of the invention]

An object of the present invention is to eliminate the above-mentioned drawbacks, and to freely select external memories with different access times without requiring any external additional circuitry when accessing an external memory added to a microcomputer. An object of the present invention is to provide a state signal control circuit for a microcomputer that can perform the following functions.

[Structure of the invention]

A state signal control circuit according to the present invention includes a state signal generation circuit having a plurality of shift registers connected in series that constitute a ring counter and sequentially generate a predetermined number of state signals, and a state signal generation circuit that generates a predetermined state signal and the next state. a flip-flop, the flip-flop comprising a wait state signal generating means for inserting a wait state signal between the flip-flop and the wait state signal to delay the generation timing of the next state signal, and the wait state signal generating means can be set and reset by a command; a first gate means for generating a first signal that takes an active level when the flip-flop is in a set state and an external memory is being accessed; a second gate means for generating a second signal that assumes an active level when a signal equivalent to the predetermined state signal from the predetermined state signal is being generated; a signal generating means that generates the wait state signal when the active level of the signal is captured in synchronization with the operation; and a signal generating means that outputs the equivalent signal when the second signal is not at the active level; a third gate means that stops outputting the equivalent signal when the signal is at an active level; and a third gate means for synthesizing the outputs of the signal generating means and the third gate means, and generating the next state signal using the combined output. and a fourth gate means for supplying the signal to the shift register.

[Explanation of Examples]

Next, embodiments of the present invention will be described using the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

The state signal generation circuit 10 is a shift register.
SF1 to SF5 and OR gate OR2 and Noah gate
NOR1 and multiple state signals T ₁ ,
Generates T ₂ , T ₃ and T _E. This state signal control circuit 10 constitutes a ring counter.

State signal control flip-flop FF1 is R
- S type (set/reset type), OR gate set by wait signal WAIT from CPU
It is reset by the signal from 3, and the AND gate A1
~A3 to control the state signal generation circuit 10.

State signals T ₁ , T ₂ , T ₃ , and _TE output from shift registers SF1 to SF5 are signals for controlling the CPU, respectively. Read signal RD, write signal
WR is a signal that becomes active "H" when the CPU accesses the memory. wait signal
WAIT is a control signal that can be programmed by the CPU. External memory access signal
EXT is a signal that becomes "L" when accessing internal memory and "H" when accessing external memory in a microcomputer with built-in ROM and RAM.

Next, the operation of this embodiment will be explained.

Figure 2 is a waveform diagram for explaining the state transition of the embodiment when accessing fast memory, and Figure 3 is a waveform diagram for explaining the state transition of the embodiment (with wait state) when accessing slow memory. FIG.

First, we will explain when the CPU accesses internal memory.

In this case, the external memory access signal EXT is always "L" and the output of the AND gate A2 is always "L", so the state signals T ₁ , T ₂ , T ₃ , T _E occurs sequentially.

Next, we will explain when the CPU accesses external memory.

When accessing external memory, external memory access signal EXT is always "H". When the memory has a fast access time, the output of the flip-flop FF1 after reset is "L", so the output of the AND gate A1 is always "L". Therefore, as in the case of internal memory access, the state signals are the state signals T ₁ , T 2 , T ₂ ,
T ₃ and T _E are generated sequentially. At this time, the memory access time is one state time.

Next, the operation for a memory whose external memory has a slow access time of one state or more will be explained with reference to FIG.

In this case, the wait signal can be programmed in advance.
Activate WAIT and flip-flop FF1
If the output of is always “H”, AND gate A1
The output is read signal RD or write signal
It becomes "H" when WR is "H". As a result, the output of shift register SF1 becomes “H” and the third
As shown in the figure, the state signals are T ₁ , T _W , T ₂ ,
T ₃ and T _E occur sequentially. That is, the state signal T _W
occurs, resulting in longer access times. At this time, the memory access time is 2-state time.

When accessing two types of external memory: memory with slow access time and memory with fast access time, use the flip-flop function in the program.
By setting the contents of FF1, more state signals T _W are generated to lengthen the access time (see Figure 3), or a reset (NOWAIT) is generated.
By doing so, the state signal T _W is not generated,
The external memory access time can be freely selected by shortening the access time. In this way, it is possible to freely select external memories with different access times in a program without slowing down the operating speed of the CPU.

〔Effect of the invention〕

As explained in detail above, according to the present invention,
Provided is a state signal control circuit for a microcomputer that can freely select external memories with different access times without requiring any external additional circuitry when an external memory is added to the microcomputer and accessed. So the effect is big.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG.
The figure is a waveform diagram for explaining the state transition of the embodiment when accessing a fast memory, and FIG. 3 is a waveform diagram for explaining the state transition of the embodiment when accessing a slow memory. 10...State signal generation circuit, A1, A2,
A3...AND gate, FF1...state signal control flip-flop, NOR1...NOR gate,
OR1, OR2, OR3...Orgate, SF1~
SF5...Shift register, T ₁ , T ₂ , T ₃ , T _E ,
T _W ...state signal.

Claims (1)

[Claims] 1. A state signal generation circuit that constitutes a ring counter and has a plurality of cascaded shift registers that sequentially generate a predetermined number of state signals, and a wait state signal between a predetermined state signal and the next state signal. In the state signal control circuit, the wait state signal generating means includes a flip-flop that can be set and reset by a command, and a flip-flop that can be set and reset by a command. a first gate means for generating a first signal that takes an active level when the state is in the state and an external memory is being accessed; second gate means for generating a second signal that takes an active level when a signal equivalent to a predetermined state signal is being generated; and synchronizing the level of the second signal with the shifting operation of the shift register. a signal generating means for generating the wait state signal when the active level of the second signal is taken in; and a signal generating means for outputting the equivalent signal when the second signal is not at the active level; a third gate means that stops outputting the equivalent signal when the signal is at an active level; and a third gate means for synthesizing the outputs of the signal generating means and the third gate means, and generating the next state signal using the combined output. and fourth gate means for supplying the signal to the shift register.