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JPH0532919B2 - - Google Patents
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JPH0532919B2 - - Google Patents

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Publication number
JPH0532919B2
JPH0532919B2 JP29912087A JP29912087A JPH0532919B2 JP H0532919 B2 JPH0532919 B2 JP H0532919B2 JP 29912087 A JP29912087 A JP 29912087A JP 29912087 A JP29912087 A JP 29912087A JP H0532919 B2 JPH0532919 B2 JP H0532919B2
Authority
JP
Japan
Prior art keywords
hole
layer
conductor
circuit pattern
insulating plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP29912087A
Other languages
Japanese (ja)
Other versions
JPH01140698A (en
Inventor
Masaki Kimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP29912087A priority Critical patent/JPH01140698A/en
Publication of JPH01140698A publication Critical patent/JPH01140698A/en
Publication of JPH0532919B2 publication Critical patent/JPH0532919B2/ja
Granted legal-status Critical Current

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  • Production Of Multi-Layered Print Wiring Board (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は多層印刷配線板の製造方法に関し、特
にブラインド・バイア・ホール(盲経由孔)を有
する高密度多層印刷配線板の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing a multilayer printed wiring board, and more particularly to a method for manufacturing a high-density multilayer printed wiring board having blind via holes.

〔従来の技術〕 従来の印刷配線板は、部品挿入用の孔は勿論、
バイア・ホール(経由孔)も貫通させて、めつき
等により孔内壁に導体層を形成させるのが一般的
である。
[Prior art] Conventional printed wiring boards have not only holes for inserting components, but also holes for inserting components.
Generally, a via hole is also passed through and a conductive layer is formed on the inner wall of the hole by plating or the like.

また、多層印刷配線板(以下多層板と称す)
は、その高多層化に伴ない、一部の内層にインナ
ーレイヤー・バイア・ホール(埋込み経由孔)を
設ける設計も採用されている。
Also, multilayer printed wiring boards (hereinafter referred to as multilayer boards)
As devices become more multi-layered, designs are also being adopted in which inner layer via holes are provided in some of the inner layers.

まず、第2図aに示すように、2枚の両面銅張
り積層板21a,21bに孔を明け、両面全面に
めつきを施して導体層24を設け、そのうちの一
面に所定の回路パターンを形成する。上述と同様
の方法でもう1枚の両面銅張り積層板21cの両
面に回路パターンを形成する。
First, as shown in FIG. 2a, holes are made in two double-sided copper-clad laminates 21a and 21b, and a conductor layer 24 is provided by plating the entire surface of both sides, and a predetermined circuit pattern is formed on one of the surfaces. Form. Circuit patterns are formed on both sides of another double-sided copper-clad laminate 21c in the same manner as described above.

次に、上述の回路パターンを形成した銅張り積
層板21a,21b,21cとプリプレグ層31
a,31bを組み合せ、加熱、加圧して一体化成
形し、多層化基板28を得る。
Next, the copper-clad laminates 21a, 21b, 21c with the above-mentioned circuit patterns formed thereon and the prepreg layer 31
a and 31b are combined and integrally molded by heating and pressurizing to obtain a multilayer substrate 28.

次に、第2図bに示すように、多層化基板28
にドリルにより貫通孔29を設ける。
Next, as shown in FIG. 2b, the multilayer substrate 28
A through hole 29 is provided with a drill.

次に、第2図cに示すように、公知の無電解め
つき及び電気めつきにより貫通孔29を含んで全
面に導体層30を設ける。
Next, as shown in FIG. 2c, a conductor layer 30 is provided on the entire surface including the through holes 29 by known electroless plating and electroplating.

次に、第2図dに示すように、公知のテンテイ
ング法により多層化基板28の最外層に所定の回
路パターンを形成し、レジスト樹脂層27を設け
てブラインド・バイア・ホール35を有する多層
印刷配線板を得ていた。
Next, as shown in FIG. 2d, a predetermined circuit pattern is formed on the outermost layer of the multilayer substrate 28 by a known tenting method, a resist resin layer 27 is provided, and the multilayer printing having blind via holes 35 is performed. I was getting a wiring board.

近年、電子機器の性能上および経済上のニーズ
から実装の高密度化の試みがなされている。
In recent years, attempts have been made to increase the packaging density of electronic devices due to performance and economical needs.

このために、IC、ISI等の電子デバイスの高集
積化、高速化が進められていることは勿論、これ
らを実装する印刷配線板についても高密度化が進
められている。
For this reason, not only are electronic devices such as ICs and ISIs becoming more highly integrated and faster, but printed wiring boards on which these devices are mounted are also becoming more dense.

このため、前述の問題解決の一つの試みとして
多層印刷配線板の製造方法に最外層と最外層の次
の層に位置する導体回路を接続するブラインド・
バイア・ホール35の穴内空間が樹脂で充填され
た製造方法がある。
For this reason, as an attempt to solve the above-mentioned problem, a method for manufacturing a multilayer printed wiring board includes a blind method for connecting conductor circuits located in the outermost layer and the layer next to the outermost layer.
There is a manufacturing method in which the inner space of the via hole 35 is filled with resin.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来の多層印刷配線板の製造方法は、
絶縁板にスルーホールを有し、かつ、予め一面の
みに導体回路パターンを形成した2つの絶縁板を
前記導体回路パターンを向い合わせに各々最外層
に配置し、その内側に予め導体回路パターンを形
成した1つ以上の絶縁板をプリプレグ層を介し積
み重ねた後に、加熱、加圧して多層化基板を形成
する時に、最外層にあるスルーホールよりプリプ
レグ層のしみ出しが生じ、その後の工程で最外層
に所定の導体回路パターンを形成するのにエツチ
ング不良を起したり、層間厚み不良が発生すると
いう欠点があつた。
The conventional method for manufacturing the multilayer printed wiring board described above is as follows:
Two insulating plates each having a through hole and a conductive circuit pattern formed only on one side are placed on the outermost layer with the conductive circuit patterns facing each other, and a conductive circuit pattern is previously formed on the inside of the two insulating plates. After stacking one or more insulating plates with prepreg layers in between, when heating and pressurizing them to form a multilayer board, the prepreg layer seeps out from the through holes in the outermost layer, and in the subsequent process, the outermost layer However, when forming a predetermined conductor circuit pattern, etching defects and interlayer thickness defects occur.

本発明の目的は導体回路パターンのエツチング
不良や層間厚み不良のない歩留りの高い多層印刷
配線板の製造方法を提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a multilayer printed wiring board with a high yield and free from defective etching of conductor circuit patterns and defective interlayer thickness.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の多層印刷配線板の製造方法は、次の工
程を有している。
The method for manufacturing a multilayer printed wiring board of the present invention includes the following steps.

(イ) 両面に銅箔が張り合わされた絶縁板に無電解
めつきと電気めつきによりスルーホールと導体
層を形成し、両面に導体回路パターンを形成す
る工程。
(a) A process in which through holes and conductor layers are formed by electroless plating and electroplating on an insulating plate with copper foil laminated on both sides, and conductor circuit patterns are formed on both sides.

(ロ) 前記絶縁板の一面の導体回路パターン面に、
熱硬化性樹脂を塗り、乾燥し、スルーホール内
を含んでレジスト樹脂層を形成する工程。
(b) On the conductive circuit pattern surface of one side of the insulating plate,
The process of applying thermosetting resin, drying it, and forming a resist resin layer including the inside of the through hole.

(ハ) 前記レジスト樹脂層を有する絶縁板の導体回
路パターンを前記レジスト樹脂層を外側にして
向い合わせに各々最外層に配置し、その内側に
予め導体回路パターンを形成した少くとも1つ
の絶縁板とプリプレグ層とを介し積み重ねた後
に、加熱、加圧して多層化基板を形成する工
程。
(c) At least one insulating plate on which the conductive circuit patterns of the insulating plates having the resist resin layer are arranged in the outermost layer facing each other with the resist resin layer on the outside, and the conductive circuit pattern is previously formed on the inside thereof. A process of stacking the laminate and prepreg layers together and then applying heat and pressure to form a multilayered board.

(ニ) 前記多層化基板の所定部分に貫通孔を設ける
工程。
(d) A step of providing a through hole in a predetermined portion of the multilayer substrate.

(ホ) 前記貫通孔を有する多層化基板の貫通孔内壁
に導体層を形成する工程。
(E) A step of forming a conductor layer on the inner wall of the through hole of the multilayer substrate having the through hole.

〔実施例〕〔Example〕

以下、本発明の実施例について図を参照して説
明する。
Embodiments of the present invention will be described below with reference to the drawings.

第1図a〜iは本発明の一実施例を説明する工
程順に示した断面である。
FIGS. 1A to 1I are cross-sectional views showing steps in order to explain an embodiment of the present invention.

第1図aに示すように、絶縁板1の表裏両面に
は、各々の導体層パターンを形成する銅箔2が設
けられている。
As shown in FIG. 1a, copper foils 2 forming respective conductor layer patterns are provided on both the front and back surfaces of the insulating plate 1.

まず、第1図bに示すように両面、銅張り積層
板に貫通孔3をドリルにより穿設し、更に、第1
図cに示すように、公知の無電解めつきと電気め
つきにより貫通孔3を含む全面に導体層4とスル
ーホール5を形成し、両面の導体層4すなわち銅
箔2を接続する。
First, as shown in Fig. 1b, through holes 3 are drilled in the copper-clad laminate on both sides, and
As shown in FIG. c, a conductor layer 4 and a through hole 5 are formed on the entire surface including the through hole 3 by known electroless plating and electroplating, and the conductor layer 4 on both surfaces, that is, the copper foil 2 is connected.

次に、第1図dに示すように、公知のテンテイ
ング法を用いて、両面に所定の回路パターン部を
光感光性ドライフイルムレジスト6で被覆した
後、現像、エツチング、剥離工程を経て第1図e
に示すように、両面に回路パターンを形成する。
Next, as shown in FIG. 1d, a predetermined circuit pattern portion is coated on both sides with a photosensitive dry film resist 6 using a well-known tenting method, and then a first resist is formed through a developing, etching, and peeling process. Diagram e
Form a circuit pattern on both sides as shown in .

次に、第1図fに示すように、最外層となる外
側となる面の導体回路パターン面の所定部分に熱
硬化樹脂を塗り、乾燥し、スルーホール内を含ん
でレジスト樹脂層7を形成して、多層化基板の最
外層となる2つの積層板を得る。
Next, as shown in FIG. 1 f, a thermosetting resin is applied to a predetermined portion of the conductor circuit pattern surface on the outermost layer, and dried to form a resist resin layer 7 including the inside of the through hole. In this way, two laminates are obtained which will become the outermost layers of the multilayered substrate.

次に、第1図gに示すように、第1図a〜fに
示した上述と同様の工法によつて、両面銅張り積
層板の両面の回路パターンを形成し、レジスト樹
脂層7でスルーホールを充填した多層化基板の最
外層の積層板1a,1bと両面に回路パターンの
みを形成した積層板1cとプリプレグ層11a,
11bを組み合せ、更に、前述の積層板1a,1
bを最外層として載置した後、加熱、加圧して一
体化成形し、多層化基板8を得る。この時第1図
fで示したスルー・ホール5は、いわゆる非貫通
のブラインド・バイア・ホール15として形成さ
れ、加熱、加圧されたプリプレグ層11a,11
bはレジスト樹脂7により外部に流れ出ることな
く成形される。
Next, as shown in FIG. 1g, circuit patterns are formed on both sides of the double-sided copper-clad laminate using the same method as described above shown in FIGS. The outermost laminated plates 1a and 1b of the multilayered board filled with holes, the laminated plate 1c with only circuit patterns formed on both sides, and the prepreg layer 11a,
11b, and further the above-mentioned laminates 1a, 1
After layer b is placed as the outermost layer, the multilayer substrate 8 is obtained by integrally molding it by heating and pressurizing it. At this time, the through hole 5 shown in FIG.
b is formed by the resist resin 7 without flowing out to the outside.

次に、第1図hに示すように、部品挿入用の穴
または、内層パターンに接続する穴をドリルによ
り穿孔し、貫通孔9を設ける。
Next, as shown in FIG. 1h, a through hole 9 is provided by drilling a hole for inserting the component or a hole connecting to the inner layer pattern.

次に、第1図iに示すように、公知の無電解め
つきにより、第1図hの貫通孔9の内壁に導体層
10を形成して所定のブラインド・バイア・ホー
ルを有する多層印刷配線板を得る。
Next, as shown in FIG. 1i, a conductor layer 10 is formed on the inner wall of the through hole 9 in FIG. 1h by known electroless plating to form a multilayer printed wiring having a predetermined blind via hole. Get a board.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、次に列挙する効
果がある。
As explained above, the present invention has the following effects.

(1) 最外層となる回路パターンを予め形成するた
めエツチング残り等の不良がなくなり、歩留り
の向上を得ることができる。
(1) Since the circuit pattern for the outermost layer is formed in advance, defects such as etching residue are eliminated, and yield can be improved.

(2) スルー・ホール内をレジスト樹脂層で充填し
たことによつて絶縁板を積層したときにしみ出
すプリプレグフローがないため、層間厚み不良
がなくなり、歩留り向上を得ることができる。
(2) By filling the through holes with a resist resin layer, there is no prepreg flow that seeps out when insulating plates are laminated, which eliminates interlayer thickness defects and improves yield.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図a〜iは本発明の一実施例を説明する工
程順に示した断面図、第2図a〜dは従来の多層
印刷配線板の製造方法の一例を説明する工程順に
示した断面図である。 1……絶縁板、1a,1b,1c……積層板、
2……銅箔、3……貫通孔、4……導体層、5…
…スルーホール、6……感光性ドライフイルムレ
ジスト、7……レジスト樹脂層、8……多層化基
板、9……貫通孔、10……導体層、11a,1
1b……プリプレグ層、12……銅箔、15……
ブラインド・バイア・ホール、21a,21b,
21c……積層板、22……銅箔、24……導体
層、25……スルーホール、27……レジスト樹
脂層、28……多層化基板、29……貫通孔、3
0……導体層、32……銅箔、35……ブライン
ド・バイア・ホール。
1A to 1I are sectional views shown in the order of steps to explain an embodiment of the present invention, and FIGS. 2A to 2D are sectional views shown in the order of steps to explain an example of a conventional method for manufacturing a multilayer printed wiring board. It is. 1... Insulating plate, 1a, 1b, 1c... Laminated board,
2...Copper foil, 3...Through hole, 4...Conductor layer, 5...
...Through hole, 6... Photosensitive dry film resist, 7... Resist resin layer, 8... Multilayer substrate, 9... Through hole, 10... Conductor layer, 11a, 1
1b... prepreg layer, 12... copper foil, 15...
Blind Via Hall, 21a, 21b,
21c...Laminated board, 22...Copper foil, 24...Conductor layer, 25...Through hole, 27...Resist resin layer, 28...Multilayer board, 29...Through hole, 3
0...Conductor layer, 32...Copper foil, 35...Blind via hole.

Claims (1)

【特許請求の範囲】 1 次の工程を有することを特徴とする多層印刷
配線板の製造方法。 (イ) 両面に銅箔が張り合わされた絶縁板に無電解
めつきと電気めつきによりスルーホールと導体
層を形成し、両面に導体回路パターンを形成す
る工程。 (ロ) 前記絶縁板の一面の導体回路パターン面に、
熱硬化性樹脂を塗り、乾燥し、スルーホール内
を含んでレジスト樹脂層を形成する工程。 (ハ) 前記レジスト樹脂層を有する絶縁板の導体回
路パターンを前記レジスト樹脂層を外側にして
向い合わせに各々最外層に配置し、その内側に
予め導体回路パターンを形成した少くとも1つ
の絶縁板とプリプレグ層とを介し積み重ねた後
に、加熱、加圧して多層化基板を形成する工
程。 (ニ) 前記多層化基板の所定部分に貫通孔を設ける
工程。 (ホ) 前記貫通孔を有する多層化基板の貫通孔内壁
に導体層を形成する工程。
[Scope of Claims] 1. A method for manufacturing a multilayer printed wiring board, comprising the following steps. (a) A process in which through holes and conductor layers are formed by electroless plating and electroplating on an insulating plate with copper foil laminated on both sides, and conductor circuit patterns are formed on both sides. (b) On the conductor circuit pattern surface of one side of the insulating plate,
The process of applying thermosetting resin, drying it, and forming a resist resin layer including the inside of the through hole. (c) At least one insulating plate on which the conductive circuit patterns of the insulating plates having the resist resin layer are arranged in the outermost layer facing each other with the resist resin layer on the outside, and the conductive circuit pattern is previously formed on the inside thereof. A process of stacking the substrate and the prepreg layer via heating and pressurizing to form a multilayer substrate. (d) A step of providing a through hole in a predetermined portion of the multilayer substrate. (E) A step of forming a conductor layer on the inner wall of the through hole of the multilayer substrate having the through hole.
JP29912087A 1987-11-26 1987-11-26 Manufacture of multi-layered printed circuit board Granted JPH01140698A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP29912087A JPH01140698A (en) 1987-11-26 1987-11-26 Manufacture of multi-layered printed circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP29912087A JPH01140698A (en) 1987-11-26 1987-11-26 Manufacture of multi-layered printed circuit board

Publications (2)

Publication Number Publication Date
JPH01140698A JPH01140698A (en) 1989-06-01
JPH0532919B2 true JPH0532919B2 (en) 1993-05-18

Family

ID=17868376

Family Applications (1)

Application Number Title Priority Date Filing Date
JP29912087A Granted JPH01140698A (en) 1987-11-26 1987-11-26 Manufacture of multi-layered printed circuit board

Country Status (1)

Country Link
JP (1) JPH01140698A (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03296295A (en) * 1990-04-13 1991-12-26 Hitachi Chem Co Ltd Manufacture of multilayer printed circuit board
JP3303823B2 (en) 1999-02-23 2002-07-22 日本電気株式会社 Power supply circuit
CN102065651A (en) * 2011-01-12 2011-05-18 广州兴森快捷电路科技有限公司 Production method of high-density laminated printed circuit board of high-frequency material
CN105555065A (en) * 2016-02-02 2016-05-04 东莞翔国光电科技有限公司 Manufacturing process for six-layer blind-hole plate by circuit board engraving machine

Also Published As

Publication number Publication date
JPH01140698A (en) 1989-06-01

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