JPH0533536B2 - - Google Patents

Abstract

PURPOSE:To reduce the pressure applied during diffusion welding in a multi- layer semiconductor integrated circuit, by forming the part of a vertical wire in a first active layer contacted with a vertical wire in a second active layer so as to have a triangular or trapezoidal cross section. CONSTITUTION:An end of a vertical wire 220 in a first active layer is formed to have a triangular cross section. In practice, however, it may be formed into a conical shape when the aperture in a first insulation film 202 is circular, and into a pyramid when the aperture is square. When such second active layer is superposed on the first active layer, the tip 221 of the first vertical wire 220 is contacted with the surface of a metal bump in the initial stage when no pressure is applied. Accordingly, if a slight pressure is applied after that, all the pressure is concentrated at the tip 221. The first vertical wire 220 or the metal bump is therefore easily deformed plastically. Thus, any dirty or oxide film is broken and it is facilitated to perform diffusion welding.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a multilayer semiconductor integrated circuit and a method for manufacturing the same.

[Prior art and its problems]

A multilayer semiconductor integrated circuit is an integrated circuit in which functional elements such as transistors, resistors, and capacitors are arranged three-dimensionally, and has a higher degree of integration and circuit scale than conventional integrated circuits in which functional elements are arranged two-dimensionally. It is expected that the operating speed will be increased due to improved performance and shorter wiring length. One method for realizing a multilayer semiconductor integrated circuit is to individually manufacture conventional integrated circuit elements (hereinafter referred to as active layers) in which functional elements are arranged two-dimensionally, and then stack these active layers in order. is possible. In order to realize a multilayer semiconductor integrated circuit using this method, it is necessary to provide vertical wiring in the active layer for wiring between the active layers. Further, as a method for connecting the vertical wirings provided in each active layer, a diffusion welding method and the like can be cited.

FIGS. 1 to 3 are cross-sectional views of an example of a multilayer semiconductor integrated circuit.

FIG. 1 shows a MOSFET consisting of a gate 105, a source and a drain 104, 105, a first vertical wiring 109, a horizontal wiring 107, and a second vertical wiring 1.
10 and metal bumps 111 on the semiconductor substrate 101
An example of the cross-sectional shape of the structure formed above is shown. 102 and 103 are the semiconductor substrate 101;
They are a first insulating film and a second insulating film that insulate the MOSFET and the horizontal wiring. 108 is a third insulating film for the purpose of protecting the surface, etc. An example of a method for forming the structure shown in FIG. 1 will be briefly described. First, a first insulating film 102 made of silicon dioxide or the like is formed on a semiconductor substrate 101 made of silicon or the like using a CVD method or a thermal oxidation method. Next, a gate 106 and a source or drain 10 are formed on the surface of the first insulating film 102.
A MOSFET consisting of 4,105 transistors is formed in a conventional manner. Thereafter, a second insulating layer 103 made of silicon dioxide or the like is formed using a CVD method or the like. next,
Parts of the first insulating layer 102 and the second insulating layer 103 are opened, and then the semiconductor substrate 101 in the openings is etched to a desired depth, for example, about 1 μm. When the semiconductor substrate 101 is silicon, a normal etching method such as nitric acid,
If a wet etching method using a mixed solution of acid or the like or a dry etching method using carbon tetrachloride gas or the like is used, the cross-sectional shape of the etched semiconductor substrate 101 will be approximately rectangular. Thereafter, a conductive material such as aluminum is buried in the opening and the etched region of the semiconductor substrate 101 to form a first vertical wiring 109. Further, a horizontal wiring 107 made of aluminum or the like and a third wiring made of silicon dioxide or the like are also provided.
An insulating layer 108 is formed. Finally, horizontal wiring 1
The third insulating layer 108 on the third insulating layer 108 is opened, and a conductive material such as aluminum is buried in the opening of the third insulating layer 108 to form a second vertical wiring 110 and a metal bump 111 such as gold. metal bump 11
1 is provided to facilitate diffusion welding, but is not necessarily required. When the semiconductor substrate 101 in the structure shown in FIG. 1 is removed by etching, the active layer of the multilayer integrated circuit is formed. Hereinafter, this will be referred to as the first active layer. Figure 2 shows a second active layer formed through the same process as the first active layer.
FIG. 3 is a cross-sectional view of the active layer of FIG. Elements having the same function or structure as in FIG. 1 are shown with the third digit of the element number in FIG. 1 changed from 1 to 2. For example, the first
The first insulating film 102 of the active layer corresponds to the first insulating film 202 of the second active layer. FIG. 3 is a cross-sectional view of a two-layer structure semiconductor integrated circuit in which a second active layer is laminated on a first active layer. 1 is an insulating filler between layers, which can be used as a reinforcing agent if a polyimide resin with an adhesive function is used, and can also be used as a heat dissipation layer if a diamond thin film is used.

Diffusion welding is a method for connecting the metal bumps 111 of the first active layer and the first vertical wiring 209 of the second active layer. Diffusion welding is a method in which pressure is applied to the contact surfaces of two metals of the same type or of the same type heated to around 300℃, and the molecules of both metals diffuse at the contact surface to bond them together.Other bonding methods, such as conductive adhesives, are used. The electrical resistance of the bonded part is lower than that of the bonding method or the method of bonding by melting low melting point metal such as solder.
It has features such as being able to bond fine patterns and having strong adhesive strength. On the other hand, the biggest drawback of the diffusion welding method is that diffusion welding is significantly inhibited if there is a film of dirt such as organic matter or an oxide film on the contact surface of two metals to be bonded. However, in reality, the dirt film cannot be completely removed even with cleaning, or in the case of metals such as aluminum,
There are problems such as the surface being easily oxidized, and it is actually difficult to carry out diffusion welding under the best conditions. Conventionally, the diffusion welding method used to assemble integrated circuit chips into packages, chip carriers, etc.
In order to solve these problems, pressure greater than that required for diffusion welding is applied to give plastic deformation to one or both of the materials to be bonded. As a result, the sliding stress generated on the contact surface causes the dirt film and oxide film to form. were destroyed and removed. Cylindrical or prismatic first vertical wiring 209 of the second active layer as shown in FIG.
Taking diffusion welding between the metal bump 111 of the first active layer and the second vertical wiring 209 as an example, the pressure applied to the interface between the second vertical wiring 209 and the metal bump 111 is applied to the second vertical wiring 209 and the metal bump 111 at the interface. This is the pressure that causes plastic deformation of either or both of the above. For example, when using aluminum for the second vertical wiring 209,
The pressure required for plastic deformation is calculated from the hardness of aluminum to be 20 kg/mm ² or more. Assuming that the size of the second vertical wiring 209 is 10 x 10 μm and there are 10,000 pieces per chip, the diffusion welding area is 1
mm ² , so in such a case, the first and second
The pressure required to bond the active layer is more than 20 kg. However, in the structure shown in FIG. 3, the thickness of the second active layer is very thin, at most a few microns, so the pressure shown above causes the second vertical wiring 209 to
Alternatively, the second active layer may also be destroyed at the same time as the metal bump 111 is plastically deformed.

[Purpose of the invention]

The present invention takes these circumstances into consideration and provides a structure of the first vertical wiring of the second active layer and a method for manufacturing the same, which can reduce the pressure applied during diffusion welding.

[Structure of the invention]

In the present invention, an active layer in which functional elements such as transistors, resistive elements, and capacitors, and horizontal wiring connecting these functional elements are formed in advance on the same plane, connects vertical wiring provided in each active layer. In a multilayer semiconductor integrated circuit that is sequentially stacked using a diffusion welding method, the first
A semiconductor device and mechanical elements such as transistors, resistive elements, and capacitors, and mechanical elements such as transistors, resistive elements, and capacitors, characterized in that the cross-sectional shape of the portion that contacts the vertical wiring provided in the second active layer adjacent to the active layer is triangular or trapezoidal. A multilayer active layer in which horizontal wiring connecting functional elements of the active layer is formed in advance on the same plane, and the vertical wiring provided in each active layer is sequentially laminated using a method of connecting vertical wiring by diffusion welding. In a manufacturing method for forming each active layer of a structural semiconductor integrated circuit, the step of forming the functional element on the surface of the semiconductor substrate, providing an opening in the insulating film on the surface of the semiconductor substrate on which the functional element is not formed, After forming a depression in the semiconductor substrate of the opening using an etching method such that the area of the bottom surface is smaller than the area of the opening, a conductive material is filled in the opening and the depression. After performing the step of forming vertical wiring and the step of forming the horizontal wiring, the back surface of the semiconductor substrate is removed with the functional elements, horizontal wiring, and vertical wiring formed on the front surface of the semiconductor substrate remaining. This method of manufacturing a semiconductor device is characterized in that the semiconductor substrate is removed by etching, the vertical wiring is made to protrude from the back surface, and the cross-sectional shape of the protruding region is triangular or trapezoidal.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 4 is a diagram showing a first embodiment of the present invention corresponding to FIG. 2. Parts of identical structure to elements of FIG. 2 are designated with the same numerals. 1st
Although the cross-sectional shape of the tip 221 of the vertical wiring 220 is triangular, in reality, it is conical when the opening shape of the first insulating film 202 is circular, and pyramidal when it is square. Consider the case where the second active layer shown in FIG. 4 is laminated on the first active layer 1 shown in FIG. 1. Initially, when no pressure is applied, the tip 221 of the first vertical wiring 220 and the surface of the metal bump 111 are in contact. Therefore, even if a small amount of pressure is applied after this, all the pressure will be concentrated on the tip 221, so a large pressure will be applied to this part, and the first
The vertical wiring 220 or the metal bump 111 is easily plastically deformed. Therefore, the dirt film and oxide film are destroyed and diffusion welding is performed. For example, if aluminum is used for the first vertical wiring 220 and gold is used for the metal bumps 111, the
By applying a pressure of mm ² and heating to 300°C, diffusion welding occurs, and the metal bump 111 on the second vertical wiring 110 of the first active layer is connected to the first vertical wiring of the second active layer. be done. This pressure is about 1/10 of the pressure when diffusion welding the cylindrical or prismatic first vertical wiring 209 onto the metal bump 111 shown in FIG.

FIG. 5 is a diagram showing a second embodiment corresponding to FIG. 2. Components having the same structure as those in FIG. 2 are designated by the same numbers. First vertical wiring 23
Although the cross-sectional shape of the tip 231 of the first insulating film 202 is a trapezoid, in reality, when the opening shape of the first insulating film 202 is circular, it is a truncated cone shape, and when it is square, it is a truncated pyramid shape. Consider the case where the second active layer shown in FIG. 5 is laminated on the first active layer shown in FIG.
Initially, when no pressure is applied, the first vertical wiring 23
The tip 231 of the metal bump 111 is in contact with the surface of the metal bump 111. Since this contact area is equal to the area of the tip 231, the pressure necessary for the first vertical wiring 230 or the metal bump 111 to undergo plastic deformation is equal to The vertical wiring 209 is smaller than that of the vertical wiring 209. For example, the area of the tip 231 is the same as that of the first insulating film 20.
If the area is 1/4 of the area of the opening in No. 2, the pressure required for plastic deformation will also be reduced to 1/4. Therefore, the fifth
When the second active layer with the structure shown in the figure is laminated on the first active layer, the pressure during diffusion welding can be lowered compared to the case of the second active layer shown in Figure 2. can.

As can be seen from the two types of examples shown above, the second
The area of the portion of the first vertical wiring provided in the active layer that contacts the metal bump of the first active layer before applying pressure is larger than the opening area of the opening of the first insulating film of the second active layer. By making it smaller, the pressure during diffusion welding can be lowered. Therefore, the cross-sectional shape of the first vertical wiring tip shown in FIGS. 4 and 5,
That is, the same effect can be obtained by using a repeating sawtooth-like cross-sectional shape instead of a triangle or trapezoid for the cross-sectional shape of the tip of the first vertical wiring.

Hereinafter, a method for forming the first vertical wiring provided in the second active layer according to the present invention will be described in detail. 6 to 12 show cross-sectional shapes according to the steps of a manufacturing method for realizing the structure shown in FIG. 4. In FIG. 6, for example, an insulating film 502 made of silicon dioxide or the like is formed on a semiconductor substrate 501 made of silicon or the like having a (100) plane orientation. In addition, 5
02 is an insulating layer corresponding to the first insulating film 202 and the second insulating layer 203 shown in FIG. Further, functional elements such as MOSFETs may already be formed in regions not shown in FIG. 6.
Next, as shown in FIG. 7, a portion of the insulating layer 502 where the first vertical wiring is to be provided is opened.
When the insulating layer 502 is made of silicon dioxide, the opening method may be wet etching using buffered acid or the like using a photoresist patterned by photolithography as a mask, or dry etching using carbon tetracide gas or the like. Etching is known. Next, the structure shown in Figure 7 can be etched using a solution such as hydrazine or potassium hydroxide, where the etching rate of the silicon crystal plane with the plane orientation (100) is sufficiently faster than the etching rate of the silicon crystal plane with the plane orientation (111). When immersed in the directional etching solution, the opening 5 is formed as shown in FIG.
The silicon substrate at part 03 has an inclination angle of approximately 35°.
It is etched into an inverted trapezoidal shape with a depression 504.
is formed. If you continue etching further, you will get No. 9.
As shown in the figure, a depression 50 with an inverted triangular cross-sectional shape
6 is formed, and the etching of the silicon substrate 501 is almost stopped. Thereafter, as shown in FIG. 10, a conductive material such as aluminum is buried in the openings 503 and 506 of the insulating layer 502 to form a first vertical wiring 507, and then a horizontal wiring 508 is formed. The first vertical wiring 507 corresponds to 220 in FIG. 4, and an example of its formation method will be described below.

First, a film of a conductive material such as aluminum is formed on the surface of the structure shown in FIG. 9 using a sputtering method or the like. The film thickness of this conductive material film is
Although it is preferable that the depth be equal to the depth of 0.06, the depth is not necessarily limited to this. After this, a photoresist or the like is applied by spin coating. As a result, the film thickness of the photoresist in the area of the opening 503 and the depression 506 becomes thicker than in other parts. Therefore, if the photoresist is uniformly etched by a method such as oxygen plasma ashing, the openings 503 and the depressions 506 are formed.
The photoresist in other parts is removed with the photoresist remaining only in the area. Finally, using the photoresist remaining in the area of the opening 503 and the depression 506 as a mask, the conductive material such as aluminum is etched using a technique such as dry etching using carbon tetrachloride gas. A conductive material such as aluminum is selectively buried in the region to form a first vertical wiring 507. Note that the first vertical wiring 5
Immediately before forming the first vertical wiring 507 and the substrate 501, a thin insulating layer such as silicon dioxide may be formed to separate the first vertical wiring 507 and the substrate 501. The horizontal wiring 508 corresponds to 207 in FIG. 4, and is a wiring made of aluminum or the like used in ordinary integrated circuits. Next, as shown in FIG. 11, an insulating film 5 of silicon dioxide, etc.
After that, a part of the insulating film 509 is opened, a conductive material such as aluminum is buried in the opening of the film 509, and a second vertical wiring 510 is formed.
are formed, and metal bumps 511 made of gold or the like are further formed. An example of a method for forming the metal bumps 511 made of gold or the like is a wet etching method using an iodine-based etching solution or the like using a photoresist as a mask, which is a gold film formed by sputtering on the entire surface and patterned by photolithography. There are dry etching methods such as ion milling and ion milling. Finally, the semiconductor substrate 50
If 1 is removed, the structure shown in FIG. 12 will be obtained. For example, if the semiconductor substrate 501 is a silicon substrate, nitric acid,
When the volume ratio of acid and acetic acid is selected to be 5:3:5 and etching is performed at room temperature with stirring, the silicon substrate is etched at a rate of 2 to 3 μm per minute. The resulting structure shown in FIG. 12 is the same as the left half of FIG. 4. Incidentally, if the anisotropic etching is stopped in the state shown in FIG. 8 and the steps after FIG. 10 are carried out, it is also possible to obtain a structure as shown in FIG. 5.

Although the above description has been made with a focus on a silicon substrate with a plane orientation of (100), if the plane orientation of the silicon substrate is selected other than (111), a similar structure can be obtained although the inclination angle 505 changes. Furthermore, if the cross-sectional shape of the opening 503 shown in FIG. 7 is made V-shaped and a dry etching technique is used, the recesses 505 and 506 to be formed in the semiconductor substrate 501 as shown in FIG. 8 or 9 can be formed. It is also possible to do so.

〔Effect of the invention〕

As described above, if the present invention is used to realize a multilayer semiconductor integrated circuit in which vertical wirings provided in each active layer are connected by diffusion welding, the first vertical wiring structure that requires less pressure for diffusion welding can be realized. can be obtained.

The substrate materials, insulating films, conductive materials, etching solutions, etc. used in explaining the present invention are merely examples, and are not necessarily limited to these.
Furthermore, the structure shown in FIGS. 1 to 5, for example,
Although the MOSFET structure and the multilayer semiconductor integrated circuit are shown as thin-film MOSFETs, they may also include MOSFETs, bipolar transistors, etc. formed on a normal semiconductor substrate.

[Brief explanation of the drawing]

1 to 3 show a multilayer structure semiconductor integrated circuit, FIG. 1 is a cross-sectional view of the first active layer, and FIG. 2 is a cross-sectional view of the second active layer, which is thinned by removing the semiconductor substrate from the first active layer. The cross-sectional view of the active layer in FIG. 3 shows a two-layer structure semiconductor integrated circuit in which a second active layer is laminated on a first active layer. 4 and 5 show a first embodiment and a second embodiment of the present invention, each of which is a cross-sectional view of the second active layer, and FIGS. 6 to 12 show a manufacturing method according to the present invention. FIG. 5 is a diagram illustrating the order of steps for manufacturing the vertical wiring portion of the second active layer shown in FIG. 4, that is, the left half region, as an example of the method. 1... Insulating filler, 101... Semiconductor substrate, 10
9...First vertical wiring of first active layer, 220,2
30... First vertical wiring of second active layer, 501... Semiconductor substrate, 502... Insulating layer, 503... Opening, 5
06... Depression, 507... First vertical wiring, 508...
Horizontal wiring, 509... Insulating film, 510... Second vertical wiring, 511... Metal bump.

Claims (1)

[Claims] 1. Each active layer is provided with an active layer in which functional elements such as transistors, resistive elements, capacitors, and horizontal wiring connecting these functional elements are formed in advance on the same plane. In a multilayer structure semiconductor integrated circuit in which vertical wirings are sequentially stacked using a method of connecting vertical wirings using a diffusion welding method, among the vertical wirings provided in a first active layer, the second active layer adjacent to the first active layer A semiconductor device characterized in that a cross-sectional shape of a portion that contacts a vertical wiring provided in an active layer is triangular or trapezoidal. 2 An active layer in which functional elements such as transistors, low-resistance elements, and capacitors and horizontal wiring connecting these functional elements are formed in advance on the same plane, diffuses the vertical wiring provided in each active layer. In a manufacturing method for forming each active layer of a multilayer semiconductor integrated circuit that is sequentially stacked using a welding connection method, the step of forming the functional element on the surface of the semiconductor substrate, the step of forming the functional element on the surface of the semiconductor substrate, and the step of forming the functional element on the surface of the semiconductor substrate, wherein the functional element is not formed. An opening is provided in the insulating film on the surface of the semiconductor substrate, and a recess is formed in the semiconductor substrate at the opening using an etching method such that the area of the bottom surface of the semiconductor substrate is smaller than the area of the opening. After that, a step of forming a vertical wiring by filling the opening and the recess with a conductive material, and a step of forming the horizontal wiring are performed, and then the functional elements formed on the surface of the semiconductor substrate, the horizontal wiring,
and a semiconductor characterized in that the semiconductor substrate is removed by etching from the back surface of the semiconductor substrate with vertical wiring remaining, the vertical wiring is made to protrude from the back surface, and the cross-sectional shape of the protruding region is triangular or trapezoidal. Method of manufacturing the device.