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JPH0533585B2 - - Google Patents
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JPH0533585B2 - - Google Patents

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Publication number
JPH0533585B2
JPH0533585B2 JP59155871A JP15587184A JPH0533585B2 JP H0533585 B2 JPH0533585 B2 JP H0533585B2 JP 59155871 A JP59155871 A JP 59155871A JP 15587184 A JP15587184 A JP 15587184A JP H0533585 B2 JPH0533585 B2 JP H0533585B2
Authority
JP
Japan
Prior art keywords
circuit
contour compensation
signal
video signal
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59155871A
Other languages
Japanese (ja)
Other versions
JPS6133079A (en
Inventor
Masashi Nagano
Masaaki Mochizuki
Koji Konishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP15587184A priority Critical patent/JPS6133079A/en
Publication of JPS6133079A publication Critical patent/JPS6133079A/en
Publication of JPH0533585B2 publication Critical patent/JPH0533585B2/ja
Granted legal-status Critical Current

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  • Picture Signal Circuits (AREA)

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、輪郭補償を行なう輪郭補償回路に関
するもので、画質を改善することを目的とする。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a contour compensation circuit that performs contour compensation, and its purpose is to improve image quality.

従来例の構成とその問題点 従来、輪郭補償回路は、第1図に示すように、
入力端子1から加えられた映像信号を微分回路2
で微分した第1信号と、イングクタンス等を含む
遅延回路3で映像信号を遅延した信号をもう1つ
の微分回路4で微分した第2信号とを、前記遅延
回路3で遅延した映像信号に加えて出力端子5か
ら取り出していた。輪郭補償の特性は、輪郭補償
回路の周波数特性できまる。従来の回路では、輪
郭補償を最少にした時、第2図のような周波数特
性になり、画面のソフトさに欠ける。又、画面の
ソフトさを作るために、遅延回路に多くの部品が
いり、半導体の集積回路においては、インダクタ
ンスを挿入することができないので、入力ピンを
2ピン必要とする不都合が生じる。
Configuration of conventional example and its problems Conventionally, the contour compensation circuit has the following configuration as shown in Fig. 1.
Differentiating circuit 2 converts the video signal applied from input terminal 1
A first signal differentiated by , and a second signal obtained by differentiating a signal obtained by delaying the video signal by a delay circuit 3 including inctance etc. by another differentiating circuit 4 are added to the video signal delayed by the delay circuit 3. It was taken out from output terminal 5. The contour compensation characteristics are determined by the frequency characteristics of the contour compensation circuit. In the conventional circuit, when the contour compensation is minimized, the frequency characteristics are as shown in FIG. 2, and the screen lacks softness. Further, in order to make the screen soft, many parts are required in the delay circuit, and since it is not possible to insert an inductance in a semiconductor integrated circuit, there is an inconvenience that two input pins are required.

発明の目的 本発明は、上記の不都合を排除するためになさ
れたものであつて、輪郭補償回路の周波数特性を
簡単に下げることができ、半導体集積回路におい
ても容易に構成することができる輪郭補償回路を
提供するものである。
Purpose of the Invention The present invention has been made in order to eliminate the above-mentioned disadvantages, and provides a contour compensation circuit that can easily lower the frequency characteristics of a contour compensation circuit and that can be easily configured even in a semiconductor integrated circuit. It provides a circuit.

発明の構成 本発明は、映像信号を微分した第1信号と、前
記映像信号を積分し、その積分された信号を微分
した第2信号とを、前記積分された映像信号に加
える構成をそなえた輪郭補償回路であつて、これ
によれば、映像信号を積分する量によつて周波数
特性を変化することができる。
Configuration of the Invention The present invention has a configuration in which a first signal obtained by differentiating a video signal and a second signal obtained by integrating the video signal and differentiating the integrated signal are added to the integrated video signal. This is a contour compensation circuit, and according to this circuit, the frequency characteristics can be changed depending on the amount of integration of the video signal.

実施例の説明 第3図は本発明にかかる一実施例ブロツク図を
示す。第1図の従来例とは、遅延回路3を通して
微分するか、積分回路6を通して微分するかの相
違がある。
DESCRIPTION OF THE EMBODIMENT FIG. 3 shows a block diagram of an embodiment according to the present invention. The difference from the conventional example shown in FIG. 1 is that differentiation is performed through a delay circuit 3 or an integration circuit 6.

第4図は、輪郭補償回路の具体的な一実施例回
路図を示す。
FIG. 4 shows a circuit diagram of a specific embodiment of the contour compensation circuit.

図中、7は電源端子、8は映像入力端子、9と
10はそれぞれ、輪郭補償制御端子、12は直流
電圧電源、11と13はそれぞれ、直流電圧印加
端子、14,25,32は、エミツタフオロワー
トランジスタ、15,33,35は、増幅用トラ
ンジスタ、16は積分用抵抗、17,34,3
6,38,40は、エミツタ抵抗、18は積分用
容量、19,20,21,22,28,29は差
動増幅用トランジスタ、23,24,42は、負
荷抵抗、26,31は微分用容量、27,30は
微分用抵抗、37,39は電流源用トランジス
タ、41は映像出力端子である。
In the figure, 7 is a power supply terminal, 8 is a video input terminal, 9 and 10 are each a contour compensation control terminal, 12 is a DC voltage power supply, 11 and 13 are each a DC voltage application terminal, 14, 25, and 32 are emitters. Ivy follower transistors, 15, 33, 35 are amplifying transistors, 16 are integrating resistors, 17, 34, 3
6, 38, 40 are emitter resistors, 18 is an integration capacitor, 19, 20, 21, 22, 28, 29 are differential amplification transistors, 23, 24, 42 are load resistances, 26, 31 are for differentiation Capacitors 27 and 30 are differentiating resistors, 37 and 39 are current source transistors, and 41 is a video output terminal.

次に動作を説明する。 Next, the operation will be explained.

端子8に入力された映像信号は、エミツタフオ
ロワートランジスタ14を通つて、一方は、増幅
用トランジスタ15のベースに入り、抵抗42と
抵抗17の比で増幅され、エミツタフオロワート
ランジスター25に入り、容量26と抵抗27と
の時定数で微分された信号が差動対の一方のトラ
ンジスタ28のベースに入る。他方は、抵抗16
と容量18との時定数で積分され、増幅トランジ
スタ33と35とに入る。トランジスタ35に入
つた信号は、抵抗36と抵抗24との比で増幅さ
れ、エミツタフオロワートランジスタ32に入
り、容量31と抵抗30との時定数で微分され、
差動対の他方のトランジスタ29に入る。差動対
の両トランジスタ28,29に入力された各信号
は足し合わされてトランジスタ28のコレクタに
出力され、輪郭補償制御トランジスタ20を通つ
て、トランジスタ33に加えられ、抵抗23と抵
抗34とで分割増幅された信号と足し合わされ、
端子41に出力される。輪郭補償の周波数特性は
第5図のようになり、主に、抵抗16と容量18
との積分定数で決まる。
The video signal input to the terminal 8 passes through the emitter follower transistor 14, one enters the base of the amplification transistor 15, is amplified by the ratio of the resistor 42 and the resistor 17, and is sent to the emitter follower transistor 25. A signal differentiated by the time constant of the capacitor 26 and the resistor 27 enters the base of one transistor 28 of the differential pair. The other is resistor 16
It is integrated with the time constant of the capacitor 18 and enters the amplification transistors 33 and 35. The signal entering the transistor 35 is amplified by the ratio of the resistor 36 and the resistor 24, enters the emitter follower transistor 32, and is differentiated by the time constant of the capacitor 31 and the resistor 30.
It enters the other transistor 29 of the differential pair. The signals input to both transistors 28 and 29 of the differential pair are added together and output to the collector of the transistor 28, passed through the contour compensation control transistor 20, applied to the transistor 33, and divided between the resistors 23 and 34. The amplified signal is added to
It is output to terminal 41. The frequency characteristics of contour compensation are as shown in Figure 5, and are mainly caused by resistance 16 and capacitance 18.
It is determined by the constant of integration.

発明の効果 以上実施例を用いて説明したように、本発明に
よれば、輪郭補償の周波数特性を積分の時定数に
よつて変化させることで可能であり、インダクタ
ンス等の遅延回路が不要のため、半導体集積化が
容易で、1ピン入力で構成でき、画面をソフトに
することが可能となる。
Effects of the Invention As explained above using the embodiments, according to the present invention, the frequency characteristics of contour compensation can be changed by the time constant of integration, and a delay circuit such as an inductance is not required. , it is easy to integrate semiconductors, can be configured with one pin input, and the screen can be made soft.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の輪郭補償回路のブロツク図、第
2図は従来の輪郭補償しない時の周波数特性図、
第3図は本発明の一実施例ブロツク図、第4図は
輪郭補償回路の一具体的回路図、第5図は本発明
の輪郭補償しない時の周波数特性図である。 1……映像入力端子、2と4……微分回路、3
……遅延回路、5……出力端子、6……積分回
路。
Figure 1 is a block diagram of a conventional contour compensation circuit, Figure 2 is a frequency characteristic diagram when the conventional contour compensation is not performed,
FIG. 3 is a block diagram of an embodiment of the present invention, FIG. 4 is a specific circuit diagram of a contour compensation circuit, and FIG. 5 is a frequency characteristic diagram when contour compensation is not performed according to the present invention. 1...Video input terminal, 2 and 4...Differential circuit, 3
...Delay circuit, 5...Output terminal, 6...Integrator circuit.

Claims (1)

【特許請求の範囲】[Claims] 1 映像信号を微分した第1信号と、前記映像信
号を積分しその積分された信号を微分した第2信
号とを前記積分された映像信号に加える回路構成
をそなえた輪郭補償回路。
1. A contour compensation circuit comprising a circuit configuration for adding a first signal obtained by differentiating a video signal and a second signal obtained by integrating the video signal and differentiating the integrated signal to the integrated video signal.
JP15587184A 1984-07-26 1984-07-26 Contour compensation circuit Granted JPS6133079A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15587184A JPS6133079A (en) 1984-07-26 1984-07-26 Contour compensation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15587184A JPS6133079A (en) 1984-07-26 1984-07-26 Contour compensation circuit

Publications (2)

Publication Number Publication Date
JPS6133079A JPS6133079A (en) 1986-02-15
JPH0533585B2 true JPH0533585B2 (en) 1993-05-19

Family

ID=15615323

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15587184A Granted JPS6133079A (en) 1984-07-26 1984-07-26 Contour compensation circuit

Country Status (1)

Country Link
JP (1) JPS6133079A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01294874A (en) * 1988-05-19 1989-11-28 Furukawa Electric Co Ltd:The Surface coating method
JPH02285089A (en) * 1989-04-26 1990-11-22 Eagle Ind Co Ltd Plating treatment

Also Published As

Publication number Publication date
JPS6133079A (en) 1986-02-15

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