JPH0534838B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a method for manufacturing a nonvolatile memory device suitable for manufacturing a FAMOS type EPROM having stable characteristics and high reliability.

(Prior Art) FIG. 1 shows a cross-sectional structure of a memory cell transistor of a very common FAMOS type EPROM. In FIG. 1, 1 is a silicon substrate, 2 is a field oxide film, and 3 is a gate oxide film.

After forming this gate oxide film 3, the silicon substrate 1
A source diffusion region 7 and a drain diffusion region 8 are formed on the gate oxide film 3, and then a polycrystalline silicon film 5 that will become a floating gate, an interlayer oxide film 4, and a polycrystalline silicon film 6 that will become an electrode of a control gate are formed on the gate oxide film 3. Form sequentially.

Next, after forming an intermediate insulating film 9, a contact hole is formed in the intermediate insulating film 9 at a location corresponding to the source diffusion region 7, and an Al wiring 10 is formed. After that, a passivation film 11 is applied to the entire surface.
form.

A typical conventional process from writing to shipping after forming an EPROM including a FAMOS transistor as shown in FIG. 1 using such a known process technology is shown in FIG.

In the case of EPROM, before performing a circuit function test or evaluating read speed by probing, information must first be written to all or some of the bits in the FAMOS memory, as shown in step A in Figure 2.

As is well known, how to write this information is to apply a high avalanche voltage to the drain diffusion region 8 and the polycrystalline silicon film 6 of the control gate shown in FIG.
Hot electrons generated between the drain and the source may be stored in the polycrystalline silicon film 5 of the floating gate through the gate oxide film 3.

FIG. 3 is a diagram showing this writing method,
A positive voltage of about 20 V from a power source E1 is applied to the polycrystalline silicon film 6 serving as a control gate, and the silicon substrate 1 and source diffusion region 7 are brought to earth potential. This power source E1 is a power source for injecting hot electrons into the floating gate.

In addition, a power supply E of about 15V is applied to the drain diffusion region 8.
Apply 2 positive voltages. This power source E2 is a voltage that generates hot electrons due to the avalanche effect.

In this writing method, when writing
The VTH (threshold voltage) of the FAMOS transistor is usually as high as 5 to 20V, and during erasing, this _VTH is as low as 2V or less.

If this V _TH falls within the range of V _TH between writing and erasing (for example, 2 to 5 V), a malfunction will occur when reading "1" or "0" of memory bit information.

By the way, although the integration of EPROMs has progressed in the past, the V _TH of the FAMOS transistor often increases after erasing, resulting in a decrease in manufacturing yield.

Here, the explanation returns to FIG. 2 again. In FIG. 2, as described above, when the writing process is completed in step A, a circuit function test and read speed evaluation are performed in step B, and then in step C, only non-defective products are cut into chips by scribing.

The cut chips are dice-bonded to the package at a temperature of 400 to 450°C in step D, and then wire-bonded in step E. Then, the process moves to step F, where UV-transparent glass is sealed on the package surface. Step G
to seal this glass at 450-500℃
UV irradiation is performed for about 10 minutes in _N2 to complete the assembly process, and the product is shipped in Step H.

However, if assembled using the conventional process described above,
EPROM had the following drawbacks.

In other words, when die bonding or sealing, FAMOS
Transistors are processed at high temperatures while electrons are stored in the floating gate, so thermal stress and electric field stress are applied simultaneously between the floating gate and the control gate, as well as between the floating gate and the substrate.
This significantly degraded the reliability of FAMOS transistors. This deterioration in reliability has been confirmed in the following tests.

EPROM, which is a sample equivalent to the product to be shipped after assembly, is exposed to ultraviolet light (usually at the wavelength of a mercury lamp).
After erasing the electrons from the floating gate by irradiating it with 2537 Å ultraviolet light (used),
If a high temperature storage test at 200 to 300℃ or an operation test at 100 to 200℃ is performed, electrons will accumulate in the floating gate again, causing damage to the FAMOS.
A phenomenon in which V _TH increases appeared as shown by characteristic a in FIG. 4.

This figure 4 shows the change in V _TH of the FAMOS transistor in each process by comparing the conventional and this invention. The horizontal axis shows each process, and the vertical axis shows V _TH (V). It is something.

In the case of this Figure 4, the method for measuring V _TH is V _D = 5V,
IDS=1 μA, Vsub=GND, characteristic a is the case according to the conventional process, and characteristic b is the case according to the present invention described later.

On the other hand, the above phenomenon appears in the memory function of EPROM in the form of deterioration of access time.

(Purpose of the Invention) This invention was made to solve these drawbacks.
Transistor reliability does not deteriorate,
It is an object of the present invention to provide a method for manufacturing a nonvolatile memory device that can greatly improve reliability as an EPROM element.

(Structure of the Invention) A method for manufacturing a nonvolatile storage device of the present invention includes:
In the package process after the wafer manufacturing process of FAMOS type EPROM, before heat treatment.
Irradiating the FAMOS type EPROM chip with ultraviolet light
This is designed to erase the charge in the floating gate of the FAMOS transistor.

(Example) An example of the method for manufacturing a nonvolatile memory device of the present invention will be described below with reference to the drawings. First, after completing the wafer process of the known FAMOS type EPROM shown in FIG. 1, the steps shown in FIG. 5 are performed.

First, in step A of FIG. 5, information is written into all or part of the bits of the FAMOS memory using a method similar to the conventional method.

In this state, electrons are accumulated in the floating gate of the FAMOS transistor corresponding to the bit into which information has been written.

Next, in step B, a probing test such as a circuit function test and readout speed evaluation is performed, and then in step I, a probe is placed several tens of centimeters above the wafer substrate with the surface of the wafer substrate facing up.
The entire surface of the substrate is irradiated with ultraviolet light with a wavelength of 2537 Å for 20 to 40 minutes.

Due to the step I, electrons in the floating gate escape to the control gate and the substrate, so no electrons are accumulated in the floating gate in this state.

After this, steps C to H are carried out in the same manner as in the conventional method, including scribing, die bonding, wire bonding, and sealing of ultraviolet-transmissive glass. That is, in FIG. 5, the same steps as in FIG. 2 are given the same alphanumeric characters as in FIG. 2, and their explanations are omitted.

The die bond in Step D is subjected to high-temperature thermal stress of 400 to 450°C, and the glass seal in Step F is subjected to high-temperature thermal stress of 450 to 500°C, but as mentioned above, there is no electric charge on the floating gate, so there is almost no electric field stress. It is zero.

EPROM assembled using this method or
Even if we perform the same conventional reliability tests on FAMOS transistors, that is, high-temperature storage tests at 200 to 300 degrees Celsius or operation tests at 100 to 200 degrees Celsius, there is a phenomenon that the access time deteriorates and the V _TH of the FAMOS transistors increases. has not been observed at all. As an example, the difference between characteristic b in FIG. 4 and characteristic a in the conventional case is obvious.

As explained above, in the embodiment of this invention,
After probing is completed and before the assembly process begins, the surface of the wafer substrate is irradiated with ultraviolet rays with a wavelength of 2537 Å to erase the electrons in the floating gate. The reliability of the transistor does not deteriorate.

Therefore, there is an advantage that reliability as an EPROM element can be greatly improved.

Note that a mercury lamp with a wavelength of 2537 Å is normally used to irradiate ultraviolet rays, but ultraviolet rays with an energy of 4.3 eV or more (the energy required to excite electrons from the valence band in the case of an N-type polycrystalline S ₁ gate) are used. That's fine.

(Effects of the Invention) As described above, according to the method of manufacturing a nonvolatile memory device of the present invention, after probing, ultraviolet rays are irradiated to make the floating gate of the FAMOS EPROM free of electrons, and then thermal stress is applied during assembly. By adding , the reliability of the FAMOS transistor can be greatly improved, and there is an advantage that the reliability of the EPROM element can also be greatly improved. Therefore, FAMOS type EPROM and FAMOS type EPROM
It can be used to manufacture microprocessors (LSI) equipped with

[Brief explanation of drawings]

Figure 1 is a cross-sectional view of a memory cell transistor in a typical FAMOS type EPROM, and Figure 2 is the same as Figure 1.
Flowchart showing the package assembly process of memory cell transistor of FAMOS type EPROM, Part 3
The figure shows the writing method of the memory cell transistor of the FAMOS type EPROM in Figure 1, and the figure 4 shows
FAMOS type EPROM in each step of the package assembly process of the conventional FAMOS type EPROM and the present invention.
FIG. 5, which is a diagram showing changes in V _TH of a memory cell transistor of an EPROM, is a flowchart showing a package assembly process of an embodiment of the method for manufacturing a nonvolatile memory device of the present invention. 1...Silicon substrate, 2...Field oxide film, 3...Gate oxide film, 4...Interlayer oxide film, 5
...Floating gate polycrystalline silicon film,
6...Polycrystalline silicon film of control gate,
7... Source diffusion region, 8... Drain diffusion region.

Claims (1)

[Claims] 1. FAMOS type that has completed wafer process
a step of preparing a semiconductor wafer containing an EPROM; a step of performing a probing test by injecting electrons into the floating gate of a memory cell transistor in the FAMOS type EPROM; and after the probing test,
irradiating the EPROM with ultraviolet rays for a predetermined period of time to erase the charges in the floating gate, and then scribing the semiconductor wafer;
A method for manufacturing a nonvolatile memory device, comprising the steps of forming a FAMOS-type EPROM IC chip, and then mounting the IC chip on a package.