JPH0535579B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a junction-destructive programmable read-only storage device.

[Conventional technology]

Programmable Read Only Memory
Considering its intended use, PROM (PROM) requires particularly high density storage capacity and reliable programming (writing). Reliable program execution consists in reliably selecting the storage elements in which information is to be stored. When a PROM that is in practical use is composed of bipolar elements, the unit memory element is generally
A junction destruction type that uses an element that includes two PN junctions connected in opposite directions, and writes information by destroying one of the two PN junctions.
There are PROMs and fuse-type PROMs, which use an element including a fuse and one PN junction connected to the fuse as a unit memory element, and write information by blowing the fuse.

Figures 4 and 5 show the conventional joint failure type.
FIG. 3 is a cross-sectional view and a circuit diagram of an example of a PROM.

^In this conventional example, as shown in FIG. 4, an N ^-
The epitaxial layer 3 of the mold is separated by an insulating region 11.
A bipolar unit memory element Q is constructed by forming a P ⁺ type base region 7 and forming an N ⁺⁺ type emitter region 8 within this base region 7. Such a unit memory element Q has a fourth
As shown in FIG. 5, word lines X 0 , X ₁ , etc. made up of a buried layer 2 and an epitaxial layer 3 are connected to each other, and word lines X ₀ , X ₁ , etc. are insulated from each other.
Digit lines Y ₀ , Y ₁ , etc., which connect the emitter regions 8 of each unit storage element Q, are formed perpendicularly to X _{1 ,} etc.

In the conventional example described above, a parasitic PNP transistor is generated between adjacent base regions 7 in the same word line, and since the base width of this transistor is relatively narrow, the current amplification factor is as high as about 0.5.
A latch-up occurs between the unit memory element Q itself and the npn transistor due to the parasitic pnph, causing write current leakage.

That is, writing information into this type of unit memory element Q is performed by flowing a reverse current through the PN junction between the emitter and the base with the base open to destroy this junction.
As shown in FIG. 5, when attempting to write information by passing current through the current path 52 shown by the solid line in the unit storage element _Q10 , due to the effect of the parasitic pnpn50, the current path 51 shown by the dotted line, that is, the unit storage element
All or part of the write current flows in the path that includes Q ₀₁ and Q ₁₁ , and information may not be written to the unit memory element Q ₁₀ where information should originally be written, or a defect may occur due to insufficient writing. This results in a decrease in write yield and reliability. In addition, in Fig. 5, Q ₀₁ and Q ₁₀ are
The unwritten unit storage elements Q ₀₀ and Q ₁₁ are written unit storage elements.

[Problem that the invention seeks to solve]

As explained above, the conventional joint failure type
PROMs have the disadvantage that write current leakage occurs due to latch-up between adjacent unit memory elements, making writing unstable and reducing write yield and reliability.

[Means for solving problems]

The programmable read-only storage device of the present invention includes a semiconductor substrate of a first conductivity type, and a high concentration buried region of a second conductivity type different from the first conductivity type on the upper surface side of the semiconductor substrate. , a low concentration semiconductor layer of the second conductivity type on the buried region, a unit element isolation region reaching from the upper surface side of the semiconductor layer to the semiconductor substrate, and the unit element isolation region surrounded by the unit element isolation region. A programmable device comprising: a unit device region having a base region of a first conductivity type and an emitter region of the second conductivity type; and a highly concentrated collector region of the second conductivity type adjacent to the unit device region. In a read-only storage device, the unit element regions are connected by providing at least one gap in the unit element isolation region, and
The connecting portion has a high concentration impurity region of the second conductivity type.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1a is a plan view showing the main parts of a first embodiment of the PROM of the present invention, and FIGS. 1b to 1e are sectional views thereof. In FIG. 1a, unit memory element Q
are connected in a line by providing a gap S in the unit isolation region 4, and the unit isolation region 5
A highly concentrated N ⁺ type impurity region 10 is provided between the unit element isolation region 5 and the portion of the unit element isolation region 4 facing the gap S provided therein.
Figures 1 b to e represent Figure 1 a to A-A, respectively.
It is a sectional view when cut along BB, CC, and DD. Here, 1 is a P ^- type silicon semiconductor substrate, 2 is an N ⁺ type buried layer, 3 is an N ^- type epitaxial layer, 6 is an insulating film, 7 is a P ⁺ type base region,
8 is an N ⁺⁺ type emitter region, and 9 is an N ⁺ type collector region.

In the embodiment shown in FIGS. 1a to 1e, a unit element isolation region 4 is provided between unit memory elements Q, and the parasitic pnp generated between the base regions 7 of the unit memory elements Q is
The base width of transistors is increasing. Furthermore, since the highly concentrated N ⁺ type impurity region 10 exists between the unit element isolation region 4 and the unit element isolation region 5 facing it, the base concentration of the parasitic pnp transistor is high, and therefore the parasitic pnp transistor The current amplification factor can be significantly reduced. For example, the base width of the parasitic pnp transistor that occurs between the base regions 7 of the unit memory element Q is 15 μm.
m and the impurity concentration of the impurity region 10 is approximately 10 ¹⁹ , the current amplification factor βpnp of the parasitic pnp transistor is
is approximately 0.001. If the current amplification factor βnpn of the npn transistor of the storage element Q itself, which is composed of the base region 7 and emitter region 8 formed in the storage element region, is 50, then βnpn×βnpn=0.05,
Conditions in which latch-up does not occur (βpnp×βnpn<
1) is satisfied. Moreover, this impurity region 10
Since the resistance value from the memory element Q to the collector region 9 is lowered, it also has the advantage of reducing the write energy. Therefore, in the embodiments shown in FIGS. 1a to 1e, there is no leakage of write current, and information can be reliably and efficiently written to the unit storage element Q in which information is to be stored.

FIG. 2 is a plan view showing one block including four unit storage elements of the embodiment shown in FIGS. 1a-e.

FIG. 3 is a plan view of a second embodiment of the invention. In this embodiment, the unit element isolation region 4
The shape of the gap provided is different from that in the embodiment shown in FIGS. 1a to 1e.

Methods for manufacturing unit element isolation regions include a method in which they are formed by selective oxidation, and a method in which trenches are selectively dug, side surfaces are oxidized, and then the trenches are filled with a material such as polysilicon.

The high concentration N ⁺ type impurity region can be formed in the same process as the high concentration N ⁺ type collector region provided across the unit element regions arranged in a row. Therefore, the present invention provides a high concentration N ⁺ type collector region that can be formed between memory elements in one unit element isolation process and without increasing the number of processes, without providing unit element separation regions with different depths. The current amplification factor of the parasitic Pnp transistor can be significantly reduced, achieving the objective.

〔Effect of the invention〕

As explained above, the present invention improves the current amplification factor of the parasitic pnn transistor that occurs between unit memory elements by
By widening the base width and increasing the base concentration, it is possible to reduce the
Since the latch-up that occurs between PROM unit memory elements does not occur, a highly reliable PROM with a good write yield can be obtained.

[Brief explanation of drawings]

FIG. 1a is a plan view showing the main parts of the first embodiment of the PROM of the present invention, and FIGS. 1b to 1e are AA, BB, CC, The cross-sectional view taken along the line D-D, Figure 2, is the same as Figures 1 a-e.
3 is a plan view showing a block of one of the embodiments shown in FIG. 3, FIG. 3 is a plan view of a second embodiment of the present invention, and FIG.
FIG. 5 is a circuit diagram for explaining the write operation of the conventional example shown in FIG. 4. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Buried layer, 3... Epitaxial layer, 4, 5... Unit element isolation region, 6
... Insulating film, 7 ... Base region, 8 ... Emitter region, 9 ... Collector region, 10 ... Impurity region, Q ... Unit memory element, S ... Gap, Q ₀₁ ,
Q ₁₀ ... unwritten unit memory element, Q ₀₀ , Q ₁₁ ...
Written unit memory element, 50...parasitic pnpn,
51, 52... Current path, X ₀ , X ₁ ... Word line,
Y ₀ , Y ₁ ...digit lines.

Claims (1)

[Scope of Claims] 1. A semiconductor substrate of a first conductivity type, a high concentration buried region of a second conductivity type different from the first conductivity type on the upper surface side of the semiconductor substrate, and this buried region. a low concentration semiconductor layer of the second conductivity type above, a unit element isolation region reaching from the upper surface side of this semiconductor layer to the semiconductor substrate, and a semiconductor layer of the first conductivity type surrounded by the unit element isolation region. a programmable read-only storage device comprising: a unit element region having a base region and an emitter region of the second conductivity type; and a highly concentrated collector region of the second conductivity type adjacent to the unit element region. In this step, the unit element regions are connected by providing a gap in at least one place in the unit element isolation region, and a high concentration impurity region of the second conductivity type is provided in the connecting portion. A programmable read-only storage device comprising: 2. The programmable read-only storage device according to claim 1, wherein the unit element region is connected to the collector region by a gap between the unit element isolation regions. 3 Collector regions sandwiching unit element regions arranged in a row are connected by a current path formed by a unit element isolation region.
Programmable read-only storage device as described in Section 1.