JPH0691221B2 - Semiconductor memory device - Google Patents

Description

The present invention relates to a semiconductor memory device, and more particularly to a 6-transistor type semiconductor memory device having a pair of CMOS inverters.

[Technical background of the invention and its problems]

A 6-transistor type semiconductor memory device (static memory) having a pair of CMOS inverters has a circuit configuration shown in FIG. That is, Qp ₁ and Qn ₁ in the figure are one CM
A p-channel MOS transistor and an n-channel MOS transistor forming an OS inverter. Qp ₂ in the figure,
Qn ₂ is a p-channel M that forms the other CMOS inverter
It is an OS transistor and an n-channel MOS transistor. The gate of one CMOS inverter is connected to the common drain part D ₂ of each transistor of the other CMOS inverter, and the gate of the other CMOS inverter is connected to the common drain part D ₁ of one CMOS inverter, and the flip-flop circuit is connected. Are configured. The sources of the p-channel MOS transistors Qp ₁ and Qp ₂ are connected to V _DD , and the n-channel MOS transistors Qn ₁ and Qn ₂ are connected to V _SS , respectively. Said common drain portion D ₂ of the common drain part D ₁ and the transistor Qp _2, Qn ₂ transistors Qp _1, Qn ₁ of the flip-flop circuit is set each V _DD potential, the V _SS potential, holds the information There is. For example, when the common drain portion D ₁ is at the V _DD potential, the transistor Qp ₂ is turned off and the transistor Qn ₂ is turned on so that the common drain portion D ₂ is at the V _SS potential.
Qp ₁ turns on and transistor Qn ₁ turns off. Also, Q
n ₃ and Qn ₄ are n-channel MOS transistors that function as transfer gates, and one of the MOS transistors Qn
₃ is connected to the node of the flip-flop circuit, and the other MOS transistor Qn ₄ is connected to the node of the flip-flop circuit. Wherein the drain side of the transistor Qn _3, Qn ₄ are respectively the bit line BL _1, BL ₂ is connected and the gate of each transistor Qn _3, Qn ₄ is connected to a word line WL. The transistors Qn ₃ and Qn ₄ are turned on when a memory cell is selected and writing and reading are performed, and the bit lines BL ₁ and BL connected to the drain side of the transistors Qn ₃ and Qn ₄ are connected. Information is transmitted between ₂ and the flip-flop circuit.

When information is written in the memory cell described above, for example, the common drain portion D ₁ is V _SS potential and the common drain portion D ₂ is V _DD.
When the potential is set, the bit line BL ₁ is set to V _SS level and the bit line BL ₂ is set to V _DD level, and the transistors Qn ₃ and Qn ₄ as transfer gates are turned on by the word line WL. On the other hand, in the case of reading, the bit lines BL ₁ and BL ₂ are connected to a sense up circuit (not shown) to form a transistor as a transfer gate.
Turn on Qn ₃ and Qn ₄ .

As the memory cell of the above-mentioned 6-transistor type static memory, the structure shown in FIGS. 6 to 8 is conventionally known. Qp ₁ and Qn ₁ in the figure are p-channel MOS transistors and n-channel MOS transistors forming one CMOS inverter, and Qp ₂ and Qn ₂ in the figure are p-channel MOS transistors and n forming the other CMOS inverter.
These are CMOS inverters, and these CMOS inverters form a flip-flop circuit by cross-connecting one gate to the common drain part of the other. In addition, Qn ₃ and Qn ₄ in the figure are the n-channels described above.
It is an n-channel MOS transistor as a transfer gate connected to the drain side of the MOS transistors Qn ₁ and Qn ₂ .

As shown in FIGS. 7 and 8, the p-channel MOS transistors Qp ₁ and Qp ₂ are formed in the island region separated by the field oxide film 3 of the n-type silicon substrate 2 in which the p-well 1 is selectively formed. Each is formed. One transistor Qp
₁ includes a p ⁺ type source 4 ₁ and a drain region 5 ₁ which are electrically isolated from each other in the island region of the substrate 2 and a channel region between the source and drain regions 4 ₁ and 5 _1. From the gate electrode 7 ₁ which is disposed on the substrate 2 via the gate oxide film 6 and which is shared by the gate of the n-channel MOS transistor Qn ₁ and is made of, for example, phosphorus-doped first layer n-type polycrystalline silicon. It is configured. The other transistor Qp ₂ includes the p ⁺ -type source 4 ₁ and the drain region 5 ₂ which are electrically isolated from each other in the island region of the substrate _2.
When these sources are arranged through a gate oxide film 6 on the substrate 2 including a channel region between the drain region 4 _1, 5 _2, the n-channel MOS transistor for example phosphorus doped to be common with the gate of the Qn ₂ and a first layer n-type polycrystalline made of silicon gate electrode 7 ₂ Metropolitan that is.
The p ⁺ type source region 4 ₁ is formed by the transistors Qq ₁ and Q
It is shared by both p ₂ and functions as a V _DD line. In addition, the transistors Qn ₁ and Qn ₂ have a field oxide film 3
Are formed in the island regions of the p-well 1 separated by. One of the transistors Qn ₁ is an n ⁺ type source formed in the island region of the p-well 1 so as to be electrically isolated from each other.
4 ₂ , drain region 5 ₃ and these source and drain regions
4 through _2, 5 gate oxide film on the well 1 includes a channel region between the ₃ (not shown) is disposed, and a gate electrode 7 _{Tokyo and} composed of the first layer n-type polycrystalline silicon . The other transistor Qn ₂ is an n ⁺ type source formed in the island region of the p-well 1 so as to be electrically isolated from each other.
4 ₃ , drain region 5 ₄ and these source and drain regions
It is arranged on the well 1 including the channel region between 4 ₃ and 5 ₄ via a gate oxide film (not shown), and is composed of the first-layer gate electrode 7 _{2 made of} n-type polycrystalline silicon. . Further, as shown in FIG. 8, one of the transistors Qn _{3 serving} as the transfer gate has an n ⁺ -type source region and drain common to the drain region 5 ₃ electrically isolated from each other in the island region of the well 1. a region 5 _5, these source and drain regions _(3), is arranged through the gate oxide film 6 in the well 1 region comprising a channel region between the 5 _5, for example, phosphorus which is common with the other transistor Qn ₄ Gate electrode made of doped first layer n-type polycrystalline silicon 7 ₃
It consists of and. The other transistor Qn
Reference numeral ₄ denotes an n ⁺ -type source region and drain region 5 ₆ which are electrically isolated from each other in the island region of the well 1 and are common to the drain region 5 ₄ and between these source and drain regions (5 ₄ ) and 5 _6. is arranged through a gate oxide film (not shown) in well 1 region containing the channel region, and a gate electrode 7 ₃ which consists of the first layer n-type polycrystalline silicon.
Incidentally, the gate electrode 7 ₃ functions as a word line WL.

Further, on the substrate 2 including the gate electrode 7 _{1-7 3,} first
Are first CVD-SiO ₂ film ₈₁ is coated as an interlayer insulating film layer, and wherein said the CVD-SiO ₂ film 8 ₁ on the first layer n-type polycrystalline silicon the same conductivity type impurities (Phosphorus) -doped second layer n-type polycrystalline silicon V _SS power supply wiring
9 ₁ and 9 ₂ are provided. These V _SS power supply wirings 9 ₁ and 9 ₂
It is connected to the transistor Qn _1, the source region of Qn ₂ 4 _2, 4 ₃ via the contact hole 10 _1, 10 ₂ which are opened in the first CVD-SiO ₂ film _81. Wiring for V _SS power supply
Since each of 9 ₁ and 9 ₂ also serves as the wiring of the adjacent memory cell, one is arranged in each memory cell. Then, the first CVD-SiO ₂ including the V _SS power supply wirings 9 ₁ and 9 ₂ is formed.
On the membrane _81, a second CVD-S as an interlayer insulating film of the second layer
iO ₂ film 8 ₂ is covered, and the second CVD-SiO ₂ film 8 ₂
A pair of intersecting Al wirings 11 ₁ and 11 ₂ are arranged on the upper side so as to cross the island region of the substrate 2 and the island region of the well 1, respectively. On the other hand, the crossing Al wiring 11 ₁ has contact holes 10 ₃ and 10 formed over the first and second CVD-SiO ₂ films 8 ₁ and 8 ₂ as shown in FIGS. 7 and 8. ₄ , 10 ₅ via the drain region 5 ₁ of the transistor Qp _{1 and} the gate electrode 7 ₂
Of the field oxide film 3 and the drain region 5 ₃ of the transistor Qn ₁ . The other intersection for Al wiring 11 ₂ first, second CVD-SiO ₂ film
Contact holes 10 ₆ , 10 ₇ , opened across 8 ₁ and 8 ₂ ,
The via 10 ₈ transistor Qp ₂ of the drain region 5 _2, are respectively connected to the drain region 5 ₄ of the gate electrode 7 ₁ of the field oxide film 3 extending portion 7b and the transistor Qn ₂ extending on . By providing such cross for Al wiring 11 _1, 11 _2, the gate electrode 7 _second transistor Qp _2, Qn ₂ constituting the other CMOS inverter, the transistor Qp _1, Qn ₁ constituting one of the CMOS inverters drain regions 5 _1, 5 ₃ Al wiring the crossing 11 ₁ and the contact hole 10 ₃
The gate electrodes 7 ₁ of the transistors Qp ₁ and Qn _{1 which} are cross-connected through ~ 10 ₅ and constitute one of the CMOS inverters are
Transistors Qp ₂ and Qn ₂ that form the other CMOS inverter
Are cross-coupled through the drain region 5 _2, 5 ₄ the crossing for Al wiring 11 ₂ and the contact hole 10 ₆ to 10 _8, whereby said flip-flop circuit of each CMOS inverter are cross-connected to each other is realized. In addition, the second CVD-SiO
On ₂ film 8 _2, Al wiring 12 as the bit line _1, 12 ₂ (B
L ₁ and BL ₂ ) are provided, and these Al wirings 12 ₁ and 12 ₁ are contact holes 10 ₉ opened over the first and second CVD-SiO ₂ films 8 ₁ and 8 _2. , 10 ₁₀ through the drain region of the transistors Qn ₃ and Qn ₄ as the transfer gate
They are connected to 5 ₅ and 5 ₆ , respectively. In the figure, 13 is a second CV including the crossing Al wirings 11 ₁ and 11 ₂ and Al wirings 12 ₁ and 12 _2.
A protective layer coated on the D-SiO ₂ film 8 _2.

Incidentally, CMOS is accompanied by a latch-up phenomenon as is well known. This is the latch-up phenomenon of the CMOS structure shown in FIG.
That is, description will be made with reference to a schematic diagram showing the thyristor effect and its equivalent circuit diagram shown in FIG.

Reference numeral 21 in FIG. 9 is an n-type silicon substrate.
A p-well 22 is selectively provided on the surface. A field oxide film 23 for separating element regions is formed on the surface of the substrate 21 including the well 22. In the island region of the substrate 21 separated by the field oxide film 23, p ⁺ type source and drain regions 24 are electrically isolated from each other.
₁ , 25 ₁ are provided. The island region of the substrate 21 adjacent to the source region 24 ₁ is for biasing the substrate 21.
An n ⁺ type diffusion region 26 ₁ is formed. A gate electrode 28 ₁ made of polycrystalline silicon is provided on the substrate 21 including the channel region between the source / drain regions 24 ₁ and 25 ₁ via a gate oxide film 27. In the island region of the p-well 22 separated by the field oxide film 23, p ⁺ type source and drain regions 24 ₂ and 25 ₂ are electrically isolated from each other.
Is provided. The source region 24 ₂ island region of the well 22 adjacent to, for biasing the well 22 p ⁺
-Type diffusion region 26 ₂ is provided. A gate electrode 28 ₂ made of polycrystalline silicon is provided on the well 22 including the channel region between the source / drain regions 24 ₂ and 25 ₂ via a gate oxide film 27.

An interlayer insulating film 29 is coated on the entire surface of the substrate 21 including the gate electrodes 28 ₁ and 28 ₂ . On the interlayer insulating film 29, a source Al wiring 30 connected to both the p ⁺ type source region 24 ₁ and the n ⁺ type diffusion region 26 ₁ via a contact hole,
A drain Al wiring 31 connected to the drain region 25 ₁ through a contact hole and a gate Al wiring 32 connected to the gate electrode 28 ₁ through a contact hole are provided. Further, on the interlayer insulating film 29, the
A source Al wiring 33 connected to both the n ⁺ type source region 24 ₂ and the p ⁺ type diffusion region 26 ₂ via a contact hole, and a drain Al wiring connected to the drain region 25 ₂ via a contact hole. A gate Al wiring 35 connected to the gate electrode 28 ₂ and the gate electrode 28 ₂ is provided, respectively. The gate Al wirings 32 and 35 are on the V _in side, the drain Al wirings 31 and 34 are on V _out , and the source Al wiring 30 of the p-channel MOS transistor is V _DD.
The source Al wiring 3 of the n-channel MOS transistor
3 are each connected to V _SS . In such a CMOS structure, the n ⁺ type source region 2 of the n-channel MOS transistor is used.
4 ₁ and p- well 22 and the n-type silicon substrate 21 respectively the emitter, base, parasitic npn transistor Qn to a collector,
And p ⁺ type source region 2 of p channel MOS transistor
4 ₂ and the n-type silicon substrate 21 and the p- well 22 respectively emitter, base, parasitic transistor Qp which the collector is formed, latchup phenomenon as shown below when the CMOS operation.

When the source / drain regions 24 ₁ , 24 ₂ , 25 ₁ , 25 ₂ of each MOS transistor are miniaturized due to high integration of the CMOS inverter, for example, when the n-channel MOS transistor is turned on, the vicinity of the drain region 25 ₂ A hole is generated by the impact ionization and the potential of the p-well 22 is raised. When the potential of the p-well 22 rises, the parasitic npn transistor Qn based on the well 22 causes a bipolar action, and the collector current I _{RS of the} transistor Qn flows through the n-type substrate 21. Since this collector current I _RS flows through the resistance Rs of the n-type silicon substrate 21 on the V _DD side, the parasitic pnp transistor Q described above is used.
As the base potential of p is lowered, the transistor Qp
Make a bipolar action. As a result, the collector current I _RW of the transistor Qp comes to flow. Then, the collector current I _RW flows in the p-well 22,
The resistance Rw raises the base potential of the parasitic npb transistor Qn, and even after the impact ionization does not occur, the rise of the base potential causes the transistor Qn to perform a bipolar action. Due to the bipolar action of the transistor Qn, its collector current I _RS further lowers the base potential of the parasitic pnp transistor Qp, making it easier for the collector current I _RW of the transistor Qp to flow, thereby further increasing the base potential of the parasitic npn transistor Qn. A large current flows from V _DD to V _SS due to the positive feedback of increasing the collector current of the transistor Qn and further increasing the collector current. Due to the latch-up current, the CMOS does not operate, and the integrated circuit having the CMOS (static memory)
Is thermally destroyed by a large current. like this,
Rs (resistance of n-type silicon substrate 21) shown in FIGS. 9 and 10 is an effective means for improving the latch-up resistance.
And Rw (resistance of p-well 22).
Specifically, by providing a p ⁺ -type diffusion region for biasing the well formed in the p-well for each CMOS inverter and connecting a wiring for biasing each diffusion region, the well is formed. The resistance should be lowered.

Therefore, in the memory cells of the static memory shown in FIGS. 6 to 8 described above, a pair of CMOS inverters are cross-connected to each other to form a flip-flop circuit.
A pair of crossed for Al wiring on the second CVD-SiO ₂ film 8 ₂ 11 _1, 11 ₂
Since the are provided, Al wiring density for determining the pitch of the memory cells on CVD-SiO ₂ film 8 ₂ of the second decreases. Therefore, the V _SS power supply wirings 9 ₁ and 9 _{2 are formed} on the first CVD-SiO ₂ film 8 _1.
The second layer of n-type polycrystalline silicon to form a second CV
It is compensated density decrease of the Al wiring of on D-SiO ₂ film 8 _2. The V _SS power supply wirings 9 ₁ , 9 _{2 made of} such n-type polycrystalline silicon
Is a diffusion region of the same conductivity type as the n-type impurity in the polycrystalline silicon, that is, an n-channel MO as shown in FIGS.
S transistor Qn ₁ and n of the same channel transistor Qn ₂
Ohmic contact can be made to the ⁺ type source regions 4 ₂ and 4 ₃ .

However, the V _SS power supply wirings 9 ₁ and 9 ₂ are commonly connected to the p ⁺ type diffusion region for biasing the well 1 formed in the p-well 1 together with the source region, and the well 1 If the resistance is lowered and the latch-up withstanding capability is improved, a pn junction is formed at a contact portion between the V _SS power source wiring made of the n-type polycrystalline silicon and the p ⁺ -type diffusion region to obtain a good ohmic contact. Becomes difficult. As a result, in the static memory shown in FIGS. 6 to 8, the area for forming the Al wiring for the well bias is provided in a region different from the memory cell region, for example, every 8 cells. Therefore, in the conventional static memory, four Al wirings (two for cross connection and two bit lines) are crossed on each _second CVD-SiO ₂ film for each memory cell. The pitch width in the X direction increases,
Moreover, since the area for forming the Al wiring for the well bias is provided in a region different from the memory cell region, the area of the memory itself increases and the total integration degree of the memory decreases. Further, since the Al wiring for the well bias can be formed only every 8 memory cells, the latch-up resistance cannot be sufficiently improved.

Therefore, as shown in FIGS. 11 to 13, the second
An attempt has been made to a static memory memory cell in which a pair of CMOS inverters are cross-connected to each other by using a layer of polycrystalline silicon. That is, the memory cell is a pair of cross-wires made of a second layer polycrystalline silicon in the first CVD-SiO ₂ film 8 ₁ on 1
4 ₁ and 14 ₂ are arranged so as to cross the island-shaped substrate 2 region and the island-shaped well 1 region, respectively. One crossed wire 14 _1, a first CVD-Si As shown in Figure 12 and Figure 13
P connected to the p ⁺ -type drain region 5 ₁ of the transistor Qp ₁ through a contact hole 15 ₁ opened in the O ₂ film 8 _1.
Field wiring of the first-layer n-type polycrystalline silicon gate electrode 7 ₂ through the wiring portion 16a of the first-type polycrystalline silicon and the contact holes 15 ₂ and 15 ₃ opened in the CVD-SiO ₂ film 8 _1. The extending portion 7a extending on the film 3 and the transistor Qn
₁ n ⁺ type drain region 5 ₃ and an n type polycrystalline silicon wiring portion 17a connected to each. The other cross wiring 14 ₂ is connected to the p ⁺ type drain region 5 ₂ of the transistor Qp ₂ through the contact hole 15 ₄ formed in the first CVD-SiO ₂ film 8 ₁ and then the p-type polycrystalline silicon. Wiring part 16b
When the contact hole 1 is opened in the CVD-SiO ₂ film 8 ₁
5 _5, 15 ₆ through by the first layer n-type polycrystalline extending portion 7b field extending over the oxide film 3 of the gate electrode 7 ₁ made of silicon and the transistor Qn ₂ n ⁺ -type drain region 5 ₄ And an n-type polycrystalline silicon wiring portion 17b connected to each of the wirings.

Further, the intersecting wiring 14 _1, first comprising 14 ₂ CVD-SiO ₂
On the membrane _81, a second CVD-SiO ₂ film 8 ₂ is covered.
P This second on CVD-SiO ₂ film 8 ₂ constituting the p-type constituting the cross wiring 14 _1, n-type polycrystalline silicon wiring portion 16a, a 17a and between the cross wire 14 ₂ -Type and n-type polycrystalline silicon wiring portions 16b, a pair of Al layers 18 for eliminating the adverse effect on the electrical effect of the pn junction formed between 17b
₁ , 18 ₂ are provided. In other words, one Al layer 18 ₁ is the p-type, n-type polycrystalline silicon wiring portion 16a, pn between 17a
The intersecting wiring 1 is formed through an elongated contact hole 19 ₁ opened in the second CVD-SiO ₂ film 8 ₂ including a bonding portion.
Connected to 4 ₁ . The other Al layer 18 ₂ is an elongated contact hole formed in the second CVD-SiO ₂ film 8 ₂ including a pn junction between the p-type and n-type polycrystalline silicon wiring portions 16b and 17b. It is connected to the cross wiring 14 ₂ via 19 ₂ .

However, in the static memory having the structure shown in FIG. 11 to FIG.
Although it is lower than the static memory of FIGS. 8 to 12, _two Al wirings 12 ₁ and 12 ₂ as bit lines and a _second wiring
There is no change in that a total of four Al layers 18 ₁ and 18 ₂ for ohmic connection of the intersecting wirings 14 ₁ and 14 _{2 made} of polycrystalline silicon are required. The pitch width of the cell in the X direction cannot be reduced. Therefore, even in the static memory having such a structure, the cell size cannot be reduced from that of the conventional static memory, and since the second layer n-type polycrystalline silicon is used as the V _SS power supply wiring, it is used for the well bias. The provision of an area different from the cell area for forming the Al wiring does not improve the degree of integration of the memory itself or the sufficient improvement of the latch-up resistance.

[Object of the Invention]

An object of the present invention is to provide a semiconductor memory device in which the pitch widths of the memory cells in the X and Y directions and the memory itself can be miniaturized and the latch-up withstand capability is remarkably improved.

[Outline of Invention]

The present invention has a pair of CMOS inverters, and a flip-flop circuit formed by cross-connecting the gate electrode of one CMOS inverter to the drain region of each transistor of the other CMOS inverter via wiring, and this flip-flop circuit. In a semiconductor memory device in which a memory cell composed of a pair of transfer MOS transistors connected to each node of the circuit and a semiconductor substrate is integrated in a matrix on a semiconductor substrate, the gate electrode of the CMOS inverter has conductivity. The first-layer polycrystalline silicon containing impurities to be provided is formed, and the wiring is formed from second-layer polycrystalline silicon containing impurities to provide conductivity, which is arranged on the first-layer interlayer insulating film covering the gate electrode. And a contact formed between the wiring and the drain region having a conductivity type opposite to that of the impurities in the wiring. The semiconductor memory device is characterized in that at least a metal is buried in the contact hole, and the gate electrode of the transfer MOS transistor is formed of second-layer polycrystalline silicon containing an impurity imparting conductivity. In the semiconductor memory device having such a structure, a metal wiring to be one power source is provided on the second layer interlayer insulating film covering the cross wiring, and the metal wiring is connected to the source region of one CMOS inverter and this source region. It is possible to connect via a contact hole to both the source region for biasing the substrate region in which is formed and the diffusion region of the opposite conductivity type. In addition, by forming the gate electrode of the transfer MOS transistor by the second-layer polycrystalline silicon, the gate electrode of the transfer MOS transistor is formed on the gate electrode made of the first-layer polycrystalline silicon forming each CMOS inverter. It becomes possible to overlap through one layer of interlayer insulating film. As a result, as described above, the X direction and Y direction of the memory cell are
The pitch width in the direction can be reduced and the memory itself can be highly integrated, and the latch-up resistance can be significantly improved.

Example of Invention

Hereinafter, an example in which the present invention is applied to a CMOS static memory will be described in detail with reference to FIGS.

Qp ₁ and Qn ₁ in the figure are p forming one of the CMOS inverters.
Channel MOS transistors, n-channel MOS transistors, Qp ₂ and Qn ₂ in the figure are p-channel MOS transistors and n-channel MOS transistors forming the other CMOS inverter, and these CMOS inverters have one gate common to the other. A flip-flop circuit is formed by cross-connecting the drain portions to each other. Also,
Qn ₃ and Qn ₄ in the figure are the n-channel MOS transistors Q described above.
It is an n-channel MOS transistor as a transfer gate connected to the drain side of n ₁ and Qn ₂ .

As shown in FIGS. 2 to 4, the p-channel MOS transistors Qp ₁ and Qp ₂ are formed in an island region separated by a field oxide film 53 of an n-type silicon substrate 52 in which a p-well 51 is selectively formed. Each is formed. One transistor Qp
₁ includes a p ⁺ type source 54 ₁ and a drain region 55 ₁ which are electrically isolated from each other in an island region of the substrate 52, and a channel region between the source and drain regions 54 ₁ and 55 _1. The gate oxide film 56 is disposed on the substrate 52, and the n
It is composed of a gate electrode 57 ₁ made of, for example, phosphorus-doped first layer n-type polycrystalline silicon which is commonly used with the gate of the channel MOS transistor Qn ₁ . The other transistor Qp ₂ includes a p ⁺ -type source 54 ₁ and a drain region 55 ₂ which are electrically isolated from each other in an island region of the substrate 52, and between the source and drain regions 54 ₁ and 55 _2. Of the first-layer n-type polycrystalline silicon doped with, for example, phosphorus, which is disposed on the substrate 52 including the channel region of the gate electrode via the gate oxide film 56 and is shared with the gate of the n-channel MOS transistor Qn _2. and a electrode 57 _2. The p ⁺ type source region 54 ₁ is shared by both the transistors Qp ₁ and Qp ₂ and functions as a V _DD line.

The transistors Qn ₁ and Qn ₂ are formed of a field oxide film.
They are formed in the island regions of the p-well 51 separated by 53, respectively. One of the transistors Qn ₁ has an n ⁺ type source region 54 ₂ and a drain region 55 ₃ which are electrically isolated from each other in the island region of the p-well 51, and these source and drain regions 54 ₂ , 55. It is arranged through the gate oxide film 56 on a well 51 containing a channel region between the _3, and a gate electrode 57 ₁ Metropolitan composed of the first layer n-type polycrystalline silicon. The other transistor Qn ₂ includes an n ⁺ type source region 54 ₃ and a drain region 55 ₄ which are electrically isolated from each other in the island region of the p-well 51, and these source and drain regions 54 ₃ and 55. It is arranged through a gate oxide film (not shown) on a well 51 containing a channel region between _4, and a gate electrode 57 ₂ which made of the first layer n-type polycrystalline silicon. The gate electrode 57 ₂ is directly contacted with the n ⁺ type drain region 55 ₃ . In addition,
The p-well 51 adjacent to the n ⁺ type source regions 54 ₂ and 54 ₃
Are provided with p ⁺ type diffusion regions 58 ₁ and 58 ₂ for well bias, respectively.

Further, on the substrate 52 including the gate electrode 57 ₁ and 57 _2,
The first CVD-SiO ₂ film 59 ₁ as an interlayer insulating film of the first layer is coated. Then, on the CVD-SiO ₂ film 59 ₁ , a pair of intersecting wirings 60 ₁ and 60 ₂ doped with a conductivity-imparting impurity, for example, phosphorus, are formed in the island region and the well of the substrate 52, respectively.
It is arranged so as to cross 51 island regions. One crossed wire 60 _1, first, as shown in FIG. 1-FIG. 3 CVD-
It opened in the SiO ₂ film 59 _1, a metal (e.g., tungsten) 61 ₁
Is connected to the p ⁺ -type drain region 55 ₁ of the transistor Qp ₁ through the buried contact hole 62 ₁ . In addition, the cross wiring 60 ₁ is connected to the n ⁺ type drain region 55 ₃ through the contact hole 62 ₂ opened in the CVD-SiO ₂ film 59 _1.
It is connected to the gate electrode 57 ₂ formed of a first layer n-type polycrystalline silicon which is direct contact. The other cross wiring 60 ₂ is opened in a first CVD-SiO ₂ film 59 _1, via the contact hole 62 ₃ tungsten 61 ₂ are embedded in the transistor Qp ₂ p ⁺ -type drain region 55 ₂ and the It is connected to both ends of the gate electrodes 57 ₁ made of the first-layer polycrystalline silicon. The wiring for crossing 60 ₂ is formed by the same CVD.
-SiO ₂ film 59 ₁ via the contact hole 62 ₄ is opened and is connected to the transistor Qn ₂ of n ⁺ -type drain region 55 _4. By providing the intersecting wirings 60 ₁ and 60 ₂ made of the second layer n-type polycrystalline silicon, the other CM
The gate electrodes 57 ₂ of the transistors Qp ₂ and Qn ₂ forming the OS inverter are direct contacted with the drain region 55 ₃ of the transistor Qn ₁ forming one of the CMOS inverters, and the p ⁺ -type drain of the transistor Qp ₁ is formed. Area 55 ₁
Contact holes 62 _2, are cross-connected through the contact hole 62 ₁ and the crossing wiring 60 ₁ tungsten 61 ₁ is embedded, yet the gate electrode 57 ₁ of the transistor Qp _1, Qn ₁ constituting one of the CMOS inverter, the Drain region of transistors Qp ₂ and Qn ₂ that form the other CMOS inverter
A contact hole 62 ₃ , which is opened in 55 ₂ and 55 ₄ over the gate electrode 57 ₁ and the drain region 55 ₂ and in which a tungsten 61 ₂ is buried, a contact hole 62 ₄ and the intersecting wiring 60.
A flip-flop circuit in which the CMOS inverters are cross-connected to each other is realized by cross-connecting through ₂ .

Also, the transistor Qn as the transfer gate
₃ , Qn ₄ is an opening 63 and a second layer n provided in a portion of the first CVD-SiO ₂ film 59 ₁ corresponding to the channel region thereof as shown in FIGS. 1, 3, and 4. A gate electrode 64 made of polycrystalline silicon is provided. That is, one transistor Qn ₃ is and the drain region 55 ₃ and the source region of a common n ⁺ -type and a drain region 55 ₅ which are electrically separated from each other in the island region of the well 51, these source and drain regions (5
5 ₃ ), 55 ₅ across the island region of the well 51 of the opening 63 through the gate oxide film 65, and the phosphorus-doped second layer shared with the other transistor Qn ₄ The gate electrode 64 is made of n-type polycrystalline silicon. The other transistor Qn ₄ has an n ⁺ -type source region and drain region 55 ₆ common to the drain region 55 ₄ electrically isolated from each other in the island region of the well 51.
When these source and drain regions (55 _4), across through the gate oxide film on the island region of the well 51 of the opening 63 (not shown) including a channel region between 55 _6, the second layer n-type And a gate electrode 64 made of polycrystalline silicon. As shown in FIGS. 1 and 4, the gate electrode 64 made of the second layer n-type polycrystalline silicon has the first electrodes at the ends of the gate electrodes 57 ₁ and 57 _{2 made} of the first layer n-type polycrystalline silicon.
It is overlapped via the CVD-SiO ₂ film 59 _1.
The gate electrode 64 functions as a bit line WL.

Further, a second CVD-SiO ₂ film 59 _{2 serving} as a second interlayer insulating film is formed on the first CVD-SiO ₂ film 59 ₁ including the intersecting wirings 60 ₁ and 60 ₂ and the gate electrode 64. It is covered. This second
Al wirings 66 ₁ and 66 ₂ for V _SS power supply are provided on the CVD-SiO ₂ film 59 ₂ . The Al wirings 66 ₁ and 66 ₂ are connected to the first and second CVs.
D-SiO ₂ film 59 _1, 59 ₂ contact hole 62 which is opened over the _5, 62 ₆ the transistor Qn ₁ via, n ⁺ -type source region 54 of the Qn _{2 2,} 54 ₃ and the p ⁺ -type diffusion The regions 58 ₁ and 58 ₂ are respectively connected. Since the Al wirings 66 ₁ and 66 ₂ also serve as wirings of the adjacent memory cells, _one Al wiring is arranged in each memory cell. In addition, the second CVD
-Al wiring 67 ₁ as a bit line on the SiO ₂ film 59 ₂ ,
67 ₂ (BL ₁ , BL ₂ ) are arranged, and these Al wiring 67 ₁ ,
67 ₁ first, transistor Qn _3, the drain of Qn ₄ via a second CVD-SiO ₂ film 59 _1, 59 contact hole 62 ₇ which is open over a _2, 62 ₈ as the transfer gate Regions 55 ₅ and 55 ₆ are respectively connected. Incidentally, reference numeral 68 in the figure is a protective film coated on the entire surface.

Thus, according to the present invention, the gate electrode 57 ₁ of a pair of CMOS inverters other as shown in the FIG. 1-FIG. 4 CMO
S Inverter transistors Qp ₂ and Qn ₂ have p ⁺ -type and n ⁺ -type drain regions 55 ₂ and 55 _{4 respectively} , and the other CMOS inverter gate electrode 57 _{2 is connected} to one CMOS inverter transistor Q 2
The first CVD-S is used as the interconnections 60 ₂ and 60 ₁ for cross-connecting with the p ⁺ and n ⁺ -type drain regions 55 ₁ and 55 ₃ of p ₁ and Qn _1.
iO ₂ film 59 impurities giving was conductivity provided in _1, for example, phosphorus is formed by the second layer n-type doped polycrystalline silicon. Moreover, these wirings 60 ₁ and 60 ₂ are
_{In the connection} between the impurity (phosphorus) in ₁ , 60 ₂ and the p ⁺ type drain regions 55 ₁ , 55 ₂ having the opposite conductivity type, tungsten 6
1 ₁ and 61 ₂ are connected through buried contact holes 62 ₁ and 62 ₃ . As a result, the crossing wirings 60 ₁ and 60 _{2 made of} the second layer n-type polycrystalline silicon and the p ⁺ -type drain region 55.
_A good contact can be made without forming a pn junction between ₁ and 55 ₂ . The gate electrode 57 ₁ consisting of cross wires 60 _1, 60 ₂ and direct contactee gates electrodes 57 ₂ and the polycrystalline silicon consisting of a first layer n-type polycrystalline silicon of a second layer n-type polycrystalline silicon connecting and an n-channel MOS transistor Qn ₂ of n ⁺ -type drain region 55 ₄ with are the comrades containing impurities of the same conductivity type (p-type) to one another, can take a good ohmic contact . In this way, the first CVD-S
The cross wirings 60 ₁ and 60 ₂ arranged on the iO ₂ film 59 ₁ allow CMOS
Since the inverters can be cross-connected to each other, they are shown in FIGS.
Unlike the conventional memory cell shown in the figure, it is not necessary to provide Al wiring for cross-connecting a pair of CMOS inverters on the second interlayer insulating film (second CVD-SiO ₂ film), and the memory cell X On the memory cell that determines the pitch width in the direction
The margin of wiring can be increased. As a result, the Al wirings 66 ₁ and 66 ₂ for the V _SS power supply can be arranged on the second CVD-SiO ₂ film 59 ₂ together with the Al wirings 67 ₁ and 67 ₂ as bit lines. Thus V
_By forming the _SS power supply wirings 66 ₁ and 66 ₂ with Al,
As shown in FIG. 1, an n-channel MOS transistor Qn ₁ ,
Through the contact holes 62 ₅ , 62 ₆ over both the source regions 54 ₂ , 54 _{3 of} Qn ₂ and the p ⁺ -type diffusion regions 58 ₁ , 58 ₂ for well bias of the p-well 51 adjacent thereto. And connect well. That is, since the V _SS power source Al wirings 66 ₁ and 66 ₂ can also be used as well bias wirings, a well bias can be applied to each memory cell. Therefore, p
-Because it is possible to increase the bias point to the well 51 and effectively reduce the resistance of the well 51, the latch-up resistance can be remarkably improved.

Further, as in the conventional structure shown in FIGS. 6 to 8, it is not necessary to dispose the Al wiring for well bias in, for example, every 8 cells in an area different from the memory cell, so that the area of the memory itself is reduced. it can.

Further, by forming the second layer n-type polycrystalline silicon gate electrode 64 as a word line, the gate electrode 57 ₁ consisting of the first layer n-type polycrystalline silicon constituting each CMOS inverter to the gate electrode 64, 57 ₂ end and first CV
Since it is possible to overlap via the D-SiO ₂ film 59 _1, the case of forming the first layer n-type polycrystalline silicon and the gate electrode as a gate electrode and word lines constituting each CMOS inverter In comparison, the pitch width of the memory cells in the Y direction can be reduced. Moreover, the second CVD-SiO ₂ film 5
Above 9 ₂ is _one Al wiring 66 ₁ (or 66 ₂ ) for V _SS power supply,
Since there are a total of three Al wirings 67 ₁ and 67 ₂ as bit lines, and one Al wiring can be reduced as compared with the conventional memory cell, the pitch width of the memory cell in the X direction can be reduced. In fact, if the design rule is 1.5μm process,
The conventional memory cell shown in FIG. 6 has a pitch width in the X direction.
While the pitch width in the Y direction is 17.0 μm and 21.0 μm, the pitch width in the X direction is 15.5 μm and the pitch width in the Y direction can be remarkably reduced in the memory cell shown in FIG. 1 of the present invention.

Although tungsten is used as the metal to be buried in the contact hole in the above embodiment, a refractory metal selected from molybdenum, tantalum, platinum or the like may be used instead of tungsten.

In the above-mentioned embodiment, the structure in which the metal such as tungsten is buried only in the contact hole connecting the second layer n-type polycrystalline silicon and the p ⁺ -type drain region is connected. ^A metal may be buried in the contact hole connected to the ⁺ type drain region and the gate electrode made of the first layer n-type polycrystalline silicon.

In the above embodiment, the gate electrode of the first layer n-type polycrystalline silicon of one CMOS inverter is connected to the n-type and p-type drain regions of the other CMOS inverter as a means for cross-connecting the gate electrode of the n-type. Although the number of contacts between the intersecting wiring made of the second-layer n-type polycrystalline silicon and the drain region is reduced by making direct contact with the drain region, the present invention is not limited to this. For example, the wiring for crossing is n-type,
By connecting both p-type drain regions through contact holes and connecting the wiring to the gate electrode made of the first layer n-type polycrystalline silicon through the contact holes, a pair of CMOS inverters are cross-connected to each other. May be.

In the above-mentioned embodiment, the cross wiring made of the second-layer polycrystalline silicon doped with n-type impurities is used.
It is also possible to use a crossing wiring in which a p-type impurity, for example, boron is made of polycrystalline silicon. At this time, when the gate electrode of the CMOS inverter is formed of the first-layer n-type polycrystalline silicon, the intersecting wiring made of the second-layer p-type polycrystalline silicon, the n ⁺ -type drain region, and the first-layer n-type polycrystalline silicon At least a metal is buried in the contact hole connecting to the silicon gate electrode.

〔The invention's effect〕

As described in detail above, according to the present invention, the pitch widths of the memory cells in the X and Y directions and the memory itself can be miniaturized, and the latch-up withstand capability can be remarkably improved. Consequently, a highly integrated and highly reliable static A semiconductor storage device such as a memory can be provided.

[Brief description of drawings]

FIG. 1 is a plan view of a memory cell of a static memory showing an embodiment of the present invention, FIG. 2 is a sectional view taken along the line XX of FIG. 1, and FIG. 3 is a line YY of FIG. Sectional view, along the 4th
The figure is a sectional view taken along the line ZZ of FIG. 1, and FIG. 5 is a pair of CMs.
An equivalent circuit diagram of a 6-transistor type static memory having an OS inverter, FIG. 6 is a plan view showing a memory cell of a conventional static memory, and FIG. 7 is XX of FIG.
8 is a sectional view taken along the line YY of FIG. 6, FIG. 9 is a schematic view of a CMOS structure for explaining the latch-up phenomenon, and FIG. 10 is a thyristor of FIG. An equivalent circuit diagram of the effect, FIG. 11 is a plan view showing a memory cell of another conventional static memory, FIG. 12 is a sectional view taken along line XX of FIG. 11, and FIG. 13 is Y of FIG. It is sectional drawing which follows the -Y line. Qp ₁ , Qp ₂ ... p-channel MOS transistor, Qn ₁ , Q
n ₂ , Qn ₃ , Qn ₄ ... n-channel MOS transistor, 51 ...
... p-well, 52 ... n-type silicon substrate, 53 ... field oxide film, 54 ₁ , 54 ₂ , 54 ₃ ... source region, 55 ₁ , 5
5 ₂ , 55 ₃ , 55 ₄ , 55 ₅ , 55 ₆ ... Drain region, 57 ₁ , 57 ₂ ...
... First layer gate electrode made of n-type polycrystalline silicon, 5
8 ₁ , 58 ₂ ...... p ⁺ type diffusion region for well bias, 59 ₁ ……
First CVD-SiO ₂ film (first interlayer insulating film), 59 ₂ ...... Second
CVD-SiO ₂ film (second interlayer insulating film), 60 ₁ , 60 ₂ ... Crossing wiring made of second layer n-type polycrystalline silicon, 61 ₁ , 61 ₂
...... Tungsten, 62 _{1 to} 62 ₈ ...... Contact hole, 64
...... Second layer gate electrode (word line) made of n-type polycrystalline silicon, 66 ₁ , 66 ₂ ...... Al wiring for V _SS power supply, 67 ₁ , 6
7 ₂ ...... Al wiring as a bit line.

Claims (5)

[Claims] 1. A pair of CMOS inverters, one CMOS
A flip-flop circuit formed by connecting the gate electrode of the inverter to the drain region of each transistor of the other CMOS inverter through wiring, and a pair of transfer MOS transistors connected to each node of the flip-flop circuit. In a semiconductor memory device in which memory cells composed of, are integrated in a matrix on a semiconductor substrate, the gate electrode of the CMOS inverter is formed of a first-layer polycrystalline silicon containing an impurity imparting conductivity, The wiring is formed of a second-layer polycrystalline silicon containing an impurity imparting conductivity, which is disposed on the first-layer interlayer insulating film that covers the gate electrode, is opened in the interlayer insulating film, and the wiring and the wiring. At least a metal is buried in the contact hole that connects the impurity inside and the drain region of the opposite conductivity type. The gate electrode of the transfer MOS transistor, the semiconductor memory device characterized by being formed by a second layer polycrystalline silicon containing impurities giving the conductivity. 2. Impurities in the first-layer polycrystalline silicon are changed to second impurities.
The semiconductor memory device according to claim 1, wherein the semiconductor memory device has the same conductivity type as impurities in the layer polycrystalline silicon. 3. The semiconductor memory device according to claim 2, wherein the impurities in the polycrystalline silicon of the first layer and the polycrystalline silicon of the second layer are n-type. 4. A semiconductor memory device according to claim 1, wherein the metal is a refractory metal selected from tungsten, molybdenum, tantalum and platinum. 5. A metal wiring as one power source is provided on a second layer interlayer insulating film covering a wiring made of the second layer polycrystalline silicon, and the metal wiring is provided as a source region of one CMOS inverter and its source. 2. The semiconductor memory device according to claim 1, wherein both the source region for biasing the substrate region in which the region is formed and the diffusion region of opposite conductivity type are connected through contact holes.