JPH0535616B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a clock signal phase synchronization technique in digital signal transmission.

(Background of the Invention) In high-efficiency digital signal transmission, code transmission is performed using pulses shaped into a small roll-off waveform, so a sample timing shift on the receiving side will rapidly deteriorate the characteristics. Conventionally, sample timing, or clock signal extraction, involves rectifying an input signal to generate a clock component, and then extracting the clock through a narrowband bandpass waver. That is, in the past, clock extraction was performed using analog circuits, which required adjustment of circuit elements, which often required time and effort for inspection and maintenance.

In recent years, receivers have become increasingly digital, and the need for digital processing for clock signal extraction has increased. For digitizing receivers, direct control of sample timing is preferred rather than extraction of the clock signal.

(Object of the Invention) An object of the present invention is to provide a clock phase error detector suitable for digital processing and realizing simple sample timing control.

(Structure of the Invention) According to the present invention, there is provided a clock phase error detector for detecting a phase error of a clock signal, which includes: (a) a first sampler that samples an input signal at the zero phase of the clock signal; (b) a second sampler that samples the input signal at the π phase of the clock signal; (c) a discriminator that identifies the output of the first sampler as a code; and (d) a value of the output of the discriminator two cycles before and the current time. a detector that outputs a detection signal when the values at the output of the second sampler match and the value at the current time is different from the value at the current time; an amplitude difference detector that detects an amplitude difference between the value of There is obtained a clock phase error detector comprising at least the following: means for outputting the multiplied value as a clock phase error only when a detection signal is output.

(Principle of the Invention) Next, the present invention will be described in detail with reference to the drawings.

Figure 1 a is a binary digital signal of +1 and -1,
Alternatively, it is a diagram showing an eye pattern of a real part or an imaginary part of a demodulated signal of a quadrature phase modulated wave. Figure b shows the sample timing.
The time per clock period (T seconds) indicated by the arrow corresponds to the widest eye opening time of the eye pattern. In the following, this timing will be referred to as signal detection timing. c in the same figure is the previous b
This shows the timing phase shifted by π phase (180°). Hereinafter, this timing will be referred to as clock phase detection timing. At this timing, the first
When the waveform in Figure a is sampled, it takes three types of values: a value of ±1 when the transmission code does not change before and after that, and a value near zero when it changes conversely. The waveform in Figure 1a depends on the roll-off rate of the transmitted pulse and the bit pattern, but it is approximately the same as the second one.
Even if it is simplified as shown in Figure a, there is no problem on average. First, let's consider signal changes as indicated by the thick line in FIG. 2a. This change means that the transmission code is ±1,
This is a case where -1, +1, -1 are alternately repeated and transmitted. Figures b and c show the signal detection timing and clock phase detection timing, respectively. If the former is delayed by T _e seconds, the width of the eye pattern will narrow from W ₀ to W ₁ . Next, let us consider the magnitude of the signal sampled at two successive clock phase detection timings. When T _e =0 in Figure 2c,
The two sample values are 1000 and 1001, which are the same value. On the other hand, if T _e ≠ 0 and T _e < 0 (i.e. sample delay), the two sample values are 1002.
1003, and the difference between the two is non-zero. Also, T _e ＞
When it is 0, it becomes 1004 and 1005, and the difference between them is also non-zero, and the polarity is opposite to that when T _e <0. If we take advantage of this, we can first make a signal transition (-
It can be seen that the polarity and magnitude of T _e can be estimated by extracting the values (1, +1, -1) and finding the difference between the sample values at the clock phase detection timings before and after that time. Here again, if the signal transition is a thick line
If the thin line 2001 is used instead of 2000, (the signal transition is +1, -1, +1), the polarity of the difference between the sample values before and after the clock phase detection timing with respect to T _e will be opposite to that in the previous example. In practice, the signal transition (-1,
+1, -1) and (+1, -1, +1) can provide more phase difference information as a clock phase difference detector, so it is better to use both. , the object of the present invention can be achieved even if only one of them is used. In the following, only the case where both are used will be described. The phase difference information, that is, the difference between the sample values of (1000, 1001) and the difference between the sample values of (1004, 1005), and the sample value at the signal detection timing between those samples (+1 or -1 in this case). need to be hung. In Figure 2, the thick line 2000 indicates the signal transition (-
1, +1, -1), the polarity (+1) of the sample value 1006 at the signal detection timing is reversed to the difference between the two sample values (1000, 1001) or (1004, 1005) at the clock phase detection timing. In the case of a thin line signal transition (+1, -1, +1), it is necessary to multiply the polarity (-1) of the sample value 1007 at the signal detection timing. The above is the principle of clock phase detection.

In the explanation so far, the signal transition of the input signal is +
In the above case, the input is periodically repeated as 1, -1, +1, -1, but of course there is no problem even if the input is general data. That is, among the random signal transitions (+1, -1, +1) and (-1, +1, -
Clock phase detection is performed by selectively extracting only the transitions in (1).

(Embodiment) FIG. 3 is a block diagram of an embodiment of the present invention. In the figure, 1 is the first sampler, 2 is the second sampler, 3 is a discriminator for identifying the code of the output of the first sampler, 4 is a detector, and delay circuits 40 and 41 with a signal transmission period T and an adder 42 and absolute value circuit 44
If the value of the output (±1) of the discriminator 3 two cycles before and the current value are equal, 2 is output, and if they are different, 0 is output. On the other hand, the subtracter 43 outputs 2 if the value one cycle before and the current value are different, and outputs 0 if they are the same. In order for the output of the AND gate 46 to become a high level H,
The value of the discriminator output two cycles ago and the current value are equal,
It can also be seen that this is limited to cases where the value one cycle ago and the current value are different. 5 is an amplitude detector and the previous 40,
The difference between the input and output of the delay circuit 50, which is the same as 41, is subtracted by the subtracter 51.
It is detected by 6 multiplies the output of the amplitude etc. detector by obtaining the polarity of the output of the first sampler one period before from the output of the delay circuit 40 of block 4.

7 is a multiplier for guiding the output of the multiplier 6 to the terminal 101 only when the output of the detector 4 becomes "H". Note that the sample timing of the first and second samplers is supplied by a clock oscillator 8 and a T/2 delay circuit 9, and the signal detection timing is supplied to the first sampler, and the clock phase detection timing is supplied to the second sampler. be done.

Since a clock phase difference signal is output from the terminal 101, the output is smoothed by an appropriate reduction filter and supplied to the clock oscillator 8, thereby controlling the clock phase (clock frequency). .

(Effects of the Invention) According to the present invention, clock phase control can be easily performed using only a small number of digital elements.

[Brief explanation of drawings]

Fig. 1 is a diagram for explaining a binary data transmission waveform, Fig. 2 is a diagram for explaining the principle of extracting clock phase difference information, and Fig. 3 is a block diagram showing an embodiment of the present invention. It is. In the figure, 1...first sampler, 2...second sampler, 3...discriminator, 4...detector, 5...amplitude difference detector, 6...multiplier are shown, respectively.

Claims (1)

[Claims] 1. A clock phase error detector for detecting a phase error of a clock signal of a received digital signal (input signal), comprising: (a) a first sampler that samples the input signal at the zero phase of the clock signal; (b) a second sampler that samples the input signal at the π phase of the clock signal; (c) a discriminator that identifies the code of the output of the first sampler; (d) a second sampler that samples the input signal at the π phase of the clock signal; a detector that outputs a detection signal when the value at the current time matches the value at the current time and the value at the current time differs from the value one cycle before; (e) the value at the output of the second sampler one cycle before; an amplitude difference detector that detects the amplitude difference between the value at the current time and the value at the current time; A clock phase error detector comprising at least the following: means for outputting the multiplied value as a clock phase error only when the detector outputs a detection signal.