JPH0535617B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) This invention relates to clock signal phase synchronization in digital signal transmission.

(Background of the Invention) In high-efficiency digital signal transmission, code transmission is performed using pulses shaped into a small roll-off waveform, so a sample timing shift on the receiving side will rapidly deteriorate the characteristics. Conventionally, sample timing, or clock signal extraction, involves rectifying an input signal to generate a clock component, and then extracting the clock through a narrowband bandpass waver. That is, in the past, clock extraction was performed using analog circuits, which required adjustment of circuit elements, which often required time and effort for inspection and maintenance.

Furthermore, in recent years, receivers have become increasingly digital, and the need for digital processing for extracting clock signals has increased. In the case of digitizing receivers, rather than extracting the clock signal, sample
A method that directly controls timing is suitable.

(Object of the Invention) An object of the present invention is to provide a clock phase error detector suitable for digital processing and realizing simple sample timing control.

(Structure of the Invention) According to the present invention, there is provided a clock phase error detector for detecting a phase error of a clock signal of a received complex signal (input signal), which comprises: (a) detecting the input clock signal at zero phase of the clock signal; The first sample samples either the real part or the imaginary part of the signal.
(b) a third sampler that samples either the real part or the imaginary part of the input signal at the π phase of the clock signal;
a sampler, (c) a first discriminator that discriminates the code of the output of the first sampler, and a second discriminator that discriminates the code of the output of the second sampler; (d) the first and second discriminators; The discriminator output is equal to its value at the current time and its value two clock cycles ago, and
and the value of the first discriminator output at the current time and 1
a detection means for outputting a detection signal when the value before the clock cycle is different; (e) the value at the current time of the third sampler output and 1;
an amplitude difference detector for detecting an amplitude difference with a value one clock period before; (f) a value obtained by multiplying the output of the amplitude difference detector by the polarity of the value of the first sampler output one clock period before; A clock phase error detector is obtained, comprising at least the following: means for outputting the multiplied value as a clock phase error only when the detection means outputs a detection signal.

(Principle of the Invention) Next, the present invention will be described in detail with reference to the drawings.

Figure 1 a is a binary digital signal of +1 and -1,
Alternatively, it is a diagram showing an eye pattern of a real part or an imaginary part of a demodulated signal of a quadrature phase modulated wave. Figure b shows the sample timing.
The time per clock period (T seconds) indicated by the arrow corresponds to the widest eye opening time of the eye pattern. Hereinafter, this timing will be referred to as signal detection timing. In the figure, c shows a timing phase that is shifted from the previous b by a π phase (180°). In the following, this timing will be referred to as clock phase detection timing. When the waveform shown in Figure 1a is sampled at this timing, there are three types of values: a value of ±1 obtained when the transmission code does not change before and after that, and a value near zero obtained when it changes conversely. Takes a value. The waveform in Figure 1a is
Although it depends on the roll-off rate of the transmitted pulse and the bit pattern, on average there is no problem even if it is treated in a simplified manner as shown in FIG. 2a. First, let's examine signal changes as shown by the bold line in Figure 2a.
This change occurs when the transmission code is alternately repeated as +1, -1, +1, -1. Figure b,
c indicates the signal detection timing and the clock phase detection timing, respectively, and if the former is sent for T _e seconds, the width of the eye pattern will narrow from W _p to W ₁ . Next, let us consider the magnitude of the signal sampled at two successive clock phase detection timings. Second
When T _e = 0 in figure c, the two sample values are 1000
and 1001, which have the same value. On the other hand, T _e
If ≠0 and T _e <0 (that is, sample delay), the two sample values are 1002 and 1003, and the difference between them is non-zero. Also, when T _e > 0, the difference between them becomes 1004 and 1005, which is also non-zero, and the polarity is
This is the opposite of the case when T _e < 0 (.If you use this fact, first the thick line 2 in Figure 2a is detected at the signal detection timing.
By extracting signal transitions such as 000 (-1, +1, -1) and finding the difference between the sample values at the clock phase detection timings before and after that time,
The polarity and magnitude of T _e can be estimated. Here too,
If the signal transition is a thin line 2001 instead of the thick line 2000 (the signal transition is +1, -1, +1), the polarity of the difference between the sample values before and after the clock phase detection timing with respect to T _e is opposite to the previous example. become. Signal transition (-1, +1, -1) and (+1, -1, +1)
However, as a clock phase difference detector, it can provide more phase difference information, so if you decide to use both of them (however, it is also possible to use only one of them). , that is, it is necessary to multiply the difference between the sample values of (1000, 1001) and the sample values of (1004, 1005) by the sample value at the signal detection timing between those samples (+ or -1 in this case). There is.
In Figure 2, the signal transitions indicated by the thick line 2000 (-1, +1, -
In the case of 1), the two sample values (1000, 1001) or (1004,
1005) sample value at the signal detection timing
The polarity (+1) of 1006 is reversed by the thin line signal transition (+
1, -1, +1), it is necessary to multiply the polarity (-1) of the sample value 1007 at the signal detection timing. The above is the principle of clock phase detection.

In the explanation so far, the signal transition of the input signal is +1,
Although this was a case where the data were changed periodically from -1 to +1 to -1, there is of course no problem even if the input is general data. Among those random signal transitions (+
Clock phase detection is performed by selectively extracting only the transitions (1, -1, +1) and (-1, +1, -1).

FIG. 3 is a block diagram showing an example of a clock phase error detector for (actual input) baseband data using this principle. In the figure, 1 is the first sampler, 2 is the third sampler (the one that samples the imaginary part of the second sampler input signal is not needed in this example), and 3 is the first sampler that identifies the code of the output of the first sampler. A discriminator (the second discriminator is also unnecessary in this embodiment, as is the second sampler) 4 is a detector, delay circuits 40 and 41 with a signal selection period T, an adder 42, and an absolute value circuit 44 constitute a discriminator 3. Output (±
If the value of 1) two cycles ago is equal to the current value, 2 is output, and if they are not different, 0 is output. On the other hand, the subtracter 43 outputs 2 if the value one cycle before and the current value are different, and outputs 0 if they are the same. As a result, the output of the AND circuit 46 becomes a high level (H) only when the value of the discriminator output from two cycles ago is equal to the current value, and the value from one cycle before is different from the current value. I know that it will happen.

Reference numeral 5 denotes an amplitude difference detector which detects the input/output difference of the delay circuit 50, which is the same as 40 and 41 above, by means of a subtracter 51.

6 is a delay circuit 4 of block 4 which sets the polarity of the output of the first sampler one cycle before to the output of the amplitude difference detector.
It is obtained from the output of 0 and multiplied.

7 is a multiplier for guiding the output of the multiplier 6 to the terminal 101 only when the output of the detector 4 becomes "H". The sample timing of the first and second samplers is determined by the clock oscillator 8 and the T/2 delay circuit 9, and the signal detection timing is determined by the first sampler and the clock phase detection timing is determined by the second sampler. Supplied.

Since a clock phase difference signal is output from the terminal 101, the clock phase (clock frequency) is controlled by appropriately smoothing the output with a reduction filter and supplying it to the clock oscillator 8.

In addition to the baseband signal of the data transmission waveform, the input signal may be either the real part or the imaginary part of the complex baseband signal (for example, the in-phase baseband signal of a 4-phase PSK signal). In this case, it is necessary to consider the existence of carrier phase error. Figure 4 a and b represent the four signal points 300, 301, 302, and 303 of the 4-phase PSK, where a is the transition to the signal points 300, 302, and 300, and b is the signal point 300, 302. , 303. FIG. 5 shows a case where the four signal points in FIG. 4 are each rotated by about 20 degrees in the time direction. FIG. 5a corresponds to FIG. 4a, and FIG. 5b corresponds to FIG. 4b.

FIG. 6 shows changes in the in-phase component (I coordinate side of the I coordinate and Q coordinate) during the signal point transition shown in FIGS. 4 and 5. First, the observed values 500, 501, 502 connected by broken lines in Figure 6a are the observed values 500', 501' connected by solid lines in Figure 4a,
502' corresponds to FIG. 5a. Although the amplitudes of the two are different, the symmetry of their waveforms is maintained. On the other hand, the observed value 5 connected by the broken line in Figure 6b
00, 501, 502 correspond to FIG. 4b, which corresponds to 500, 501, 502 in FIG. 6a. That is, since the I and Q components are completely independent signals, a change on the Q side will not affect the I side unless there is transmission distortion. On the other hand, observation points 500'', 501'', and 50 connected by solid lines in Figure 6b
2'' has a carrier phase error, so (IcosQ _e +QsinQ _e ) appears as the I component.Therefore, as the I component, (+1, -1,
500', 501, and 502'' become asymmetrical due to the influence of the Q component, which changes asymmetrically (+1, -1, -1), even though they change symmetrically with +1). This shows that the principle of clock phase difference information extraction explained using Fig. 2 cannot be used.In order to extend and utilize this principle, the signal point transition is shown in Fig. 4. 3 like a
00,302,300 or 301,303,3
It is necessary to extract only those such as 01 in which both the I and Q components change symmetrically.

In this way, the problems caused by the carrier phase error described above can be solved.

(Embodiment) FIG. 7 is a diagram showing a block diagram of an embodiment of the present invention.

In the figure, the same reference numerals as in FIG. 3 are the same as the components with the same numbers in FIG.
The difference from the configuration in FIG. 3 is that in addition to the change in the I component from the terminal 100, it is also necessary to detect the change in the Q component from the terminal 110, and for this purpose, the same sampler and discriminator as in 1 and 3 are used. , it is necessary to change the configuration of the detector 4 so as to add a function to detect that the change in the Q component is also symmetrical. 4' is a new detector for this purpose, but there is a third
Block 4 in the figure is included as a component and is connected to the outside through terminals 105 and 102. Now, in order to detect the symmetry of signal changes on the Q side, delay circuits 47 and 48, an adder 49, and an absolute value circuit 50 are used. Q side is (+1, -1, +
1) or (-1, +1, -1), the absolute value circuit 44 of block 4 in FIG.
Similarly, 2 is output, and in other cases, 0 is output. This output and the output from the conventional block 4 are ANDed in an AND circuit 51, and as shown in FIG.
The output of the detector 4' reaches a high level (H) only when the signal point transitions occur symmetrically for both I and Q components as shown in
become. This high level signal is led to the multiplier 7, and only the correct clock phase difference information is sent to the output terminal 1.
It plays the role of supplying to 01.

In the above explanation, the principle explained using Fig. 2 is mainly applied to the real part of a complex signal, and an example in which the imaginary part signal is also used to overcome the clock phase error problem will be explained. However, since the real part and imaginary part of a complex signal can be arbitrarily selected on the receiving side, it is clear from the above explanation that it is also possible to implement the present invention by exchanging the real part and imaginary part. It is.

(Effects of the Invention) According to the present invention, clock phase control of complex signal data can be easily performed using only a small number of digital elements.

[Brief explanation of the drawing]

Figure 1 is a diagram for explaining the binary data transmission waveform, Figure 2 is a diagram for explaining the principle of extracting clock phase difference information, and Figure 3 is a diagram for explaining the clock position relative to the (actual signal) baseband signal. The configuration diagram of the phase difference detector, Figures 4 and 5 are diagrams showing the signal point changes of the four-phase phase modulated wave in two cases: without and with carrier phase difference. FIG. 7 is a block diagram showing an embodiment of the present invention. FIG. In the figure, 1...first sampler, 1'...second sampler, 2...third sampler, 3...first discriminator, 3'...second discriminator, 4'... …Detector,
5... An amplitude difference detector, 6... A multiplier, respectively.

Claims (1)

[Scope of Claims] 1. A clock phase error detector for detecting a phase error of a clock signal of a received complex signal (input signal), comprising: (a) detecting the real part of the input signal at the zero phase of the clock signal; , the first to sample either one of the imaginary parts
(b) a third sampler that samples either the real part or the imaginary part of the input signal at the π phase of the clock signal;
a sampler, (c) a first discriminator that discriminates the code of the output of the first sampler, and a second discriminator that discriminates the code of the output of the second sampler; (d) the first and second discriminators; The discriminator output is equal to its value at the current time and its value two clock cycles ago, and
and the value of the first discriminator output at the current time and 1
a detection means for outputting a detection signal when the value before the clock cycle is different; (e) the value at the current time of the third sampler output and 1;
an amplitude difference detector for detecting an amplitude difference with a value one clock period before; (f) a value obtained by multiplying the output of the amplitude difference detector by the polarity of the value of the first sampler output one clock period before; A clock phase error detector comprising at least the following: means for outputting the multiplied value as a clock phase error only when the detection means outputs a detection signal.