JPH0536396B2 - - Google Patents
Info
- Publication number
- JPH0536396B2 JPH0536396B2 JP11781887A JP11781887A JPH0536396B2 JP H0536396 B2 JPH0536396 B2 JP H0536396B2 JP 11781887 A JP11781887 A JP 11781887A JP 11781887 A JP11781887 A JP 11781887A JP H0536396 B2 JPH0536396 B2 JP H0536396B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- temperature
- molecular beam
- interface
- epitaxial growth
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000000758 substrate Substances 0.000 claims description 31
- 238000000034 method Methods 0.000 claims description 17
- 238000001451 molecular beam epitaxy Methods 0.000 claims description 11
- 239000013078 crystal Substances 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims 1
- 230000001678 irradiating effect Effects 0.000 claims 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 12
- 239000004065 semiconductor Substances 0.000 description 7
- 239000012535 impurity Substances 0.000 description 5
- 150000001875 compounds Chemical class 0.000 description 4
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 3
- 125000004429 atom Chemical group 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000002052 molecular layer Substances 0.000 description 3
- 239000002994 raw material Substances 0.000 description 3
- 238000001228 spectrum Methods 0.000 description 3
- 108010083687 Ion Pumps Proteins 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000000295 emission spectrum Methods 0.000 description 2
- 125000005842 heteroatom Chemical group 0.000 description 2
- 238000000103 photoluminescence spectrum Methods 0.000 description 2
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000005424 photoluminescence Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 230000005533 two-dimensional electron gas Effects 0.000 description 1
Landscapes
- Crystals, And After-Treatments Of Crystals (AREA)
- Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
Description
【発明の詳細な説明】
(産業上の利用分野)
本発明は、ヘテロ界面の形成方法に関し、特に
分子線エピタキシ法によつて化合物半導体の高品
質なヘテロ界面を形成する方法に関する。DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a method for forming a heterointerface, and particularly to a method for forming a high quality heterointerface of a compound semiconductor by molecular beam epitaxy.
(従来の技術)
2次元電子ガストランジスタや量子井戸レーザ
のような化合物半導体のデバイスは、その多くが
異種の半導体結晶が接合したヘテロ接合を利用す
るものである。ヘテロ接合界面(以下、ヘテロ界
面と記す)の性質はキヤリアの散乱や、発光、吸
収等に影響し、デバイス特性を大きく左右する。
従つて、平坦かつ急峻で、不純物や欠陥のない高
品質の界面を形成することが重要である。急峻な
ヘテロ界面を形成する手段として分子線エピタキ
シ(Molecular Beam Epitaxy、以下MBEとい
う)法が広く行なわれている。(Prior Art) Most compound semiconductor devices such as two-dimensional electron gas transistors and quantum well lasers utilize heterojunctions in which different types of semiconductor crystals are joined. The properties of the heterojunction interface (hereinafter referred to as heterointerface) affect carrier scattering, light emission, absorption, etc., and greatly influence device characteristics.
Therefore, it is important to form a high-quality interface that is flat, steep, and free of impurities and defects. Molecular beam epitaxy (hereinafter referred to as MBE) is widely used as a means of forming steep hetero-interfaces.
第2図にMBE装置の概略断面図を示す。MBE
法はイオンポンプ等の真空ポンプ9によつて超高
真空に保たれた成長室1中に、所望の結晶を構成
する元素を含む原料を加熱し分子線状に噴出させ
る分子線源20,21,22と、この分子線源2
0,21,22とは独立に温度制御可能な基板ホ
ルダー3とを設け、分子線源20,21,22か
ら基板4に向けて原料元素の分子線を噴出させて
エピタキシヤル成長を行なうものである。MBE
法では、シヤター5の開閉により個々の分子線の
断続並びに蒸発源の温度設定により分子線強度の
変調制御を行うことができる。 Figure 2 shows a schematic cross-sectional view of the MBE device. M.B.E.
The method uses molecular beam sources 20 and 21 that heat raw materials containing elements constituting a desired crystal and eject them in the form of molecular beams in a growth chamber 1 maintained at an ultra-high vacuum by a vacuum pump 9 such as an ion pump. , 22 and this molecular beam source 2
A substrate holder 3 whose temperature can be controlled independently of the substrates 0, 21, and 22 is provided, and molecular beams of raw material elements are ejected from molecular beam sources 20, 21, and 22 toward the substrate 4 to perform epitaxial growth. be. M.B.E.
In this method, the molecular beam intensity can be modulated and controlled by opening and closing the shutter 5 to intermittent individual molecular beams and by setting the temperature of the evaporation source.
従来原子のオーダーで平坦かつ急峻なヘテ界面
を形成する方法としてMBE成長中にシヤツター
5を閉じることで成長を界面で中断し、数十秒な
いし数分間待機することにより界面の平坦性を増
す方法がGaAs/AlGaAsヘテロ系について報告
されている(ジヤパニーズ・ジヤーナル・オフ・
アプライド・フイジツクス、(Jpn.J.Phys.24
(1985)L417頁)。この方法では、待機中に基板
表面の原子が表面を動きまわり、表面に存在する
ステツプやキンクに捉えられ次第に大きな島を形
成する。良く制御されたGaAsとAlGaAsのヘテ
ロ成長のMBEでは、界面の遷移領域の幅は、1
分子層である。このため、界面には、高さが1分
子層厚の極めて平坦な島が形成される。 A conventional method for forming a flat and steep interface on the order of atoms is to interrupt the growth at the interface by closing the shutter 5 during MBE growth, and wait for several tens of seconds to several minutes to increase the flatness of the interface. has been reported for the GaAs/AlGaAs hetero system (Japanese journal off.
Applied Physics, (Jpn.J.Phys.24
(1985) page L417). In this method, atoms on the substrate surface move around on the surface during waiting, are captured by steps and kinks on the surface, and gradually form larger islands. In the well-controlled MBE of GaAs and AlGaAs heterogrowth, the width of the interface transition region is 1
It is a molecular layer. Therefore, extremely flat islands with a height of one molecular layer thick are formed at the interface.
(発明が解決しようとする問題点)
しかしながら、成長を中断し、待機している間
には、基板表面に成長室1中に存在する不純物が
吸着してしまう。このため、このようにして界面
を平坦化して形成したGaAsとAlGaAsからなる
半導体素子、例えば量子井戸を用いて発光素子を
形成する場合に、発光スペクトル幅は狭まるもの
の、発光効率が低下してしまう問題がある。(Problems to be Solved by the Invention) However, while the growth is interrupted and the growth is on standby, impurities present in the growth chamber 1 are adsorbed onto the substrate surface. For this reason, when forming a light emitting device using a semiconductor device made of GaAs and AlGaAs formed by flattening the interface in this way, such as a quantum well, the emission spectrum width is narrowed, but the luminous efficiency is reduced. There's a problem.
本発明の目的はこの問題点を解決した高品質ヘ
テロ界面の形成方法を提供することにある。 An object of the present invention is to provide a method for forming a high-quality heterointerface that solves this problem.
(問題点を解決するための手段)
本発明の界面形成方法は、所望の結晶を構成す
る元素を含む分子線を温度に保持した基板上に堆
積させる分子線エピタキシ成長において、第1の
化合物半導体結晶を堆積させる第1のエピタキシ
ヤル成長工程と、該第1のエピタキシヤル成長を
中止して前記基板の温度を前記第1のエピタキシ
ヤル成長工程の場合より高く保持して待機する待
機工程と、続いて該基板の温度を該待機工程より
低い温度に保持して第2の化合物半導体結晶を堆
積させる第2のエピタキシヤル成長工程を備えて
いる点に特徴がある。(Means for Solving the Problems) The interface forming method of the present invention is a method for forming a first compound semiconductor in molecular beam epitaxy in which molecular beams containing elements constituting a desired crystal are deposited on a substrate kept at a temperature. a first epitaxial growth step in which crystals are deposited; a standby step in which the first epitaxial growth is stopped and the temperature of the substrate is held higher than in the first epitaxial growth step; The method is characterized in that it subsequently includes a second epitaxial growth step in which a second compound semiconductor crystal is deposited while maintaining the temperature of the substrate at a lower temperature than in the standby step.
(作用)
この界面形成方法は、界面での待機中に基板温
度を成長中より上げることで原子の表面拡散速度
を増大させるので平坦化に要する時間が減り、不
純物の吸着量の低減される。また、基板温度を高
くすることにより不純物の表面への吸着確率その
ものが低減される。(Function) This interface formation method increases the surface diffusion rate of atoms by raising the substrate temperature during standby at the interface compared to during growth, thereby reducing the time required for planarization and reducing the amount of impurities adsorbed. Furthermore, by increasing the substrate temperature, the probability of impurities being adsorbed onto the surface itself is reduced.
(実施例)
以下、図面を参照しながら本発明の実施例を説
明する。第1図aは、本発明の界面形成方法を、
基板温度の時間変化のグラフとして表した図、第
1図bは本発明により形成した量子井戸の77kで
のフオトルミネツセンス(以下、PLという)ス
ペクトルである。第2図は、本発明に用いる
MBE装置の概略断面図である。(Example) Hereinafter, an example of the present invention will be described with reference to the drawings. FIG. 1a shows the interface forming method of the present invention,
FIG. 1b, which is a graph of the change in substrate temperature over time, is a photoluminescence (hereinafter referred to as PL) spectrum at 77K of a quantum well formed according to the present invention. Figure 2 is used in the present invention.
FIG. 2 is a schematic cross-sectional view of the MBE device.
ここでは、GaAs基板上に、Al0.5Ga0.5Asバリ
ア層でGaAs量子井戸を挟んだ量子井戸構造を形
成する例について述べる。第2図のMBE装置の
概略の構成については既に説明した。分子線源2
0にはGa、21にはAl、22にはAsが原料とし
て充填される。まず通常の方法により有機洗浄
し、化学的エツチングにより清浄化したGaAs
(100)基板4が10-10Torrに排気された成長室1
中の基板ホルダー3に装着される。 Here, we will describe an example in which a quantum well structure is formed on a GaAs substrate, with a GaAs quantum well sandwiched between Al 0.5 Ga 0.5 As barrier layers. The general configuration of the MBE device shown in FIG. 2 has already been described. Molecular beam source 2
0 is filled with Ga, 21 with Al, and 22 with As as raw materials. GaAs was first organically cleaned using conventional methods and cleaned by chemical etching.
(100) Growth chamber 1 with substrate 4 evacuated to 10 -10 Torr
It is attached to the board holder 3 inside.
成長に先立ち、GaおよびAl分子線源20,2
1は、所望のAl0.5Ga0.5Asの組成を得るべく温度
設定し、As分子線源22もおよそ1×10-5Torr
の分子線強度がGaAs基板1の位置で得られるよ
うに温度設定する。As分子線源22の前方のシ
ヤツター5をAs分子線をGaAs基板4に照射しつ
つ、基板ホルダー3内蔵のヒーターの温度設定を
上げAs圧下でGaAs基板4の表面を熱クリーニン
グする。通常580゜で表面の酸化膜が脱離し、表面
が清浄となる。基板温度を600℃で安定に制御さ
せ、GaとAlの分子線源20,21の前方のシヤ
ツター5を開けAl0.5Ga0.5Asのバリア層を成長
(第1のエピタキシヤル成長)させる。成長層厚
は0.5μmとした。 Prior to growth, Ga and Al molecular beam sources 20,2
1, the temperature is set to obtain the desired composition of Al 0.5 Ga 0.5 As, and the As molecular beam source 22 is also set at approximately 1×10 -5 Torr.
The temperature is set so that a molecular beam intensity of 1 is obtained at the position of the GaAs substrate 1. While the shutter 5 in front of the As molecular beam source 22 is used to irradiate the GaAs substrate 4 with As molecular beams, the temperature setting of the heater built into the substrate holder 3 is raised to thermally clean the surface of the GaAs substrate 4 under As pressure. Normally, at 580 degrees, the oxide film on the surface is removed and the surface becomes clean. The substrate temperature is stably controlled at 600° C., the shutter 5 in front of the Ga and Al molecular beam sources 20 and 21 is opened, and a barrier layer of Al 0.5 Ga 0.5 As is grown (first epitaxial growth). The growth layer thickness was 0.5 μm.
次に、GaとAlのシヤツター5を閉じて成長を
中断し、同時に基板ホルダー3のヒーターの温度
設定を680℃に上げてそのままAs照射下で10秒間
待機(待機工程)する。 Next, the Ga and Al shutters 5 are closed to interrupt the growth, and at the same time, the temperature setting of the heater of the substrate holder 3 is raised to 680° C., and the substrate is left under As irradiation for 10 seconds (standby step).
次に、基板温度を再び600℃に設定し、同時に、
Ga分子線源20の前方のシヤツター5を開けて
GaAsを約28Å(約10分子層)成長(第2のエピ
タキシヤル成長工程)する。これで量子井戸の片
側のヘテロ界面が形成された。 Next, set the substrate temperature to 600℃ again, and at the same time,
Open the shutter 5 in front of the Ga molecular beam source 20.
GaAs is grown to about 28 Å (about 10 molecular layers) (second epitaxial growth step). This forms a heterointerface on one side of the quantum well.
ついで、再びGaのシヤツター5を閉じて成長
を中断し、基板温度を680℃にし、基板4にAsの
みを照射して10秒間待機する(待機工程)。 Then, the Ga shutter 5 is closed again to interrupt the growth, the substrate temperature is set to 680° C., the substrate 4 is irradiated with only As, and the process is waited for 10 seconds (standby step).
次に、再び基板温度を600℃に戻し、GaとAlの
シヤツター5を開けてAl0.5Ga0.5Asバリア層を
0.5μm成長させ、量子井戸層構造が形成される。 Next, the substrate temperature is returned to 600°C, the Ga and Al shutter 5 is opened, and the Al 0.5 Ga 0.5 As barrier layer is formed.
A quantum well layer structure is formed by growing 0.5 μm.
このようにして形成された量子井戸のPLスペ
クトルを77kで測定すると、第1図bの実線のス
ペクトルのように2つのピークが見られる。それ
ぞれのピークは、厚さが1分子層分異なるGaAs
量子井戸、即ち厚さ4.5a0と5.0a0(a0はGaAsの格
子定数)の量子井戸からのPL発光に対応してい
る。従来の界面形成法により、待機を3分間行な
つた場合のスペクトルが破線で示されている。こ
の場合にもピークが2つあり、界面が平坦化さ
れ、島が形成されていることがわかるが発光強度
が本発明の場合の1/3程度に落ちている。 When the PL spectrum of the quantum well formed in this manner is measured at 77K, two peaks are seen as shown in the solid line spectrum in Figure 1b. Each peak corresponds to a GaAs layer whose thickness differs by one molecular layer.
It corresponds to PL emission from quantum wells, that is, quantum wells with thicknesses of 4.5a 0 and 5.0a 0 (a 0 is the lattice constant of GaAs). The dashed line shows the spectrum obtained when waiting for 3 minutes using the conventional interface formation method. In this case as well, there are two peaks, indicating that the interface is flattened and islands are formed, but the emission intensity has fallen to about 1/3 of that in the case of the present invention.
このように、本発明によれば発光効率の高い、
高品質な界面を有する量子井戸が得られる。 As described above, according to the present invention, the luminous efficiency is high.
Quantum wells with high quality interfaces can be obtained.
尚、以上の実施例では、量子井戸を例にとつた
が、ヘテロ界面への変調ドーピングを行なつた2
次元電子ガス系等においても、本発明のヘテロ界
面形成法は、界面の高品質化に有効であること言
うまでもない。 In the above embodiments, a quantum well was used as an example, but modulation doping to the hetero interface was performed.
Needless to say, the method for forming a heterointerface of the present invention is effective in improving the quality of the interface in dimensional electron gas systems and the like.
また、InGaAs/InAlAs等の他の材料系におい
ても本発明は有効であるのは言うまでもない。 It goes without saying that the present invention is also effective for other material systems such as InGaAs/InAlAs.
(発明の効果)
以上のように、本発明のヘテロ界面形成法によ
れば、界面が単分子層の高さの平坦な島領域から
形成され、極めて平坦かつ急峻であるだけでな
く、界面に不純物が少ない。この結果、発光スペ
クトルが狭く、強度が強いので発光・受光素子の
作製等各種半導体素作製の応用に適する。また、
界面が平坦で純物が少ないのでヘテロ界面でのキ
ヤリアの輪送現像を利用した電子デバイスの作製
に応用に適する。(Effects of the Invention) As described above, according to the heterointerface formation method of the present invention, the interface is formed from a flat island region with the height of a monomolecular layer, and is not only extremely flat and steep, but also Low impurities. As a result, the emission spectrum is narrow and the intensity is strong, making it suitable for applications in the production of various semiconductor elements, such as the production of light-emitting and light-receiving devices. Also,
Since the interface is flat and there are few pure substances, it is suitable for application to the production of electronic devices using carrier rotation development at a heterointerface.
第1図aは、本発明のヘテロ界面形成方法を説
明する基板温度の時間変化グラフ、第1図bは、
本発明により形成した量子井戸の77kにおけるフ
オトルミネツセンススペクトル図である。第2図
は、本発明に用いられる分子線エピタキシ装置の
概略断面図である。
図中、1……成長室、20……Ga分子線源、
21……Al分子線源、22……As分子線源、3
……基板ホルダー、4……基板、5……シヤツタ
ー、9……イオンポンプをそれぞれ示す。
FIG. 1a is a graph of changes in substrate temperature over time to explain the method of forming a heterointerface of the present invention, and FIG. 1b is a
FIG. 3 is a photoluminescence spectrum diagram at 77k of a quantum well formed according to the present invention. FIG. 2 is a schematic cross-sectional view of a molecular beam epitaxy apparatus used in the present invention. In the figure, 1... growth chamber, 20... Ga molecular beam source,
21...Al molecular beam source, 22...As molecular beam source, 3
. . . substrate holder, 4 . . . substrate, 5 . . . shutter, 9 . . . ion pump, respectively.
Claims (1)
定の温度に保持した基板に照射して基板上に原子
又は分子を堆積させる分子線エピタキシ成長にお
いて、第1の原子又は分子を堆積させる第1のエ
ピタキシヤル成長工程と、該第1のエピタキシヤ
ル成長を中止して前記基板の温度を前記第1のエ
ピタキシヤル成長工程の場合よりも高く保持して
待機する待機工程と、待機工程に続いて該基板の
温度を該待機工程より低い温度に保持して第2の
原子又は分子を堆積させる第2のエピタキシヤル
成長工程を少なくとも有することを特徴とするヘ
テロ界面形成方法。1 In molecular beam epitaxy growth, in which atoms or molecules are deposited on the substrate by irradiating a molecular beam containing elements constituting a desired crystal onto a substrate held at a predetermined temperature, the first step is to deposit the first atoms or molecules. an epitaxial growth step, a standby step in which the first epitaxial growth is stopped and the temperature of the substrate is held higher than in the first epitaxial growth step, and subsequent to the standby step, A method for forming a heterointerface, comprising at least a second epitaxial growth step of depositing second atoms or molecules while maintaining the temperature of the substrate at a temperature lower than that of the standby step.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11781887A JPS63282193A (en) | 1987-05-13 | 1987-05-13 | Formation of hetero interface |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11781887A JPS63282193A (en) | 1987-05-13 | 1987-05-13 | Formation of hetero interface |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63282193A JPS63282193A (en) | 1988-11-18 |
| JPH0536396B2 true JPH0536396B2 (en) | 1993-05-28 |
Family
ID=14721015
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11781887A Granted JPS63282193A (en) | 1987-05-13 | 1987-05-13 | Formation of hetero interface |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63282193A (en) |
-
1987
- 1987-05-13 JP JP11781887A patent/JPS63282193A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63282193A (en) | 1988-11-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2587623B2 (en) | Epitaxial crystal growth method for compound semiconductor | |
| WO1987003740A1 (en) | Process for forming thin film of compound semiconductor | |
| US4960728A (en) | Homogenization anneal of II-VI compounds | |
| US4554030A (en) | Method of manufacturing a semiconductor device by means of a molecular beam technique | |
| JP2905667B2 (en) | Method for manufacturing II-VI compound semiconductor thin film and II-VI compound semiconductor device | |
| JPH0936427A (en) | Semiconductor device and manufacturing method thereof | |
| JPH0536396B2 (en) | ||
| EP0215436A2 (en) | Method of growth of thin film layer for use in a composite semiconductor | |
| JP2706369B2 (en) | Method for growing compound semiconductor and method for manufacturing semiconductor laser | |
| JPS6394615A (en) | Manufacture of vertical type semiconductor super lattice | |
| JPS61225817A (en) | Apparatus for molecular beam epitaxial growth | |
| US5134091A (en) | Quantum effective device and process for its production | |
| JPH0727865B2 (en) | Hetero interface formation method | |
| JP3182584B2 (en) | Compound thin film forming method | |
| US5940723A (en) | Heteroepitaxial growth of III-V materials | |
| JPH0787179B2 (en) | Method for manufacturing superlattice semiconductor device | |
| JPH0831410B2 (en) | Method for manufacturing semiconductor device | |
| JP2006253414A (en) | Method for forming semiconductor thin film on Si substrate and structure thereof | |
| JPH0992930A (en) | Semiconductor device | |
| JP4041887B2 (en) | Method for forming antimony quantum dots | |
| JPS6245107A (en) | Formation of semiconductor thin-film | |
| JP3096579B2 (en) | Vapor phase growth method and vapor phase growth apparatus | |
| JPH06191989A (en) | Production of semiconductor crystal thin film | |
| JPH09118588A (en) | Molecular beam epitaxial growth method and apparatus | |
| JP4565172B2 (en) | Quantum well using BeTe / CdS heterointerface |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |