JPH0727865B2 - Hetero interface formation method - Google Patents
Hetero interface formation methodInfo
- Publication number
- JPH0727865B2 JPH0727865B2 JP28221587A JP28221587A JPH0727865B2 JP H0727865 B2 JPH0727865 B2 JP H0727865B2 JP 28221587 A JP28221587 A JP 28221587A JP 28221587 A JP28221587 A JP 28221587A JP H0727865 B2 JPH0727865 B2 JP H0727865B2
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- Japan
- Prior art keywords
- semiconductor
- mixed crystal
- molecular beam
- interface
- crystal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 title claims description 31
- 125000005842 heteroatom Chemical group 0.000 title claims description 18
- 230000015572 biosynthetic process Effects 0.000 title description 3
- 239000013078 crystal Substances 0.000 claims description 51
- 239000004065 semiconductor Substances 0.000 claims description 30
- 238000001451 molecular beam epitaxy Methods 0.000 claims description 16
- 239000002052 molecular layer Substances 0.000 claims description 10
- 125000000129 anionic group Chemical group 0.000 claims description 9
- 125000002091 cationic group Chemical group 0.000 claims description 9
- 230000001678 irradiating effect Effects 0.000 claims description 5
- 150000001875 compounds Chemical class 0.000 claims description 3
- 150000001768 cations Chemical class 0.000 claims 1
- 239000002356 single layer Substances 0.000 claims 1
- 239000000758 substrate Substances 0.000 description 14
- 229910052738 indium Inorganic materials 0.000 description 5
- 230000007704 transition Effects 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 4
- 239000000969 carrier Substances 0.000 description 4
- 239000002994 raw material Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- 108010083687 Ion Pumps Proteins 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- 125000004432 carbon atom Chemical group C* 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000295 emission spectrum Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 230000003595 spectral effect Effects 0.000 description 1
- 230000005533 two-dimensional electron gas Effects 0.000 description 1
Landscapes
- Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
- Recrystallisation Techniques (AREA)
Description
【発明の詳細な説明】 [産業上の利用分野] 本発明は、ヘテロ界面の形成方法に関し、特に分子線エ
ピタキシ法によって化合物半導体の高品質ヘテロ界面を
形成する方法に関する。Description: TECHNICAL FIELD The present invention relates to a method for forming a hetero interface, and more particularly to a method for forming a high quality hetero interface of a compound semiconductor by a molecular beam epitaxy method.
[従来の技術] 2次元電子ガストランジスタや量子井戸レーザのような
化合物半導体のデバイスは、その多くが異種の半導体結
晶を接合したヘテロ接合を利用するものである。ヘテロ
接合界面(以下、ヘテロ界面と称する)の性質はキャリ
アの散乱や、発光、吸収等に影響し、デバイス特性を大
きく左右する。従って、平坦かつ急峻で、不純物や欠陥
のない高品質の界面を形成することが重要である。この
ような急峻なヘテロ界面を形成する手段として分子線エ
ピタキシ(Molecular Beam Epitaxy,以下MBEと称する)
法が広く行われている。[Prior Art] Most of compound semiconductor devices such as a two-dimensional electron gas transistor and a quantum well laser utilize a heterojunction in which different kinds of semiconductor crystals are joined. The properties of the heterojunction interface (hereinafter referred to as the heterointerface) affect carrier scattering, light emission, absorption, etc., and greatly affect device characteristics. Therefore, it is important to form a high-quality interface that is flat and steep and has no impurities or defects. Molecular beam epitaxy (hereinafter referred to as MBE) is a means of forming such a steep hetero interface.
The law is widely practiced.
第2図は、このMBE法を行うために一般的に用いられるM
BE装置の概略断面図を示したもので、イオンポンプ等の
真空ポンプ9によって超高真空に保たれた成長室1中
に、所望の結晶を構成する元素を含む原料を加熱し、分
子線状に各元素を噴出させる分子線源20,21,22,23と、
この分子線源20,21,22,23とは独立に温度制御可能に基
板4を加熱・保持する基板ホルダ3とを設け、各分子線
源20,21,22,23から基板4に向けて原料元素の分子線を
噴出させてエピタキシャル成長を行うものである。MBE
法では、各分子線源の前方に配設されたシャッタ5a〜5d
の開閉により個々の分子線の継続を行うと共に、各原料
の蒸発源の温度設定により分子線強度の変調制御を行う
ことができる。Figure 2 shows the M commonly used to perform this MBE method.
FIG. 1 is a schematic cross-sectional view of a BE apparatus, in which a raw material containing an element that constitutes a desired crystal is heated in a growth chamber 1 kept in an ultrahigh vacuum by a vacuum pump 9 such as an ion pump to form a molecular beam. Molecular beam source 20,21,22,23 for ejecting each element to
This molecular beam source 20, 21, 22, 23 is provided with a substrate holder 3 for heating and holding the substrate 4 so that the temperature can be controlled independently of each other, and the molecular beam sources 20, 21, 22, 23 are directed toward the substrate 4. Epitaxial growth is performed by ejecting the molecular beam of the raw material element. MBE
In the method, shutters 5a-5d arranged in front of each molecular beam source are used.
It is possible to continue the individual molecular beam by opening and closing, and to control the modulation of the molecular beam intensity by setting the temperature of the evaporation source of each raw material.
従来、MBE法において原子のオーダーで平坦かつ急峻な
ヘテロ界面を形成する方法としては、各分子線源20〜23
のシャッタ5a〜5dを閉じることで成長を界面で中断し、
数十秒ないし数分間待機することにより、界面の平坦性
を増す方法がGaAs/AlGaAsヘテロ系について報告されて
いる(ジャパニーズ・ジャーナル・オブ・アプライド・
フィジックス(Jpn.J.Appl.Phys.),24,(1985),L417
頁)。ここではこの方法を、界面待機MBE法と呼ぶ。Conventionally, as a method of forming a flat and steep hetero interface on the order of atoms in the MBE method, each molecular beam source 20 to 23
Growth is interrupted at the interface by closing the shutters 5a-5d of
A method of increasing the flatness of the interface by waiting for several tens of seconds to several minutes has been reported for the GaAs / AlGaAs hetero system (Japanese Journal of Applied.
Physics (Jpn.J.Appl.Phys.), 24, (1985), L417
page). This method is called the interface waiting MBE method here.
第3図は従来の界面待機MBE法によるヘテロ界面形成方
法を工程順に模式的に説明した説明図である。ここでは
AxC1-xD3元混晶上にAyB1-yD3元混晶を界面待機MBE法
により積層する場合を説明する。なお、A,B,Cは陽イオ
ン性、Dは陰イオン性元素を表す。また図中、D元素に
ついては省略した。FIG. 3 is an explanatory view schematically explaining a conventional hetero interface formation method by the interface standby MBE method in the order of steps. here
A case where A y B 1-y D ternary mixed crystal is laminated on the A x C 1-x D ternary mixed crystal by the interface waiting MBE method will be described. In addition, A, B, and C are cationic, and D is an anionic element. Further, in the figure, the D element is omitted.
第2図において、分子線源20,21,22および23にそれぞれ
A,C,BおよびDの各元素の原料を入れ、分子線源20,21お
よび23の前方のシャッタ5a,5bおよび5dを開き、下地のA
xC1-xDの成長を行った後、AおよびC元素の分子線源20
および21の前方のシャッタ5aおよび5bを閉じてD元素の
みを照射する状態とする。中断した瞬間には、第3図
(a)に示すように表面に高さ2分子層におよぶ凹凸が
存在している。しかし、そのまま90〜180秒待期を続け
ると表面上のAおよびC原子あるいは分子が表面を拡散
し、表面のステップやキンクに捉えられて第3図(b)
に示すように高さが1分子層の平坦な島を形成する。次
に、AおよびB元素の分子線源20および22の前方のシャ
ッタ5aおよび5cを開いて、平坦化された表面の上にAyB
1-yD3元混晶を成長させれば、第3図(c)に示すよう
に所望のヘテロ界面が得られる。こうして得られた界面
の遷移領域の幅は、1分子層分であり、極めて急峻かつ
平坦なものである。In Fig. 2, the molecular beam sources 20, 21, 22 and 23 are respectively
Put the raw materials of each element of A, C, B and D, open the shutters 5a, 5b and 5d in front of the molecular beam sources 20, 21 and 23 to open the A
After the growth of x C 1-x D, a molecular beam source of A and C elements 20
The shutters 5a and 5b in front of and 21 are closed to irradiate only the D element. At the moment of interruption, as shown in FIG. 3 (a), there is unevenness having a height of two molecular layers on the surface. However, if the waiting period is continued for 90 to 180 seconds, A and C atoms or molecules on the surface diffuse on the surface and are captured by steps or kinks on the surface, as shown in FIG. 3 (b).
As shown in, a flat island having a height of one molecular layer is formed. Next, the shutters 5a and 5c in front of the molecular beam sources 20 and 22 of the A and B elements are opened, and A y B is placed on the flattened surface.
By growing a 1-y D ternary mixed crystal, a desired hetero interface can be obtained as shown in FIG. 3 (c). The width of the transition region of the interface thus obtained is one molecular layer, which is extremely steep and flat.
[発明が解決しようとする問題点] しかしながら、この1分子層分の遷移領域を詳細に検討
すると、この部分は陽イオン性元素としてA,B,C種類の
元素が共存した4元混晶になっている。このことは次の
ような不利益をもたらす。即ち、4元混晶は3元混晶よ
りもキャリアを散乱させやすい。また界面に望ましくな
いエネルギーポテンシャルの乱れが生じ、界面に沿う方
向へのキャリアの輸送を妨げる。この問題は、遷移領域
の4元混晶組成が界面に平行な面内で均一でないので、
ことに重大である。界面におけるポテンシャルの乱れ
は、このような界面を持つ量子井戸からの励起子発光の
スペクトル幅を拡げる働きをする。従って量子井戸を光
素子に応用する際には大きな問題である。[Problems to be Solved by the Invention] However, when the transition region of one molecular layer is examined in detail, this part is a quaternary mixed crystal in which A, B, and C elements coexist as cationic elements. Has become. This has the following disadvantages. That is, the quaternary mixed crystal is more likely to scatter carriers than the ternary mixed crystal. In addition, undesired disturbance of the energy potential occurs at the interface, which hinders the transport of carriers in the direction along the interface. This problem is because the quaternary mixed crystal composition in the transition region is not uniform in the plane parallel to the interface,
Especially important. The disturbance of the potential at the interface serves to expand the spectral width of exciton emission from the quantum well having such an interface. Therefore, it is a big problem when the quantum well is applied to an optical device.
本発明の目的は、以上述べたような従来の問題点を解決
するためになされたもので、界面での望ましくない混晶
の形成を防止して高品質のヘテロ界面を形成する方法を
提供することにある。The object of the present invention is to solve the above-mentioned conventional problems, and provides a method for forming a high-quality hetero interface by preventing the formation of an undesired mixed crystal at the interface. Especially.
[問題点を解決するための手段] 本発明は、第1の半導体N元混晶(Nは3以上の自然数
を表す)の上に該第1の半導体N元混晶と共通の陽イオ
ン性元素と陰イオン性元素を少なくとも1個ずつ含む第
2の半導体M元混晶(Mは3以上の自然数を表す)を分
子線エピタキシ法により積層してなる半導体ヘテロ界面
の形成方法において、第1の半導体N元混晶をエピタキ
シャル成長させる第1の成長工程と、陽イオン性元素を
含む分子線の照射を停止し、陰イオン性元素のみを含む
分子線を照射しながら待機することにより、前記第1の
成長工程で成長した第1の半導体N元混晶表面の段差が
1分子層となるように平坦化する表面平坦化工程と、前
記第1の半導体N元混晶と第2の半導体M元混晶に共通
の陽イオン性元素および陰イオン性元素からなる第3の
半導体Q元結晶または混晶(Qは2≦Q≦Nの自然数を
表す)を1分子層だけ成長させる第2の成長工程と、前
記第2の半導体M元混晶を前記第3の半導体Q元結晶ま
たは混晶の上にエピタキシャル成長させる第3の成長工
程とを有してなることを特徴とするヘテロ界面形成方法
である。[Means for Solving the Problems] The present invention is directed to a first semiconductor N-element mixed crystal (N represents a natural number of 3 or more) and a common cationic property with the first semiconductor N-element mixed crystal. In a method for forming a semiconductor hetero interface, a second semiconductor M-element mixed crystal (M represents a natural number of 3 or more) containing at least one element and at least one anionic element is laminated by a molecular beam epitaxy method. In the first growth step of epitaxially growing the semiconductor N-element mixed crystal, and by irradiating the molecular beam containing the cationic element and waiting while irradiating the molecular beam containing only the anionic element, A surface flattening step of flattening the surface of the first semiconductor N-ary mixed crystal grown in the first growth step so as to form a single molecular layer; and the first semiconductor N-ary mixed crystal and the second semiconductor M. Common cationic and anionic elements in mixed crystals A second growth step of growing a third semiconductor Q-source crystal or mixed crystal (Q represents a natural number of 2 ≦ Q ≦ N) consisting of one molecular layer, and the second semiconductor M-source mixed crystal as described above. And a third growth step of epitaxially growing on a third semiconductor Q-source crystal or mixed crystal.
[作用] 第1図は本発明によるヘテロ界面形成方法を工程順に模
式的に説明した説明図である。ここではAxC1-xD3元混
晶上にAyB1-yD3元混晶を積層する場合を説明する。な
お、A,B,Cは陽イオン性、Dは陰イオン性元素を表す。
また図中、D元素については省略した。[Operation] FIG. 1 is an explanatory view schematically explaining the method for forming a hetero interface according to the present invention in the order of steps. Here, a case of stacking an A y B 1-y D ternary mixed crystal on an A x C 1-x D ternary mixed crystal will be described. In addition, A, B, and C are cationic, and D is an anionic element.
Further, in the figure, the D element is omitted.
第1図(a)は下地のAxC1-xDの成長を行った後、成長
を中断した時の下地の半導体3元混晶の表面を示したも
のである。次に、平坦化を行って、第1図(b)に示す
ような表面状態とした後、第1および第2の半導体混晶
に共通の元素からなる結晶を1分子層分成長させると第
1図(c)に示す如くなり、界面の遷移領域には、高々
N元の混晶しか形成されない。次いで第1図(d)に示
すように、第2の半導体混晶であるAyB1-yDを積層して
ヘテロ構造を形成する。この方法によれば、従来の方法
のように下地の混晶より次数の高い、即ちキャリアを散
乱しやすい混晶が形成されることがなく、キャリアの輸
送効率の高い界面が得られる。FIG. 1 (a) shows the surface of the underlying semiconductor ternary mixed crystal when the growth of the underlying A x C 1-x D was stopped and the growth was stopped. Next, flattening is performed to obtain a surface state as shown in FIG. 1 (b), and then a crystal of an element common to the first and second semiconductor mixed crystals is grown for one molecular layer. As shown in FIG. 1 (c), only N-element mixed crystals are formed at the transition region of the interface. Then, as shown in FIG. 1D, a second semiconductor mixed crystal A y B 1-y D is laminated to form a heterostructure. According to this method, unlike the conventional method, a mixed crystal having a higher order than that of the underlying mixed crystal, that is, a mixed crystal that easily scatters carriers is not formed, and an interface having high carrier transport efficiency can be obtained.
[実施例] 以下、図面を参照しながら本発明の一実施例を説明す
る。[Embodiment] An embodiment of the present invention will be described below with reference to the drawings.
本発明の方法に用いられるMBE装置としては例えば前記
の第2図に示すような装置を用いることができる。以
下、例として第1図の説明図におけるAをIn、BをGa、
CをAl、DをAsとし、InP(001)基板上に第1の半導体
N元混晶として、InxAl1-xAs(x=0.52)を、第2のM
元半導体混晶としてInyGa1-yAs(y=0.53)を積層して
ヘテロ構造を形成する場合について述べる。As the MBE device used in the method of the present invention, for example, the device shown in FIG. 2 can be used. In the following, as an example, A in the explanatory diagram of FIG. 1 is In, B is Ga,
C is Al, D is As, and In x Al 1-x As (x = 0.52) is used as the first semiconductor N-ary mixed crystal on the InP (001) substrate and the second M is used.
A case will be described in which In y Ga 1-y As (y = 0.53) is stacked as a source semiconductor mixed crystal to form a heterostructure.
第2図に示すMBE装置の各分子線源は、それぞれ20にI
n、21にGa、22にAl、23にAsが原料として充填されてい
る。Each molecular beam source of the MBE device shown in Fig. 2 has 20
Ga is filled in n, 21 and Al in 22 and As in 23.
まず、通常の方法によりInP(001)基板4を有機洗浄
し、化学的にエッチングして清浄化した後、10-10Torr
台の超高真空に排気された成長室1中の基板ホルダ3に
装着する。First, the InP (001) substrate 4 is organically cleaned by a usual method, chemically etched and then cleaned, and then 10 -10 Torr.
It is mounted on the substrate holder 3 in the growth chamber 1 which is evacuated to an ultrahigh vacuum of the table.
成長開始に先立ち、In、Ga、Alの各分子線源20,21,22は
所望の組成、即ちInxAl1-xAs(x=0.52)とInyGa1-yAs
(y=0.53)が得られるように温度制御される。また、
As分子線源23も、InP基板4表面において2×10-5Torr
の強度が得られるように温度を制御する。As分子線源23
の前方のシャッタ5dを開け、As分子線をInP基板4に照
射しつつ、基板ホルダ3に取付けられた抵抗ヒータの温
度を上げ、As圧下でInP基板4の表面を熱クリーニング
する。通常、540℃で表面の酸化膜や汚れが脱離し、表
面が清浄となる。次に基板温度を550℃に安定させ、In
とAlの分子線源20,22の前方のシャッタ5a,5cを開けて、
In0.52Al0.48Asを0.5μm成長させる(第1の成長工
程)。典型的な成長速度は0.8μm/hであった。Prior to the start of growth, the In, Ga, and Al molecular beam sources 20, 21, and 22 have desired compositions, that is, In x Al 1-x As (x = 0.52) and In y Ga 1-y As.
The temperature is controlled so that (y = 0.53) is obtained. Also,
As molecular beam source 23 is also 2 × 10 −5 Torr on the surface of InP substrate 4.
The temperature is controlled so that the strength of As molecular beam source 23
The shutter 5d in front of is opened, the temperature of the resistance heater attached to the substrate holder 3 is raised while irradiating the InP substrate 4 with the As molecular beam, and the surface of the InP substrate 4 is thermally cleaned under As pressure. Normally, the oxide film and dirt on the surface are removed at 540 ° C, and the surface becomes clean. Next, stabilize the substrate temperature at 550 ° C and
Open the shutters 5a, 5c in front of the Al and Al molecular beam sources 20, 22,
In 0.52 Al 0.48 As is grown to 0.5 μm (first growth step). The typical growth rate was 0.8 μm / h.
次に、InとAlの分子線源20,22のシャッタ5a,5cを閉じて
成長を中断する。ここで成長の中断の瞬間は前記の第1
図(a)に対応する。Next, the shutters 5a and 5c of the In and Al molecular beam sources 20 and 22 are closed to interrupt the growth. Here, the moment of interruption of growth is the first
It corresponds to FIG.
次いで、そのままAsを照射しながら、120秒待機を行っ
て平坦化を行う(平坦化工程)。この状態は前記の第1
図(b)に対応する。Next, while irradiating As as it is, the wafer is waited for 120 seconds to be planarized (planarization step). This state is the first
It corresponds to FIG.
次に、Inの分子線源20の前方のシャッタ5aを1分子層の
厚さ、即ち、約2.93Åに相当する2.5秒だけ開ける。こ
の第2の成長工程により表面がInAsにより覆われる(第
1図(c)に対応)。Next, the shutter 5a in front of the In molecular beam source 20 is opened for 2.5 seconds corresponding to the thickness of one molecular layer, that is, about 2.93Å. The surface is covered with InAs by this second growth step (corresponding to FIG. 1 (c)).
続いて、Gaの分子線源21の前方のシャッタ5bを開け、In
0.53Ga0.47Asを成長させ、第3の成長工程を行う。Subsequently, the shutter 5b in front of the Ga molecular beam source 21 is opened, and In
0.53 Ga 0.47 As is grown and a third growth step is performed.
以上の工程により前記第1図(d)に対応するヘテロ界
面が形成される。このヘテロ界面では、界面に平行な方
向には4元混晶は存在せず、界面は3元混晶であるI
nx′Al1-x′AsからIny′Ga1-y′Asへ急峻に切替ってい
る。従って、従来の界面待機MBE法では避けられない。
4元混晶よりなる界面遷移領域が生じず、高品質な界面
が得られる。界面にできるInx′Al1-x′AsとIny′G
a1-y′Asは、必ずしもInP基板4に格子整合しないが、
1分子層しかないのでその影響はほとんど無視できる。Through the above steps, the hetero interface corresponding to FIG. 1 (d) is formed. At this hetero interface, there is no quaternary mixed crystal in the direction parallel to the interface, and the interface is a ternary mixed crystal.
is it abruptly switched from n x 'Al 1-x' As to In y 'Ga 1-y' As. Therefore, the conventional interface waiting MBE method cannot avoid it.
An interface transition region composed of a quaternary mixed crystal does not occur, and a high quality interface can be obtained. In x ′ Al 1-x ′ As and In y ′ G formed at the interface
Although a 1- y′As does not always have lattice matching with the InP substrate 4,
Since there is only one molecular layer, its effect can be almost ignored.
[発明の効果] 以上述べたように、本発明のヘテロ界面形成方法によれ
ば、界面が1分子層の高さの平坦な島から形成され、極
めて急峻であるだけでなく、キャリアを散乱したり、エ
ネルギーポテンシャルを乱す望ましくない混晶層を生じ
ない。この結果、ヘテロ界面に沿ったキャリアの輸送現
象を利用した電子デバイスの作製や、界面での混晶(合
金)散乱が発光スペクトル幅に影響する量子井戸を用い
た光素子の作製に適する。[Effects of the Invention] As described above, according to the method for forming a hetero interface of the present invention, the interface is formed from a flat island having a height of one molecular layer, is not only extremely steep, but also scatters carriers. In addition, an undesired mixed crystal layer that disturbs the energy potential is not generated. As a result, it is suitable for manufacturing an electronic device utilizing the carrier transport phenomenon along the hetero interface and for manufacturing an optical element using a quantum well in which mixed crystal (alloy) scattering at the interface affects the emission spectrum width.
第1図は本発明のヘテロ界面形成方法を模式的に説明し
た工程図、第2図は本発明の方法に用いられるMBE装置
の一例を示す概略断面図、第3図は従来の界面待機MBE
法によるヘテロ界面の形成方法を模式的に説明した工程
図である。 1……成長室、3……基板ホルダ 4……基板、5a〜5d……シャッタ 9……真空ポンプ、20〜23……分子線源 A,B,C……陽イオン性元素 D……陰イオン性元素FIG. 1 is a process diagram schematically explaining the hetero interface forming method of the present invention, FIG. 2 is a schematic sectional view showing an example of an MBE apparatus used in the method of the present invention, and FIG. 3 is a conventional interface standby MBE.
FIG. 7 is a process diagram schematically illustrating a method for forming a hetero interface by the method. 1 ... Growth chamber, 3 ... Substrate holder 4 ... Substrate, 5a-5d ... Shutter 9 ... Vacuum pump, 20-23 ... Molecular beam source A, B, C ... Cationic element D ... Anionic element
Claims (1)
数を表す)の上に該第1の半導体N元混晶と共通の陽イ
オン性元素と陰イオン性元素を少なくとも1個ずつ含む
第2の半導体M元混晶(Mは3以上の自然数を表す)を
分子線エピタキシ法により積層してなる半導体ヘテロ界
面の形成方法において、第1の半導体N元混晶をエピタ
キシャル成長させる第1の成長工程と、陽イオン性元素
を含む分子線の照射を停止し、陰イオン性元素のみを含
む分子線を照射しながら待機することにより、前記第1
の成長工程で成長した第1の半導体N元混晶表面の段差
が1分子層となるように平坦化する表面平坦化工程と、
前記第1の半導体N元混晶と第2の半導体M元混晶に共
通の陽イオン性元素および陰イオン性元素からなる第3
の半導体Q元結晶または混晶(Qは2≦Q≦Nの自然数
を表す)を1分子層だけ成長させる第2の成長工程と、
前記第2の半導体M元混晶を前記第3の半導体Q元結晶
または混晶の上にエピタキシャル成長させる第3の成長
工程とを有してなることを特徴とするヘテロ界面形成方
法。1. At least one cation element and an anionic element common to the first semiconductor N-element mixed crystal (N is a natural number of 3 or more) and common to the first semiconductor N-element mixed crystal. In a method for forming a semiconductor hetero interface, which comprises stacking second semiconductor M-ary mixed crystals (M is a natural number of 3 or more) containing each by a molecular beam epitaxy method, the first semiconductor N-ary mixed crystal is epitaxially grown. The first growth step and the irradiation of the molecular beam containing the cationic element are stopped, and the waiting is performed while irradiating the molecular beam containing only the anionic element.
A surface flattening step for flattening the step difference on the surface of the first semiconductor N-source mixed crystal grown in the growing step to form a monolayer.
A third compound composed of a cationic element and an anionic element common to the first semiconductor N-source mixed crystal and the second semiconductor M-source mixed crystal
A second growth step of growing only one molecular layer of the semiconductor Q elemental crystal or mixed crystal (Q represents a natural number of 2 ≦ Q ≦ N) of
A third growth step of epitaxially growing the second semiconductor M-element mixed crystal on the third semiconductor Q-element crystal or mixed crystal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28221587A JPH0727865B2 (en) | 1987-11-10 | 1987-11-10 | Hetero interface formation method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28221587A JPH0727865B2 (en) | 1987-11-10 | 1987-11-10 | Hetero interface formation method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01125818A JPH01125818A (en) | 1989-05-18 |
| JPH0727865B2 true JPH0727865B2 (en) | 1995-03-29 |
Family
ID=17649557
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28221587A Expired - Fee Related JPH0727865B2 (en) | 1987-11-10 | 1987-11-10 | Hetero interface formation method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0727865B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2729528B2 (en) * | 1990-04-13 | 1998-03-18 | ヤンマーディーゼル株式会社 | Soundproof work equipment |
| JP4629247B2 (en) * | 2001-02-14 | 2011-02-09 | 本田技研工業株式会社 | Outboard motor cooling passage structure |
-
1987
- 1987-11-10 JP JP28221587A patent/JPH0727865B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01125818A (en) | 1989-05-18 |
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