JPH053952B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a horizontal synchronization signal extraction circuit that removes equalization pulses from a reproduced signal of a VTR or the like and extracts a horizontal synchronization signal.

2. Description of the Related Art A device that separates a composite synchronization signal from a composite video signal, obtains a frequency-combined signal with the composite synchronization signal, and then processes the video signal, for example.
In the jitter correction device during VTR playback operation,
The above frequency coupling is configured to follow the horizontal synchronizing signal of the reproduced signal, and the equalization pulse of the vertical blanking period is converted into a wind signal by some method (for example, the method shown in Japanese Patent Application Laid-Open No. 53-148914). It has been modified to extract only the horizontal synchronization signal information using .

FIG. 3 is a block diagram showing a conventional example, and FIG. 4 is a diagram showing waveforms of each part thereof. 1 is a terminal to which a composite synchronization signal (waveform 1 in Figure 4) is applied, and 2 is a monostable multi-circuit as synchronization extraction means, which extracts the leading edge information of the composite synchronization signal and outputs the pulse of waveform 3. , only the horizontal synchronization information is extracted by the gate circuit 4 and applied to the phase comparator (PC) 5. The oscillation frequency of the voltage controlled oscillator (VCO) 6 changes under the control of the PC 5.

A clock from the VCO 6 is applied to an output terminal 7 and a frequency divider 8, and a horizontal synchronous frequency clock (waveform 9) is generated from the frequency divider 8 and applied to the PC 5 and the gate circuit 4. Above PC5, VCO6 and frequency divider 8
This constitutes a PLL 11 as a phase synchronization means.

In the PC 5, the horizontal synchronization information from the gate circuit 4 and the clock (waveform 9) from the frequency divider 8 are compared in phase. The clock (waveform 9) is also used as a gate signal (ie, a window signal) for the gate circuit 4.

The gate circuit 4 extracts only the leading edge information (waveform 3) of the composite synchronization signal that has entered the window signal 9 (high level in FIG. 4), and outputs horizontal synchronization information such as waveform 10.

Problems to be Solved by the Invention However, the reproduced video signal from a helical scan VTR is subject to expansion and contraction of the signal at the connection of signal tracks (head switching point) due to expansion and contraction of the magnetic tape and rotating cylinder system. skew distortion) occurs. In VHS type VTR cylinders, etc., the above skew amount is currently 10 μs ~
Expected to be around 30μs. In addition, in order to prevent the skew effect of the reproduced image, the time axis correction device etc.
The head switching point of the VTR is located in the first half of the vertical blanking period of the video signal (the equalization pulse period of the period before the vertical synchronization signal).

This is because a PLL designed in pursuit of residual jitter performance of the time base correction device requires about 10H to 20H (1H is one horizontal synchronization signal section) as a response to the above-mentioned skew amount.

How the conventional configuration shown in FIG. 3 behaves in response to skew will be described with reference to FIG. 4.
In FIG. 4, cases where there is skew in the reproduced signal are distinguished by adding a dash (-) to the code.

The reproduced composite synchronizing signal 1-1 has a skew 13 at the head switching point 12.

Immediately after head switching point 12
Since the PLL 11 is not responding, the window signal 9-1 from the frequency divider 8 in the PLL 11 predicts that the horizontal synchronization signal will come at regular intervals around the head switching point 12, so the incoming composite synchronization Among the leading edge information (waveform 3-1) of the signal 1-1, the pulse that has entered the window signal 9-1 is determined to be horizontal synchronization information (waveform 10-1), and the waveform 10-1 is applied to the PC5. , PLL11 on waveform 10-1
locks.

However, at the end of the equalization pulse period 14, the leading edge information (waveform 3-1) of the composite synchronization signal 1-1
It can be seen from the figure that the relationship between the window signal 9-1 and the window signal 9-1 is reversed from that before the head switching 12. Therefore, the waveform 10-1 (horizontal synchronization information) is no longer applied to the PC 5, and the PLL 11 remains unlocked for a while. Here, if the window signal 9-1 is configured to operate only during the equalization pulse period 14, the waveform 10-1
As shown by the broken line, a new 0.5H skew 15 occurs at the end of the equalization pulse period.

In this state, as mentioned above, in the first half of the vertical blanking period, in order to prevent the skew effect on the reproduced image,
The purpose of locating the head switching point becomes meaningless. The cause of this skew is that the waveform extracted by the gate circuit 4 immediately after the head switching 12 is not the original horizontal synchronization information.

In the end, the unondo signal 9-1 of the conventional example does not follow the reproduced signal in which the skew has occurred, so
The biggest drawback of the conventional method was that horizontal synchronization information was extracted incorrectly from the equalization pulse. Also,
Since the wind signal 9-1, which is the output of the frequency divider 8 of the PLL 11, moves relative to the reproduced signal during the skew response process of the PLL 11, the waveform 9-1 shown in FIG.
(as shown by the dashed arrow) toward waveform 9-1)
Depending on the skew condition, during the equalization pulse period
0.5H skew may occur. (Detailed explanation will be omitted.) Therefore, there is also a problem in using the output of the frequency divider 8 of the PLL 11 as the wind pulse.

Means for Solving the Problems In order to solve the problems of the above-mentioned conventional example, the present invention has the following steps:
Obtain a composite synchronization signal from the reproduced video signal of a VTR, etc.
The leading edge information of this composite synchronization signal is extracted by the synchronization extraction means, and one piece of leading edge information of an unnecessary equalization pulse component is extracted from this leading edge information using the output (wind signal) of the oscillation means having the frequency of the horizontal synchronization period. The equalization pulse removing means is configured to extract only the horizontal synchronizing signal component by removing the horizontal synchronizing signal components, and furthermore, the horizontal frequency of the composite synchronizing signal is calculated from the first vertical reference (for example, vertical synchronizing signal) position of the previous field of the composite synchronizing signal. A phase synchronization means is provided to generate a clock (for example, a clock with a frequency twice the horizontal synchronization frequency) synchronized with the horizontal synchronization frequency, and this clock is counted a predetermined number of times and delayed by the time of one field of the reproduced video signal. A skew detection means is configured to derive a reference and detect the amount of skew from the phase relationship between the second vertical reference and the third vertical reference (for example, the vertical synchronization signal of the composite synchronization signal), and , a horizontal synchronizing signal extracting circuit characterized by having a signal generating means for shifting the phase of the window signal.

Effect The present invention uses the above-described configuration to calculate the skew amount that occurs when switching heads by using the phase difference between the second vertical reference (vertical synchronization signal information of the previous field) and the third vertical reference (vertical synchronization signal information of the current field). The amount of deviation is detected as the amount of skew. In addition, this value is detected as an integral value, and by taking advantage of the fact that the skew amount does not involve sudden fluctuations, the wind signal is shifted by a phase amount corresponding to the integral value of the phase shift amount, and the horizontal synchronization signal is stably generated. Extract.

Embodiment An embodiment of the present invention is shown in FIG. 1, and the timing of each part will be explained using FIG. 2. Elements that are the same as those of the conventional example are given the same numbers, and only the parts that are different from the conventional example will be explained.

When the present invention is in operation, the PLL 11 attempts to lock onto the horizontal synchronization information (points a to p indicated by broken lines on waveform 1 in FIG. 2) of the composite synchronization signal (waveform 1) input to input terminal 1. _H16 is output from frequency divider 8. The PLL 11 is affected by the skew 13 that occurs around the head switching point 12, which is the switching point of multiple heads in the waveform 1, and it takes a period of 1 to follow the horizontal synchronization information a to p.
It takes 7.

On the other hand, from the composite synchronization signal input to input terminal 1,
Waveform 18-1 (vertical synchronization signal) is extracted in VS _YNC SEP18. Monostable multi 19 (MM2)
is the pulse waveform 19-1 from the trailing edge of the waveform 18-1 to after the period 17 when the PLL 11 becomes stable.
(the trailing edge is the first vertical reference). The counter 20 counts the clock 2 _H (waveform 21) generated by the phase synchronization means in the frequency divider 8 from a first vertical reference, and outputs a waveform 22 (the trailing edge of which is the second vertical reference). The second vertical reference is located immediately before the head switching point 12 of the next field, and the clock _2H counts the time equivalent to one field period of the reproduced video signal, so it is not affected by skew. is not set to the previous state. Monostable Multi 23 (MM3)
creates a pulse 23-1 from the second vertical reference to near the leading edge of the vertical synchronization signal 18-1. The trapezoidal wave generating circuit 24 generates a trapezoidal wave 24-1 having a slope like a waveform 24-1 from the trailing edge of the pulse 23-1, and supplies the trapezoidal wave 24-1 to a sample hold (S/H) 25.

On the other hand, the monostable multi 26 uses the vertical synchronization signal 18
A sample pulse 26-1 is generated at the -1 leading edge (third vertical reference) and is supplied to the S/H 25.
In the S/H 25, a potential obtained by sampling the trapezoidal wave 24-1 using a sample pulse 26-1 is extracted. This becomes the detected skew amount. Integrating circuit 2
7 averages the sample potential corresponding to this skew amount, and the time constant of the monostable multi 28 (MM5) is controlled by this output. The flip-flop 29 (FF1) is cleared by the waveform 22 output from the counter 20 and reset just before the head changeover, and is then reset at the first rising edge of _{the H} waveform 16 after the trailing edge of the waveform 22 (second vertical reference). Output starts at edge.

MM5 outputs a pulse waveform 28-1 having a width corresponding to control with the above voltage from the rise of the output of flip-flop 29. This operates as a phase correction value for skew, and the oscillator 32 stops oscillating at the H level of the output pulse 28-1 of the monostable multi 28, and starts oscillating from the trailing edge of the pulse 28-1. i.e. monostable multi 30 (MM6), 3
1 (MM7) constitutes an oscillator 32 having a substantially horizontal synchronous frequency, and outputs a waveform 32-1.

Here, as mentioned above, the second vertical reference is
This is output from PLL 11 in a stable state, and it stably matches the video signal of the previous field. Furthermore, since the trailing edge of the output waveform 28-1 of the monostable multi 28 is controlled by the voltage corresponding to the skew amount as described above, the waveform 32 that oscillates from the trailing edge of the waveform 28-1 is the skew amount. 13, and matches the phase of the horizontal synchronization information of the next field.

For example, as shown in FIG. 2, if the skew amount is small and the vertical synchronization signal moves closer to the second vertical reference (18-2 shown by the broken line in the waveform 18 in FIG. 2), The sample pulse 26 also moves to the left in FIG. 4, as indicated by a broken line 26-2.
This causes the sample point to become trapezoidal 24
In order to sample the high voltage of -1, the averaged voltage also becomes high, and the width of the pulse 28-1 of the monostable multi 28 becomes narrower, so the waveform 32
The signal generation means operates so that the -1 oscillation starts earlier and the phase is automatically shifted.

In this manner, after the head switching point, the waveform 32-1 generated by this signal generating means can be stably used as a window signal for the next field. However, before the head switching point, it does not match the horizontal synchronizing signal, so _H16 from PLL 11 is more stable as a window signal, so before and after the head switching point, the above waveform 32-1 and The switch that switches _H16 is SW33.

Furthermore, the flip-flop 34 (FF2) is cleared at the leading edge of the equalization pulse period pulse (the waveform example is omitted at the point in _FIG .
is output from SW33. In addition, the flip-flop 34 becomes H level due to the head switch pulse of the input terminal 35, and the waveform 32 is output from the SW 33.
-1 is controlled to be output as a window signal. Further, the gate circuit 36 (gate 2) outputs the output signal from the SW 33 only during the equalization pulse period, and outputs a window signal such as a waveform 36-2, which is applied to the gate circuit 4. This is because from this point on, the PLL circuit becomes stable even if it is affected by skew.

On the other hand, the output waveform from monostable multi 2 is like waveform 3, and points A to △ are marked on the same waveform.
All the horizontal synchronization information of R is the wind signal 36-2.
All pulses other than points A to R in waveform 3 are within the H level of window signal 36-.
2, unnecessary equalization pulse information is stably removed, skew occurs only between points C and D, and skew 15, which occurs in the conventional example, is eliminated.
No skew occurs at all other than the head switching points such as .

Note that in this embodiment, the second vertical reference is counted by one field to bring it to the previous field state, but if a reference with the skew amount corrected is set, the purpose will be achieved, and skew will not occur. Needless to say, it is sufficient to count only the period of values that include the range.

Effects of the Invention The present invention performs playback by switching between multiple heads.
If the head switching point of the VTR is placed during the equalization pulse period, malfunction of the equalization pulse removal circuit that extracts horizontal synchronization information from the equalization pulse period due to skew distortion can be completely prevented.

In addition, in order to prevent errors in extracting horizontal synchronization information in the time axis corrector, etc., skew occurs only at the head switching point, and the PLL
follows the vertical blanking period stably and has no skew effect on the reproduced image. Furthermore, the same effect can be obtained by applying the present invention to other equipment that handles video signals.

Further, depending on the configuration of the PLL, a pulse delay such as a monostable multi (MM2) 19 or a monostable multi (MM3) 23 is not particularly necessary.

Additionally, if the head switching point depends on the vertical blanking position, switch 33
is not particularly important and the same effects as the present invention can be obtained.

The output of frequency divider 8 serves as the clock for counter 20.
_2H was used, but any clock may be used as long as it is synchronized with the reproduced video signal.

Monostable multi (MM1, 2, 3, 4, 5, 6,
7) etc., the same effect can be obtained even if other circuit configurations are used.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG.
3 is a block diagram of a conventional example, and FIG. 4 is a diagram of its operation waveforms. 2, 19, 23, 26, 28, 30, 31...
Monostable multi (MM), 4...gate circuit, 5...
... Phase comparator (PC), 6 ... Voltage controlled oscillator (VCO), 8 ... Frequency divider, 11 ... PLL, 18 ...
...VSYNC SEP, 20...Counter, 24...
Trapezoid generation circuit, 25...Sample hold (S/
H), 27... Integration circuit, 29, 34... Flip-flop (FF), 32... Oscillator, 33... Switch (SW), 36... Gate circuit.

Claims (1)

[Scope of Claims] 1. A plurality of heads that reproduce video signals recorded as a plurality of tracks on a recording medium, and leading edge information of a pulse of a composite synchronization signal included in the reproduced video signal reproduced by the heads. synchronization extraction means for extracting a signal; equalization pulse removal means for extracting a horizontal synchronization signal by gating the leading edge information signal extracted by the synchronization extraction means with a window signal; phase synchronization means for generating a horizontal synchronization timing signal; extracting a vertical synchronization signal from the composite synchronization signal; skew detection means for detecting a skew amount which is an amount of discontinuity in the time axis of the reproduced signal; and signal generation means for generating a signal with a horizontal synchronization period whose phase changes according to the output of the skew detection means, A horizontal synchronizing signal extraction circuit configured to output the output of the generating means as the window signal and the output of the equalization pulse removing means as the horizontal synchronizing signal. 2. Claims characterized in that the reference point of the skew detection means uses a signal obtained by using the horizontal synchronization timing signal of the phase synchronization means as a clock and delaying the vertical synchronization signal by one field period of the reproduced video signal. 2. The horizontal synchronization signal extraction circuit according to item 1. 3. The horizontal synchronizing signal extraction circuit according to claim 1, further comprising gate means for making the output of the signal generating means a window signal only during the equalization pulse period of the composite synchronizing signal. 4. The horizontal synchronizing signal extraction circuit according to claim 1, wherein the skew amount detected by the skew detection means is outputted via an integrating circuit.