JPH0543293B2 - - Google Patents

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a method of manufacturing a semiconductor device, and particularly relates to a method for manufacturing a semiconductor device, particularly a high frequency GaAs MES (Metal Semiconductor).
It is related to the manufacture of FETs and is used in the manufacture of submicron dual gate FETs.

(Conventional technology) Conventionally, it is well known as a high frequency device.
GaAs dual-gate FETs are used in UHF band mixers, etc., but the gate electrode formation method used so far is photolithography. It is based on graphi, and the gate length is (>1μm),
Further, the distance between both gates was several μm.

(Problems to be Solved by the Invention) To date, many submicron gate formation methods have been reported for single gates, but there have been few reports for dual gates.
The submicron region is the limit for photolithography, and since it is a dual gate, pattern separation between gates becomes a problem. Therefore, currently the only option is to use an EB device (electron beam exposure device), but with an EB device, drawing takes a very long time and the throughput is poor.
Furthermore, even if an EB device is used, what is formed is a resist pattern, so the problem of pattern conversion differences also arises when forming gate electrodes. As described above, there has been no effective method for forming submicron dual gates.

Therefore, the present invention uses photolithography in the same way as in the past, without reducing throughput.
This allows submicron dual-gate FETs to be easily manufactured.

(Means and effects for solving the problems) The present invention includes a step of providing a laminated metal film in which a high melting point metal and a barrier metal are laminated in this order on a semiconductor substrate, and a mask pattern on the laminated metal film. A process of forming a photoresist or insulating film, a process of depositing an Au film on the mask pattern and the laminated metal film, and a process of removing the Au film on the mask pattern and etching the mask pattern. a step of leaving and adhering the dual gate Au film to the side wall; a step of removing the mask pattern;
The present invention is characterized by comprising a step of etching and removing the laminated metal film using the remaining Au film as a mask to provide a laminated film of the high melting point metal, barrier metal, and Au film on the semiconductor substrate.

In other words, the present invention makes it possible to form submicron dual gates by depositing an Au film on the sidewalls of a resist or insulating film pattern that can be formed by photolithography and etching it. This eliminates the need to form submicron resist patterns. In addition, by providing a laminated metal layer of high melting point metal, barrier metal, and Au, it has short key characteristics and
A MESFET with excellent resistance characteristics can be obtained.

(Example) Examples of the present invention will be described below with reference to the drawings.
Figure 1 shows the dual gate before reaching the same embodiment.
It is a diagram to obtain MESFET. As shown in Figure 1a
For example, by photography in which a resist is laminated on a GaAs substrate 1, or by an insulating film 2, for example.
After stacking 5000 angstroms, the insulating film 2 is opened using photolithography, and then the resist is peeled off and the insulating film is patterned.
(Space interval 1.5 to 2 μm) Next, as shown in Figure 1b, a gate metal film 3 is placed on the resist or oxide film 2.
(3000 angstroms) using a sputtering device. The gate metal film 3 is made of a high melting point metal (W, TiW,
(WSi, WN, WSiN, etc.). Here, if a resist is used for the film 2, the resist may sag due to the temperature increase during metal deposition, and the metal thickness cannot be made very thick. However, it is easy to remove in the next step. Further, when an insulating film is used as the film 2, pattern distortion does not occur, but removal is troublesome. Next, etching is performed using ion milling so that the beam is incident perpendicularly. At this time, since the beam is perpendicularly incident, the metal is scattered in a 45 degree direction as shown in FIG. Therefore, by using a resist for the film 2, even if the gate metal film 3 is thin, it can be made thicker at the etching stage as shown in FIG. 1d. Next, as shown in Figure 1e, a resist or oxide film 2 is formed.
is removed to form a submicron gate 3.

FIG. 2 shows an embodiment of the present invention that is a development of FIG. When using a metal stacked gate as shown in Figure 2 (for example, WN/Mo/Au), the second
As shown in figure a, there is a WN layer 4 ₁ and a Mo layer 4 ₂ on the GaAs substrate 1.
are sequentially laminated, and resist pattern 2 is formed on Mo layer 4 ₂ .
By forming the Au mask 3 and performing the same process as in FIG. 1, the Au mask 3 as shown in FIG. 2c can be obtained. Next, by performing reactive ion etching using this Au as a mask, the underlying metal 4 can be pattern-transferred, and a laminated gate electrode can be formed as shown in FIG. 2d.

Here, the WN layer 4 ₁ functions as a high melting point metal, the Mo layer 4 ₂ functions as a barrier metal, and the Au layer 3 functions as a low resistance metal. In particular, the above-mentioned high melting point metal does not change its shot key characteristics even when subjected to high temperatures during the process, and has the advantage that high quality shot key characteristics are obtained, so that high frequency amplification does not deteriorate.

[Effects of the Invention] As explained above, according to the present invention, a submicron dual gate can be formed using conventional photolithography technology, and there is no need to use an EB device, thereby increasing throughput. Furthermore, by using gate metal Au, a stacked gate can be easily formed, and gate resistance can be reduced. Furthermore, by using a high melting point metal on the semiconductor, it is possible to prevent the shot key characteristics from changing at high temperatures. Therefore, according to the present invention, it is possible to provide a MESFET that is a submicron dual gate but has excellent shot key characteristics and resistance characteristics.

[Brief explanation of the drawing]

FIG. 1 is a process diagram for manufacturing a dual gate prior to the present invention, and FIG. 2 is a process diagram showing an embodiment of the present invention. 1... Semi-insulating GaAs substrate, 2... Photoresist or insulating film, 3... Au layer, 4... Laminated gate metal.

Claims (1)

[Claims] 1. A step of providing a laminated metal film in which a high melting point metal and a barrier metal are laminated in this order on a semiconductor substrate, and forming a photoresist or an insulating film serving as a mask pattern on the laminated metal film. process, and on the mask pattern and laminated metal film.
a step of depositing an Au film, and a step of removing the Au film on the mask pattern by directional etching, and leaving a dual gate Au film on the sidewalls of the mask pattern and attaching it;
a step of removing the mask pattern and removing the remaining mask pattern;
A method for manufacturing a semiconductor device, comprising the step of etching and removing the laminated metal film using an Au film as a mask to provide a laminated film of the high melting point metal, barrier metal, and Au film on the semiconductor substrate. . 2. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor substrate is GaAs. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is a submicron dual-gate MESFET.