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JPH0544187B2 - - Google Patents
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JPH0544187B2 - - Google Patents

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Publication number
JPH0544187B2
JPH0544187B2 JP57038014A JP3801482A JPH0544187B2 JP H0544187 B2 JPH0544187 B2 JP H0544187B2 JP 57038014 A JP57038014 A JP 57038014A JP 3801482 A JP3801482 A JP 3801482A JP H0544187 B2 JPH0544187 B2 JP H0544187B2
Authority
JP
Japan
Prior art keywords
sample
junction
current
frequency
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57038014A
Other languages
Japanese (ja)
Other versions
JPS58155732A (en
Inventor
Noriaki Honma
Tadasuke Munakata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP57038014A priority Critical patent/JPS58155732A/en
Publication of JPS58155732A publication Critical patent/JPS58155732A/en
Publication of JPH0544187B2 publication Critical patent/JPH0544187B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00Testing or measuring during manufacture or treatment of wafers, substrates or devices

Landscapes

  • Testing Of Individual Semiconductor Devices (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Description

【発明の詳細な説明】 本発明は、半導体におけるp−n接合の接合抵
抗が再結合電流によつて支配されているときの空
乏層内のキヤリア寿命を測定する装置に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an apparatus for measuring carrier lifetime in a depletion layer when the junction resistance of a pn junction in a semiconductor is dominated by recombination current.

一般に、p−n接合ダイオードの電流−電圧特
性は次式で表わされることは良く知られている。
Generally, it is well known that the current-voltage characteristics of a pn junction diode are expressed by the following equation.

Jd=Jp(eq/mkTVd−1) …(1) ただし、Jdはダイオード電流密度、Jpは飽和電
流密度、Vdはダイオード印加電圧、qは電子の
電荷、kボルツマン定数、Tは温度、mは1かそ
れ以上の数を表わす。理想的なダイオードではキ
ヤリアの拡散によつて電流が流れ、m=1であ
る。しかし、Siのように真性キヤリア濃度niが小
さい場合には、キヤリアの再結合による電流が支
配的となり、m=2で与えられる特性となる。結
局、再結合による電流が支配的なダイオードの電
流−電圧特性は、横軸にqVd/kT、縦軸にlog
(Jd/Jp)をとると第1図のようになる(図中、
(JdFなる曲線は順方向電流の場合を示し、(JdR
なる曲線は逆方向電流の場合を示す。)。
J d = J p (e q/mkTVd −1) …(1) where, J d is the diode current density, J p is the saturation current density, V d is the diode applied voltage, q is the electron charge, k is the Boltzmann constant, T represents temperature, and m represents a number of 1 or more. In an ideal diode, current flows due to carrier diffusion, and m=1. However, when the intrinsic carrier concentration n i is small like S i , the current due to carrier recombination becomes dominant, and the characteristic is given by m=2. In the end, the current-voltage characteristics of a diode, in which the current due to recombination is dominant, are expressed as qV d /kT on the horizontal axis and log on the vertical axis.
If (J d /J p ) is taken, it becomes as shown in Figure 1 (in the figure,
The curve (J d ) F shows the case of forward current, and (J d ) R
The curve shows the case of reverse current. ).

すなわち、再結合電流が支配的な領域では直線
部分の傾きがm=2となり、該直線がVd=0で
ある縦軸と交差する点のJdは、再結合による飽和
電流密度Jprを与える。このような再結合電流の
増加は、小信号レベルのダイオード特性を劣化さ
せることになる。
That is, in the region where recombination current is dominant, the slope of the straight line part is m = 2, and J d at the point where the straight line intersects the vertical axis where V d = 0 is the saturation current density J pr due to recombination. give. Such an increase in recombination current deteriorates the diode characteristics at a small signal level.

Vd≪kT/qである場合には、再結合電流密度
Jdrは次式で与えられる。
If V d ≪kT/q, the recombination current density
J dr is given by the following formula.

Jdr=(qniWVd)/(√po ppVb) …(2) ここで、τpoは接合近傍のp層でのキヤリア寿
命、τppは接合近傍のn層でのキヤリア寿命、W
は空乏層幅、Vbは接合の拡散電位である。
J dr = (qn i WV d ) / (√ po pp V b ) ...(2) Here, τ po is the carrier life in the p layer near the junction, τ pp is the carrier life in the n layer near the junction, W
is the depletion layer width, and V b is the junction diffusion potential.

(2)式において、τre=√po ppとしたとき、τre

空乏層での実効的キヤリア寿命を表わす。これよ
り、ダイオードの電流−電圧特性を測定し、(2)式
を含めた(1)式の計算値を測定値にフイツテングさ
せることにより、τre=√po ppを評価することが
できる。この結果、τreの大小によつてダイオー
ド特性の良否を評価できる。〔参照:プロシーデ
イングス オブ ザ アイアールイー(Proc.
IRE),Vol.45,Sept/1957,pp.1228−1243〕 しかし、この従来方法では、電流−電圧特性を
測定するため、接合ダイオードに抵抗性電極を形
成する必要が有る。従つて、素子の製造プロセス
途上で評価する場合、電極形成工程が余分に必要
となる問題がある。さらに、電極形成に伴う汚染
や損傷の影響が発生するので、事実上破壊測定で
あるという欠点を持つ。
In equation (2), when τ re =√ po pp , τ re
represents the effective carrier lifetime in the depletion layer. From this, by measuring the current-voltage characteristics of the diode and fitting the calculated value of equation (1) including equation (2) to the measured value, τ re =√ po pp can be evaluated. As a result, the quality of the diode characteristics can be evaluated based on the magnitude of τ re . [Reference: Proceedings of the IR (Proc.
IRE), Vol. 45, Sept/1957, pp. 1228-1243] However, in this conventional method, in order to measure the current-voltage characteristics, it is necessary to form a resistive electrode on the junction diode. Therefore, when evaluating the device during the manufacturing process, there is a problem in that an extra electrode forming step is required. Furthermore, since the effects of contamination and damage associated with electrode formation occur, this method has the disadvantage of being virtually a destructive measurement.

本発明は半導体のp−n接合の空乏層における
キヤリア寿命を試料に電極を形成する前に、非接
触、非破壊的に測定し得るキヤリア寿命測定装置
を提供することを目的とする。
An object of the present invention is to provide a carrier life measuring device that can non-contact and non-destructively measure the carrier life in a depletion layer of a pn junction of a semiconductor before forming an electrode on a sample.

以下、本発明を図面を用いて詳細に述べる。 Hereinafter, the present invention will be described in detail using the drawings.

はじめに、本発明の原理について述べる。 First, the principle of the present invention will be described.

半導体のp−n接合に、エネルギーギヤツプよ
りも大きい光子エネルギーの光を照射すると、接
合には光電流が流れ、光電圧が発生することは良
く知られている。これを電気的な等価回路で表わ
すと第2図のようになる。ここで、Cjは接合容
量、Rjは接合抵抗を表わす。
It is well known that when a pn junction of a semiconductor is irradiated with light having a photon energy greater than the energy gap, a photocurrent flows through the junction and a photovoltage is generated. This can be expressed as an electrical equivalent circuit as shown in FIG. Here, C j represents junction capacitance, and R j represents junction resistance.

次に、光の強度を周波数でチヨツピングする
と、それに応じて光電圧も周波数で変化するこ
とになる。このとき、接合の両端に発生する光電
圧の開放電圧Vppは光電流密度をJp、接合面積を
Sとすると次式で与えられる。
Next, when the intensity of light is stepped by frequency, the photovoltage also changes by frequency accordingly. At this time, the open-circuit voltage Vpp of the photovoltage generated at both ends of the junction is given by the following equation, where Jp is the photocurrent density and S is the junction area.

Vpp=Rj/1+jωCjRjJpS …(3) ここで、ω=2πである。従つて、Vppは交流
信号となるが、その振幅は次式で与えられる。
V pp =R j /1+jωC j R j J p S...(3) Here, ω=2π. Therefore, V pp becomes an alternating current signal, and its amplitude is given by the following equation.

|Vpp|=Rj/√1+ω2Cj 2Rj 2|Jp|S …(4) ところで、照射光の波長が、光の吸収が半導体
の基板のキヤリア拡散量より十分短かい領域とな
るように選んでやれば、Jpはωによつて変化せず
一定とみなせることが知られている。従つて、こ
のとき|Vppの周波数依存性は、横軸と縦軸を対
数で表わすと第3図のようになる。これより、|
Vpp|の周波数特性は、次式で与えられる遮断周
波数cを持つ。
|V pp |=R j /√1+ω 2 C j 2 R j 2 |J p |S...(4) By the way, the wavelength of the irradiated light is a region where the absorption of light is sufficiently shorter than the amount of carrier diffusion of the semiconductor substrate. It is known that if it is chosen so that J p does not change with ω and can be considered constant. Therefore, in this case, the frequency dependence of |V pp is as shown in FIG. 3 when the horizontal and vertical axes are expressed logarithmically. From now on, |
The frequency characteristic of V pp | has a cutoff frequency c given by the following equation.

c=1/2πCjRj …(5) さて、Cjは接合の空乏層容量であるので、Cj
εpεsS/W(式中、εpは真空中の誘電率、εsはSiの
比誘電率)で与えられる。ここで、p層の不純物
濃度をNA、n層の不純物濃度をNDとすると、空
乏層幅Wは次式で与えられる。
c = 1/2πC j R j …(5) Now, C j is the depletion layer capacitance of the junction, so C j =
It is given by ε p ε s S/W (where ε p is the dielectric constant in vacuum, and ε s is the relative dielectric constant of Si). Here, when the impurity concentration of the p layer is N A and the impurity concentration of the n layer is N D , the depletion layer width W is given by the following equation.

W=√2p s -1A -1D -1b …(6) 一方、Vdが十分小さく、接合が再結合電流に
よつて特徴づけられる場合には、Rjは次式で与
えられる。
W=√2 p s -1 ( A -1 + D -1 ) b …(6) On the other hand, if V d is sufficiently small and the junction is characterized by a recombination current, R j can be expressed as is given by

Rj=Vd/(JdrS)=τreVb/(qniWS) …(7) これより、(6)式と(7)式を用いて、(5)式からc
求めることができる。この結果、τreは次式で与
えられる。
R j = V d / (J dr S) = τ re V b / (qn i WS) ...(7) From this, use equations (6) and (7) to find c from equation (5). be able to. As a result, τ re is given by the following equation.

τre=(ni/πc)(NA -1+ND -1) …(8) ここで、真性キヤリア濃度niは温度が決まれば
半導体に固有の値となる。従つて、NAとNDが既
知であればcを測定することにより、実効的なキ
ヤリア寿命τreを求めることができる。
τ re =(n ic )(N A -1 +N D -1 ) (8) Here, the intrinsic carrier concentration n i becomes a value specific to the semiconductor once the temperature is determined. Therefore, if N A and N D are known, the effective carrier life τ re can be determined by measuring c .

さらに、この方法は電圧を印加するかわりに光
を照射するので非接触、非破壊で行うことが可能
である。すなわち、光をチヨツピングしているた
め、発生する光電圧は交流状となる。従つて、電
気的容量を介すれば、非接触で信号の光電圧が測
定できることになる。従つて、ダイオードに電極
を形成する必要がない。
Furthermore, since this method irradiates light instead of applying voltage, it can be performed non-contact and non-destructively. In other words, since the light is being stepped, the generated photovoltage is in the form of an alternating current. Therefore, the optical voltage of the signal can be measured without contact via the electrical capacitance. Therefore, there is no need to form electrodes on the diode.

なお、NAやNDの値は、渦電流法や、光反射
法、光の偏光解析法などの方法によりあらかじめ
非接触、非破壊的に測定できることは知られてい
る。
Note that it is known that the values of N A and N D can be measured in advance in a non-contact and non-destructive manner by methods such as the eddy current method, the light reflection method, and the polarization analysis method.

次に、本発明を具体的な実施例を参照して詳細
に説明する。
Next, the present invention will be explained in detail with reference to specific examples.

第4図は本発明によるキヤリア寿命測定装置の
一例を示す。1は金属試料台で電極を兼ねてい
る。2はp−n接合を有するウエハ試料である。
その上に電気的容量結合をなすために数10μm離
して透明電極4を付けたガラス板5が、試料2と
透明電極4との間隔が一定になるようにスペーサ
3の上に載せられている。一法、発光ダイオード
(LED)光源7は周波数スイープ発振器8とLED
駆動回路9とによつて変調され、周波数のパル
ス光が放射される。LED7から放射された光は、
レンズ6によつて試料3の上に集光される。光の
照射によつて試料3に生じた光電圧は、参照番号
1と4との電極を介して入力インピーダンスが
100MΩ以上の位相検波型増幅器10により検出
される。次に、発振器8の周波数をスイープさせ
て光電圧の周波数特性を測定する。位相検波型増
幅器10の出力は参照番号11で示した3dB降下
電圧検出回路に接続され、出力が3dB降下した点
で周波数スイープ発振器8のスイープを停止させ
る。同時に、参照番号11′のゲート回路を開き、
参照番号12のA−D変換器により発振器8のそ
のときの周波数をデジタル信号としてインターフ
エース回路13に接続する。一方、NA,NDのデ
ータはインターフエース回路13を通してマイク
ロコンピユータ14に入力されており、cの値が
入力される毎に演算が行なわれる。求められた実
効的なキヤリア寿命τreの値はプリンター15で
出力される。
FIG. 4 shows an example of a carrier life measuring device according to the present invention. 1 is a metal sample stage which also serves as an electrode. 2 is a wafer sample having a pn junction.
A glass plate 5 on which transparent electrodes 4 are attached at a distance of several tens of μm to form electrical capacitive coupling is placed on the spacer 3 so that the distance between the sample 2 and the transparent electrodes 4 is constant. . One method, light emitting diode (LED) light source 7 is a frequency sweep oscillator 8 and LED
The light is modulated by the drive circuit 9 and pulsed light having a certain frequency is emitted. The light emitted from LED7 is
The light is focused onto the sample 3 by the lens 6. The photovoltage generated on the sample 3 by the irradiation of light is transmitted through the electrodes with reference numbers 1 and 4, and the input impedance is
It is detected by a phase detection type amplifier 10 of 100MΩ or more. Next, the frequency of the oscillator 8 is swept to measure the frequency characteristics of the optical voltage. The output of the phase detection type amplifier 10 is connected to a 3 dB voltage drop detection circuit indicated by reference numeral 11, and the sweep of the frequency sweep oscillator 8 is stopped when the output drops by 3 dB. At the same time, open the gate circuit with reference number 11',
The current frequency of the oscillator 8 is connected to the interface circuit 13 as a digital signal by an A-D converter reference number 12. On the other hand, the data N A and N D are input to the microcomputer 14 through the interface circuit 13, and calculations are performed every time the value of c is input. The value of the determined effective carrier life τ re is output by the printer 15.

以上説明したごとく本発明によれば、再結合電
流で支配されているp−n接合空乏層内のキヤリ
ア寿命を、試料に電極を形成せずに、非接触、非
破壊的に測定できることになる。従つて、製造プ
ロセスにおいて、電極形成前に素子の良否を判定
でき、しかも測定した試料は破壊されないため、
歩留り向上に大きな効果を発揮しうる。
As explained above, according to the present invention, the carrier lifetime in the p-n junction depletion layer, which is dominated by recombination current, can be measured non-contact and non-destructively without forming an electrode on the sample. . Therefore, in the manufacturing process, the quality of the device can be determined before electrode formation, and the measured sample is not destroyed.
This can be highly effective in improving yield.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はp−n接合ダイオードの電流−電圧特
性を説明するための曲線図、第2図はp−n接合
の電気的な等価回路を示す図、第3図は光電圧の
周波数特性を示す曲線図、第4図は光電圧の周波
数特性から遮断周波数を測定し、キヤリア寿命を
求めるための本発明によるキヤリア寿命測定装置
の実施例を示す図である。 1……金属試料台兼電極、2……試料、3……
スペーサ、4……透明電極、5……ガラス板、6
……レンズ、7……LED光源、8……周波数ス
イープ発振器、9……LED駆動回路、10……
位相検波型増幅器、11……3dB降下電圧検出回
路、11′……ゲート回路、12……A−D変換
器、13……インターフエース回路、14……マ
イクロコンピユータ、15……プリンター。
Figure 1 is a curve diagram to explain the current-voltage characteristics of a p-n junction diode, Figure 2 is a diagram showing the electrical equivalent circuit of a p-n junction, and Figure 3 is a diagram showing the frequency characteristics of a photovoltage. The curve diagram shown in FIG. 4 is a diagram showing an embodiment of the carrier life measuring device according to the present invention for measuring the cutoff frequency from the frequency characteristics of the optical voltage and determining the carrier life. 1...Metal sample stand and electrode, 2...Sample, 3...
Spacer, 4...Transparent electrode, 5...Glass plate, 6
... Lens, 7 ... LED light source, 8 ... Frequency sweep oscillator, 9 ... LED drive circuit, 10 ...
Phase detection amplifier, 11...3dB voltage drop detection circuit, 11'...gate circuit, 12...A-D converter, 13...interface circuit, 14...microcomputer, 15...printer.

Claims (1)

【特許請求の範囲】 1 導電性試料台と、上記試料台上に置かれた接
合を有する半導体試料と、上記試料に対向するよ
うに近接して設けられた透明電極と、上記透明電
極を介して上記試料上に周波数可変のパルス化し
た光子ビームを照射する手段と、上記周波数可変
のパルス化した光子ビームを発生する手段と、上
記光子ビームの照射によつて上記試料の表裏面に
発生する光電圧を取り出すため上記透明電極と上
記試料台に接続された増幅手段と、上記増幅手段
の出力信号から上記半導体試料における接合の遮
断周波数を求めるための信号処理手段において、 上記遮断周波数と上記半導体試料の不純物濃度
とから所定の関係式に基づいて上記半導体試料の
空乏層でのキヤリア寿命を算出する演算手段を備
えたことを特徴とするキヤリア寿命測定装置。
[Claims] 1. A conductive sample stage, a semiconductor sample having a bond placed on the sample stage, a transparent electrode provided in close proximity to face the sample, and a means for irradiating a pulsed photon beam with a variable frequency onto the sample; a means for generating the pulsed photon beam with a variable frequency; an amplification means connected to the transparent electrode and the sample stage for extracting a photovoltage, and a signal processing means for determining a cutoff frequency of a junction in the semiconductor sample from an output signal of the amplification means, the cutoff frequency and the semiconductor sample being A carrier life measuring device comprising a calculation means for calculating the carrier life in the depletion layer of the semiconductor sample based on a predetermined relational expression from the impurity concentration of the sample.
JP57038014A 1982-03-12 1982-03-12 Measuring device for life of carrier Granted JPS58155732A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57038014A JPS58155732A (en) 1982-03-12 1982-03-12 Measuring device for life of carrier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57038014A JPS58155732A (en) 1982-03-12 1982-03-12 Measuring device for life of carrier

Publications (2)

Publication Number Publication Date
JPS58155732A JPS58155732A (en) 1983-09-16
JPH0544187B2 true JPH0544187B2 (en) 1993-07-05

Family

ID=12513714

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57038014A Granted JPS58155732A (en) 1982-03-12 1982-03-12 Measuring device for life of carrier

Country Status (1)

Country Link
JP (1) JPS58155732A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3274924B2 (en) * 1993-12-15 2002-04-15 株式会社東芝 Semiconductor device screening method

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5856437U (en) * 1981-10-09 1983-04-16 株式会社日立製作所 Semiconductor junction characteristic measurement device

Also Published As

Publication number Publication date
JPS58155732A (en) 1983-09-16

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