JPH0584673B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a memory cell of a semiconductor memory device in which the presence or absence of charge is stored information.

[Conventional technology]

As an example of a conventional semiconductor memory device of this type,
Figure 6 shows the configuration of the memory cells of 16k and 64k dynaq RAM. In FIG. 6, 1 is a semiconductor substrate with P ^- type conductivity, 2 is a gate electrode connected to a power supply terminal T1, 3 is a gate electrode connected to a connection terminal T2 for connecting a word line, and 4 is a gate electrode. An insulating film, 5 an interlayer insulating film, and 6 a charge storage region.
7 is an N ⁺ region as a bit line, 8 is an inter-element isolation insulating film for isolation between elements, 9 is ^a P ⁺ region for isolation between elements, and each N ⁺ region 6, Depletion layers 10 and 11 are formed between 7 and semiconductor substrate 1, respectively. In FIG. 6, the wiring portion and the protective film are omitted. Also, to simplify the explanation, region 6 is assumed to be an N ⁺ diffusion region, but
In the case of a normal configuration, by applying a positive potential to the gate electrode 2, an N ⁺ inversion layer is induced in a portion corresponding to the region 6 on the semiconductor surface via the gate insulating film 4, and charges are accumulated. There is.

In such a conventional configuration, a state in which electrons are accumulated in the N ⁺ region 6 as a charge accumulation region of a memory cell is defined as "0", and a state in which electrons are not accumulated is defined as "1". And N ⁺ region 7 as bit line
The potential is held at a certain intermediate potential in advance by the function of a sense amplifier (not shown).

Here, when the potential of the word line increases and the potential of the gate electrode 3 as a transfer gate connected to this word line becomes higher than the threshold voltage, a channel of the N ⁺ inversion layer is formed directly under the gate electrode 3. As a result, both N ⁺ regions 6 and 7 become electrically conductive.

Now, the stored information in the memory cell is “0”, that is,
In the case where electrons are accumulated in the N ⁺ region 6,
When N ⁺ region 6 and N ⁺ region 7 as a bit line are brought into conduction, the potential of N ⁺ region 7, which had been held at an intermediate potential up to that point, is lowered.
Conversely, if the stored information of the memory cell is "1", that is, no electrons are accumulated in the N ⁺ region 6, this conduction causes the potential of the N ⁺ region 7, which was at an intermediate potential, to rise. . The change in the potential of this bit line is sensed and amplified by a sense amplifier and taken out, and the same stored information is refreshed and written into the memory cell again within the same cycle.

[Problem that the invention seeks to solve]

Conventional memory cells operate in this way, but because the charge storage region 6 and the bit line 7 are formed of an N ⁺ region or an N ⁺ inversion layer, radiation such as alpha rays enters the memory chip and is generated. Electrons in the electron-hole pairs that are generated are collected in these charge storage regions 6 and bit lines 7, inverting the original stored information and causing malfunctions (hereinafter referred to as "soft errors"). There was a drawback.

The present invention was made in view of these points, and its purpose is to eliminate soft errors caused by radiation such as alpha rays with a simple structure without impairing transistor characteristics even in a miniaturized structure. The object of the present invention is to obtain a method for manufacturing a semiconductor memory device that can be manufactured easily.

[Means for solving problems]

In order to eliminate such drawbacks, the present invention selectively implants and diffuses impurities to form a highly concentrated impurity diffusion region of the first conductivity type, and utilizes a frame process in the element isolation process. The impurity diffusion region is extended to form a highly doped region of the first conductivity type.

[Effect]

In a semiconductor memory device manufactured by applying the present invention, malfunctions caused by incidence of radiation such as alpha rays are prevented, and transistors operate stably.

〔Example〕

FIG. 1 shows a semiconductor memory device manufactured by applying the present invention, and FIG. 2 shows a cross-sectional view for explaining one embodiment of the method for manufacturing the semiconductor memory device according to the present invention. In FIGS. 1 and 2, the same or equivalent parts as in FIG. 6 are given the same reference numerals.

First, this embodiment will be explained using FIGS. 2a to 2g. FIGS. 2a to 2e are cross-sectional views for explaining the element isolation process. FIG. 2a is a cross-sectional view showing a mask pattern on a wafer for thermal oxidation for device isolation.
A three-layer structure is used.

Next, using this thermal oxidation mask pattern, P ⁺ impurities are selectively implanted and diffused to invert and
A P ⁺ region 9 is provided as an impurity diffusion region for preventing parasitic effects (FIG. 2b).

Next, by evaporating Si ₃ N ₄ and etching the entire surface, the nitride film Si ₃ N ₄ 15 remains even after etching because it is thickly deposited only at the stepped portions (Fig. 2c), and this nitride film is Using the film Si ₃ N ₄ 15, i.e. using the framed process, the oxide film SiO ₂ 12
By performing thermal oxidation using the core as a core, an element isolation insulating film 8 is formed and an impurity diffusion region is formed.
The P ⁺ region 9 is extended to form a P ⁺ region 9 as a high concentration region (Fig. 2 d), and a nitride film Si ₃ N ₄ 13, 15,
By removing the oxide films SiO ₂ 12 and 14 (FIG. 2e), the pattern shown in FIG. 1 is obtained.

Next, after forming the gate electrode 3 and gate insulating film 4 (FIG. 2 f), selective N By implanting and diffusing ⁺ impurities, N ⁺ region 7 can be formed partially surrounded by P ⁺ region 9 (FIG. 2g). FIG. 2g clearly shows the differences between FIGS. 1 and 2.

As a high concentration region formed in this way,
The concentration of the P ⁺ layer 9 is 1 higher than the concentration of the semiconductor substrate 1.
It is best to set it to a value higher than 10 ¹⁴ P to 10 ¹⁸ /cm ³ . Further, it is preferable to use a low dielectric constant material such as PSG for the passivation film that will be formed later in the semiconductor memory device shown in FIG.

The above-mentioned soft error occurs when the electrons in the electron-hole pairs generated when radiation such as alpha rays enters the chip are collected in the N ⁺ regions 6 and 7, which act as charge storage regions and bit lines, respectively. caused by being caused. In other words, before the α rays that enter the chip lose energy and stop, they generate many electron-hole pairs along their range, and the depletion layer 1
The electron-hole pairs generated within 0 and 11 are immediately separated by the electric field inside the depletion layer, the electrons are collected in the N ⁺ regions 6 and 7, and the holes flow down through the semiconductor substrate 1. Furthermore, the electron-hole pairs generated inside the N ⁺ regions 6 and 7 do not contribute to the increase or decrease of electrons at all because they are recombined, and the electron-hole pairs generated inside the semiconductor substrate 1 are Depletion layer 1 due to diffusion
Only the electrons that have reached 0 and 11 will be collected in the N ⁺ regions 6 and 7 and cause soft errors, while the others will be recombined within the semiconductor substrate 1.

Therefore, in this embodiment, by surrounding N ⁺ region 7 with P ⁺ region 9 having a higher concentration than semiconductor substrate 1, the following characteristics are produced.

The width of depletion layer 11 formed at the interface between N ⁺ region 7 and P ⁺ region 9 becomes smaller, and the capacitance of N ⁺ region 7 becomes larger.

Since a portion of N ⁺ region 7 is formed within P ⁺ region 9 , electrons diffused from semiconductor substrate 1 are recombined in P ⁺ region 9 and do not reach N ⁺ region 7 .

Since a potential barrier against electrons is formed at the interface between semiconductor substrate 1 and P ⁺ region 9, electrons with low energy among the electrons diffused from semiconductor substrate 1 are not allowed to pass through.

According to the described point, the difference in the number of electrons corresponding to "0" and "1" accumulated in the N ⁺ region 7 becomes large, and there is a margin for electrons generated by incidence of α rays etc. be able to. Furthermore, according to the points described above, electrons can be prevented from diffusing into the N ⁺ region 7, and the occurrence of soft errors can be eliminated.

Note that in this embodiment, the N ⁺ region 7 as a bit line
In this example, the P ⁺ region 9 is formed to surround the sense amplifier's N ⁺ region and the peripheral circuitry.
The same applies to the N ⁺ region. Furthermore, although this example is applied to a dynamic type,
In addition to being similarly applicable to static type devices, the present invention can also be applied to cases where an N channel is a P channel, and can be applied to both MOS devices and bipolar devices.

Examples of memory cells manufactured by applying the present invention housed in a package are shown in FIGS. 3 to 5.
The material constituting the package in each figure is a conventionally known material, and there is no need for it to be a material with a low alpha particle emission rate, and an alpha particle prevention film on the chip surface is not required.

FIG. 3 shows the case where the device is housed in a ceramic package, FIG. 4 shows the case where it is housed in a resin mold package, and FIG. 5 shows the case where it is housed in a flip-chip method. 3 to 5, 21 is a memory chip, 22 is a bonding wire, 23 is an external lead, 24 is a ceramic base, 25 is a lid, 26 is a frame, and 27 is a resin. Although not shown here, by applying the present invention, even when the chip is housed in a SOJ, ZIP, or module type package, there is no need to use an alpha particle prevention film on the chip surface or a special packaging material. Similarly, it is possible to reduce the number of manufacturing steps and the cost of the manufacturing process.

〔Effect of the invention〕

As explained above, the present invention provides a semiconductor memory device in which a region of a second conductivity type is formed as a bit line on a semiconductor substrate of a first conductivity type. Since the high concentration regions of the first conductivity type were formed without increasing the number of steps, there is a margin for electrons generated by the incidence of alpha rays, etc., and each region of the second conductivity type is This has the effect that it is possible to obtain a semiconductor memory device that prevents electrons from diffusing and prevents malfunctions caused by the incidence of radiation such as alpha rays.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing a semiconductor memory device manufactured by applying the present invention, FIG. 2 is a cross-sectional view showing an embodiment of the method for manufacturing a semiconductor memory device according to the present invention, and FIGS. The figure is a block diagram showing an example in which memory cells manufactured by applying the present invention are housed in a package, and FIG. 6 is a sectional view showing a conventional semiconductor memory device. 1... Semiconductor substrate, 2, 3... Gate electrode, 4
...Gate insulating film, 5...Interlayer insulating film, 6,7...
...N ⁺ region, 8...element isolation insulating film, 9...P ⁺
Region, 10, 11... depletion layer, T1... power supply terminal, T2... connection terminal.

Claims (1)

[Scope of Claims] 1. A first impurity diffusion region of a second conductivity type forming a bit line formed on a substrate of a first conductivity type; A semiconductor memory device having a second impurity diffusion region of one conductivity type and having a higher concentration than the substrate, wherein the second impurity diffusion region is formed by the following steps. A method for manufacturing a storage device. (a) Step of forming an impurity diffusion region using a thermal oxidation prevention pattern provided on the substrate as a mask. (b) A step in which a film is formed on the front surface and then etched to form sidewall portions at the stepped portions of the pattern. (c) Perform thermal oxidation to form an inter-element isolation insulating film on the substrate surface where the pattern and sidewall portion are not provided, and at the same time, the impurity diffusion region is extended and diffused by this thermal oxidation, and a second impurity diffusion region is formed. Steps to become. 2. Manufacturing a semiconductor memory device according to claim 1, wherein the concentration of the second impurity diffusion region is in the range of 10 ¹⁴ to 10 ¹⁸ /cm ³ , which is one or more orders of magnitude higher than the substrate concentration. Method.