JPH0544822B2 - - Google Patents
Info
- Publication number
- JPH0544822B2 JPH0544822B2 JP60062605A JP6260585A JPH0544822B2 JP H0544822 B2 JPH0544822 B2 JP H0544822B2 JP 60062605 A JP60062605 A JP 60062605A JP 6260585 A JP6260585 A JP 6260585A JP H0544822 B2 JPH0544822 B2 JP H0544822B2
- Authority
- JP
- Japan
- Prior art keywords
- susceptor
- thermostat
- heater
- temperature
- wafer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
- H10P72/04—Apparatus for manufacture or treatment
- H10P72/0431—Apparatus for thermal treatment
- H10P72/0432—Apparatus for thermal treatment mainly by conduction
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
- C23C16/46—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for heating the substrate
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
- C23C16/50—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges
Landscapes
- Chemical & Material Sciences (AREA)
- Engineering & Computer Science (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Materials Engineering (AREA)
- Mechanical Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Physics & Mathematics (AREA)
- Plasma & Fusion (AREA)
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は、プラズマCVD装置に係り、特に複
数枚のウエハを同時に成膜処理するバツチ式プラ
ズマCVD装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a plasma CVD apparatus, and particularly to a batch-type plasma CVD apparatus that processes a plurality of wafers at the same time.
従来技術を第１図、第２図により説明する。 The prior art will be explained with reference to FIGS. 1 and 2.
第１図、第２図で、複数枚のウエハ（図示省
略）が一方の面に同時に載置されるサセプタ１０
の他方の面には、円板状のヒータ１１が複数個配
設されている。ヒータ１１は、それぞれ並列回路
に結線され電源（図示省略）に接続されている。
なお、ヒータ１１は、その外側をセラミツクで被
覆されており、内蔵されている電熱用抵抗線は、
電気的にも、また、外気からも絶縁されている。 In FIGS. 1 and 2, a susceptor 10 on which multiple wafers (not shown) are simultaneously placed on one surface.
A plurality of disc-shaped heaters 11 are arranged on the other surface of the disc. The heaters 11 are each connected to a parallel circuit and connected to a power source (not shown).
The outside of the heater 11 is covered with ceramic, and the built-in resistance wire for electric heating is
It is electrically and insulated from the outside air.
サセプタ１０の一方の面に複数枚同時に載置さ
れたウエハは、サセプタ１０がヒータ１１により
加熱されることで昇温され、その後、例えば、電
源をON−OFF制御することで所定温度に保持さ
れる。また、ウエハの温度が所定温度に達した時
点で、成膜処理が実施される。 A plurality of wafers placed simultaneously on one surface of the susceptor 10 are heated by heating the susceptor 10 with the heater 11, and then the temperature is raised, and then, for example, the temperature is maintained at a predetermined temperature by controlling the power supply on and off. Ru. Further, a film forming process is performed when the temperature of the wafer reaches a predetermined temperature.
このようなプラズマCVD装置は、、次のような
欠点があつた。 Such plasma CVD equipment has the following drawbacks.
(1) ヒータ容量のばらつきに起因するサセプタの
位置による温度不均一が生じ、、このため成膜
処理時のウエハ温度が不均一になるため、ウエ
ハの成膜速度を均一化きない。(1) Temperature non-uniformity occurs depending on the position of the susceptor due to variations in heater capacity, and as a result, the wafer temperature during film formation becomes non-uniform, making it impossible to equalize the film formation rate on the wafer.
(2) サセプタ、つまり、ウエハの温度制御用とし
て大容量の制御装置が必要である。(2) A large-capacity control device is required to control the temperature of the susceptor, that is, the wafer.
〔発明の目的〕
本発明は、成膜処理時のウエハ温度を均一化す
ることで、ウエハの成膜速度を均一化できるプラ
ズマCVD装置を提供することにある。[Object of the Invention] An object of the present invention is to provide a plasma CVD apparatus that can uniformize the wafer deposition rate by equalizing the wafer temperature during film deposition processing.
本発明のは、一方の面にウエハが載置されるサ
セプタと、サセプタの他方の面に配設した複数個
のヒータと、サセプタと複数個のヒータとの間に
それぞれ空間を形成し、該それぞれの空間にサセ
プタおよびヒータと絶縁して設けたサーモスタツ
トと、サセプタに螺合して設け、サーモスタツト
の接点部に電気絶縁材を介して当接させ、複数個
のヒータの容量のばらつきに対応してサーモスタ
ツトのON−OFFタイミングを調節する調節ネジ
とを具備し、サーモスタツトの一方を電源に、他
方をヒータの電熱用抵抗線に接続して成ることを
特徴とするもので、ヒータ容量のばらつきをなく
しサセプタの温度を均一にして、成膜処理時のウ
エハ温度を均一化し、ウエハの成膜速度を均一化
できるようにしたものである。
The present invention includes a susceptor on which a wafer is placed on one surface, a plurality of heaters arranged on the other surface of the susceptor, and a space between the susceptor and the plurality of heaters. A thermostat is installed in each space insulated from the susceptor and heater, and the thermostat is screwed onto the susceptor, and the contact part of the thermostat is brought into contact with an electrically insulating material to prevent variations in the capacity of multiple heaters. The thermostat is equipped with an adjustment screw for adjusting the ON-OFF timing of the thermostat, and is characterized in that one side of the thermostat is connected to a power source and the other side is connected to a resistance wire for electric heating of a heater. This eliminates variations in capacitance, makes the temperature of the susceptor uniform, and makes the wafer temperature uniform during the film forming process, thereby making it possible to make the film forming rate of the wafer uniform.
本発明の一実施例を第３図〜第５図により説明
する。
An embodiment of the present invention will be described with reference to FIGS. 3 to 5.
第３図〜第５図で、複数枚のウエハ（図示省
略）が一方の面に同時に載置されるサセプタ１０
の他方の面には、円板状のヒータ１１が配設され
ている。サセプタ１０とヒータ１１との間には、
ON−OFF作動する電気接点、、例えば、バイメ
タルサーモスタツト（以下、サーモスタツトと
略）１２が電気絶縁材（以下、絶縁材と略）１３
でサセプタ１０と電気的に絶縁されて設けられて
いる。サーモスタツト１２の接点部は、サセプタ
１０とヒータ１１と絶縁材１３とで形成された空
間１４にある。サーモスタツト１２のON−OFF
タイミングを調節する調節ネジ１５がサセプタ１
０に螺合され、その先端は、電気絶縁物１６を介
しサーモスタツト１２の接点部に当接されてい
る。また、サーモスタツト１２を構成する導電材
料板１７は、電源（図示省略）に接続され、バイ
メタル１８は、ヒータ１１の電熱用抵抗線１９に
接続され、電熱用抵抗線１９は、電源に接続され
ている。 3 to 5, a susceptor 10 on which a plurality of wafers (not shown) are simultaneously placed on one surface
A disc-shaped heater 11 is disposed on the other surface of the disc. Between the susceptor 10 and the heater 11,
An electrical contact that operates ON-OFF, for example, a bimetal thermostat (hereinafter abbreviated as a thermostat) 12 is connected to an electrical insulating material (hereinafter abbreviated as an insulating material) 13
It is provided to be electrically insulated from the susceptor 10. A contact portion of the thermostat 12 is located in a space 14 formed by the susceptor 10, the heater 11, and the insulating material 13. ON-OFF of thermostat 12
The adjustment screw 15 that adjusts the timing is the susceptor 1
0, and its tip is brought into contact with a contact portion of the thermostat 12 via an electrical insulator 16. Further, the conductive material plate 17 constituting the thermostat 12 is connected to a power source (not shown), the bimetal 18 is connected to the electric heating resistance wire 19 of the heater 11, and the electric heating resistance wire 19 is connected to the power source. ing.
サセプタ１０の一方の面に複数枚同時に載置さ
れたウエハは、サセプタ１０がヒータ１１により
加熱されることで昇温され、その後、サーモスタ
ツト１２がON−OFF作動すること所定温度に保
持される。この場合、サーモスタツト１２のON
−OFFタイミングは、ヒータ１１の容量のばら
つきに対応し、調節ネジ１５により調節される。
また、ウエハの温度が所定温度に達した時点で成
膜処理が実施される。 A plurality of wafers placed simultaneously on one surface of the susceptor 10 are heated by heating the susceptor 10 by the heater 11 to raise the temperature, and then maintained at a predetermined temperature by turning the thermostat 12 ON and OFF. . In this case, turn on thermostat 12.
The -OFF timing is adjusted by the adjustment screw 15 in response to variations in the capacity of the heater 11.
Further, the film forming process is performed when the temperature of the wafer reaches a predetermined temperature.
本実施例のようなプラズマCVD装置では、次
のような効果が得られる。 A plasma CVD apparatus such as this embodiment provides the following effects.
(1) サーモスタツトのON−OFFタイミングがヒ
ータ容量のばらつきに対応し調節されるため、
ヒータの容量のばらつきに起因するサセプタの
位置による温度不均一を防止できる。(1) Since the ON-OFF timing of the thermostat is adjusted to accommodate variations in heater capacity,
It is possible to prevent temperature non-uniformity due to the position of the susceptor due to variations in the capacity of the heater.
(2) サセプタの位置による温度が均一になるた
め、成膜処理時のウエハの温度が均一化され、
したがつて、ウエハの成膜速度を均一化でき
る。(2) Since the temperature is uniform depending on the position of the susceptor, the temperature of the wafer during the film formation process is uniform.
Therefore, the film formation rate on the wafer can be made uniform.
(3) サセプタ、つまり、ウエハの温度制御は、サ
ーモスタツトをON−OFF作動することで行え
るため、温度制御装置を不用にできる。(3) The temperature of the susceptor, that is, the wafer, can be controlled by turning the thermostat ON and OFF, making a temperature control device unnecessary.
本発明によれば、ヒータ容量のばらつきの影響
を排除きるので、サセプタの温度が均一になり、
成膜処理時のウエハ温度が均一化され、ウエハの
成膜速度を均一化できるという効果がある。
According to the present invention, since the influence of variations in heater capacity can be eliminated, the temperature of the susceptor becomes uniform, and
This has the effect that the wafer temperature during the film forming process can be made uniform, and the film forming rate of the wafer can be made uniform.
第１図は、ヒータ配設側からみた従来のサセプ
タの平面図、第２図は、第１図のイ−イ視断面
図、第３図は本発明によるプラズマCVD装置の
一実施例を示すもので、ヒータ配設側からみたサ
セプタの部分平面図、第４図は、第３図のロ−ロ
視断面図、第５図は、第４図の部分拡大断面図で
ある。
１０……サセプタ、１１……ヒータ、１２……
サーモスタツト、１３……電気絶縁材、１４……
空間、１５……調節ネジ。
FIG. 1 is a plan view of a conventional susceptor seen from the heater installation side, FIG. 2 is a cross-sectional view taken along line A in FIG. 1, and FIG. 3 shows an embodiment of the plasma CVD apparatus according to the present invention. FIG. 4 is a partial plan view of the susceptor seen from the side where the heater is disposed, FIG. 4 is a cross-sectional view taken from the roller in FIG. 3, and FIG. 5 is a partial enlarged cross-sectional view of FIG. 4. 10...Susceptor, 11...Heater, 12...
Thermostat, 13... Electrical insulation material, 14...
Space, 15...adjustment screw.
Claims (1)
タと、 前記サセプタと前記複数個のヒータとの間にそ
れぞれ空間を形成し、該それぞれの空間に前記サ
セプタおよび前記ヒータと絶縁して設けたサーモ
スタツトと、 前記サセプタに螺合して設け、前記サーモスタ
ツトの接点部に電気絶縁材を介して当接させ、前
記複数個のヒータの容量のばらつきに対応して前
記サーモスタツトのON−OFFタイミングを調節
する調節ネジとを具備し、 前記サーモスタツトの一方を電源に、他方を前
記ヒータの電熱用抵抗線に接続して成ることを特
徴とするプラズマCVD装置。[Claims] 1. A susceptor on which a wafer is placed on one surface, a plurality of heaters arranged on the other surface of the susceptor, and a space between the susceptor and the plurality of heaters. a thermostat provided in each space insulated from the susceptor and the heater; a thermostat provided screwed onto the susceptor and brought into contact with a contact portion of the thermostat via an electrical insulating material; and an adjustment screw for adjusting ON-OFF timing of the thermostat in response to variations in capacity of the plurality of heaters, one of the thermostats being used as a power source and the other being used as a resistance wire for heating the heaters. A plasma CVD device characterized by being connected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60062605A JPS60220929A (en) | 1985-03-27 | 1985-03-27 | Plasma cvd apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60062605A JPS60220929A (en) | 1985-03-27 | 1985-03-27 | Plasma cvd apparatus |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60220929A JPS60220929A (en) | 1985-11-05 |
| JPH0544822B2 true JPH0544822B2 (en) | 1993-07-07 |
Family
ID=13205117
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60062605A Granted JPS60220929A (en) | 1985-03-27 | 1985-03-27 | Plasma cvd apparatus |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60220929A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5075256A (en) * | 1989-08-25 | 1991-12-24 | Applied Materials, Inc. | Process for removing deposits from backside and end edge of semiconductor wafer while preventing removal of materials from front surface of wafer |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55121649A (en) * | 1979-03-14 | 1980-09-18 | Pioneer Electronic Corp | Cvd device |
-
1985
- 1985-03-27 JP JP60062605A patent/JPS60220929A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60220929A (en) | 1985-11-05 |
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