JPH0546146B2 - - Google Patents

Description

Detailed Description of the Invention Technical Field The present invention relates to a signal processing device for a so-called video format signal having a configuration similar to that of a normal TV signal, and in particular to a signal processing device for a video format signal whose content is information obtained from a movie film source. The present invention relates to a signal processing device that processes video format signals to form non-interlaced video format signals that have a higher vertical resolution than conventional interlaced formats and can perform more effective video reproduction.

BACKGROUND TECHNOLOGY The so-called video format signal includes horizontal and vertical synchronization signals, blanking signals, etc.
It has a similar structure to a TV signal, and refers to a signal that carries video information that can be reproduced on a cathode ray tube using so-called interlaced scanning.

In order to record and reproduce the contents of a movie film source on a video disc or videotape, the contents of the movie film source must be first converted into a video format signal based on the NTSC system or the like.

However, since the frame advance speed of a normal movie film is 24 frames per second and the number of frames of an NTSC video format signal is 30 per second, it is impossible to make each frame of a video format signal correspond one-to-one. Have difficulty. Therefore, a so-called 2-3 pulldown method is often adopted in which two fields correspond to odd frames of a movie film and three fields correspond to even frames. In other words, each frame of the movie film is associated with a frame group, and the number of frames in each frame group is varied as appropriate to eliminate the time lag caused by the difference in frame feed speed and frame frequency.

On the other hand, video format signals based on standard formats such as the NTSC format are obtained by interlaced scanning, which causes so-called line flicker, which causes flickering in a fine horizontal striped pattern. There are problems with visibility. Therefore, various methods have been considered to convert the scanning line structure of a video format signal into a structure obtained by line sequential scanning. A so-called field memory method that performs inter-field insertion in which a portion corresponding to a scanning line is inserted is well known.

In conventional signal processing devices that perform signal processing of video format signals using this field memory method, when converting the scanning line structure of a video format signal whose content is information obtained from a motion picture film source, Since interpolation may be performed using field information of different frames, a problem arises in that an image that cannot actually exist is formed when changing a scene or the like.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned points, and provides a signal processing method capable of successfully converting the scanning line structure of a video format signal containing information obtained from a motion picture film source. The purpose is to provide equipment.

In order to achieve the above object, a signal processing device for a video format signal according to the present invention delays a video format signal obtained from a movie film source by a first period that differs from one field period by 1/2 horizontal scanning period. a first signal delay means for
and a second signal delay means for delaying the output of the first execution delay means by a second period which is smaller than the one frame period by the first period, the difference between the video format signal and the output of the second signal delay means. Based on the period during which the value obtained by performing the predetermined calculation processing of generating a changing control signal, selecting one of the input video format signal and the output of the second signal delay means according to the control signal, and selecting the output of the first signal delay means and the signal selection means; The time axis of the output corresponding to each horizontal scanning line is compressed to 1/2, and the output is alternately output every 1/2 horizontal scanning period.

Further, predetermined calculation processing is performed on the difference between the video format signal and the output of the second signal delaying means of two unit interval signals each consisting of a portion occurring in one field period, and the output of the first signal delaying means. The signal selection means may select the one having the smaller value.

Further, a code that sequentially changes every field period is set based on a period in which the value obtained by performing a predetermined calculation process on the difference between the video format signal and the output of the second signal delay means is equal to or less than a predetermined value. It is also possible to add it to at least one of the signal delay means and the signal selection means.

Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In FIG. 1, a video format signal is supplied to input terminal IN. This video format signal is, for example, a digital signal obtained by sampling this video format signal at a predetermined period and converting it into digital data as pixel data corresponding to sample values obtained. This video format signal is supplied to an arithmetic circuit 1, a delay circuit 2, and a signal selection circuit 3. The delay circuit 2 consists of a FIFO (first in, first out) type memory with a storage capacity capable of storing video format signals generated within, for example, 262H (262 horizontal scanning periods), and sequentially writes the video format signals and also stores the video format signals only 262H after the write timing. The configuration is such that the video format signals are delayed by 262H by sequentially reading them out at delayed timing.
The video format signal delayed by 262H by the delay circuit 2 is supplied to the delay circuit 4 and the double speed conversion circuit 5. For example, the delay circuit 4
It consists of a FIFO type memory having a storage capacity capable of storing a video format signal generated within 263H, and is configured to delay the video format signal by 263H in the same manner as the delay circuit 2.
Further, the double speed conversion circuit 5 has two line memories capable of storing all pixel data corresponding to one horizontal scanning line of a video format signal, for example.
The pixel data corresponding to each horizontal scanning line of the video format signal supplied to the two line memories is alternately written, and the data stored in the two line memories is alternately read out twice at twice the writing speed. The configuration is such that it is output as follows.

The video format signal delayed by 263H by the delay circuit 4 is supplied to the arithmetic circuit 1 and the signal selection circuit 3. The arithmetic circuit 1 calculates the difference for each pixel data between the input video format signal and the signal obtained by delaying this input video format signal by one frame period by the delay circuits 2 and 4, and calculates the difference for each pixel data. The configuration is such that the maximum value of the absolute value of the difference between each pixel data is obtained for each line, the obtained maximum values are added, and the obtained data is output. The output data of this arithmetic circuit 1 is supplied to a latch circuit 6. The latch circuit 6 includes a synchronous separation circuit (not shown).
A vertical synchronizing signal v separated from the video format signal is supplied by the latch circuit 6, and the output data of the arithmetic circuit 1 is stored and held in the latch circuit 6 by this vertical synchronizing signal v. The output data of this latch circuit 6 is supplied to a comparator 7. The comparator 7 compares the output data of the latch circuit 6 with a predetermined reference value, for example, and outputs a low level signal when the output data of the latch circuit 6 is smaller than the reference value. The output of this comparator 7 is supplied to a selection control circuit 8. The selection control circuit 8 has a counter that is reset by a low level signal output from the comparator 7 and counted up by a vertical synchronization signal v, for example.
Based on the output of this counter, a signal whose level changes according to a predetermined rule every other field period is output as a selection control signal.
The output of this selection control circuit 8 is supplied to the signal selection circuit 3. The signal selection circuit 3 is configured to selectively output the input video format signal when the selection control signal is at a low level, and selectively output the output of the delay circuit 4 when the selection control signal is at a high level. It is becoming. The output of this signal selection circuit 3 is supplied to a double speed conversion circuit 9. The double speed conversion circuit 9 is
It is configured similarly to the double speed conversion circuit 5. The outputs of these double speed converting circuits 5 and 9 are connected to the changeover switch 1.
0. The output of a switching control circuit 11 is supplied to the switching switch 10 . The switching control circuit 11 is supplied with a horizontal synchronization signal h separated from the input video format signal by a synchronization separation circuit (not shown). The switching control circuit 11 is
For example, the switching control signal is configured to output a switching control signal that is synchronized with the horizontal synchronizing signal h and is inverted at half the cycle of the horizontal synchronizing signal h. This switching control circuit 11
The output of is supplied to the changeover switch 10. For example, the changeover switch 10 selectively outputs the output of the double speed conversion circuit 5 when the changeover control signal is at a low level, and selectively outputs the output of the double speed conversion circuit 9 when the changeover control signal is at a high level. It is structured as follows. The output of this changeover switch 10 is the output terminal
Supplied to OUT.

In the above configuration, the input video format signal is divided into fields a, a', a,
Consisting of b, b', c, c', c, d, d', e...
Frame A of a movie film corresponds to two odd fields a and an even field a', and frame B corresponds to an odd field b and an even field b'. In other words, after frame A is scanned by one frame by interlaced scanning, it is scanned by one additional field.

In the same way, for frames C and D, repeat scanning 3 times and 2 times alternately to obtain fields C,
c', d, and d' are obtained. Therefore, this video format signal changes regularly every five field periods.

When the input video format signal α as shown in FIG. 3A is delayed by 262H by the delay circuit 2, the video format signal β as shown in FIG.
is obtained. When the output of the delay circuit 2 is delayed by 263H by the delay circuit 4, a video format signal γ as shown in FIG. 3C is obtained.

Since the input video format signal α is subjected to conversion processing with a period of 5 field periods, there is a difference between the input video format signal α and the signal obtained by delaying the input video format signal α by one frame period. One field period T that coincides with each other exists in five field periods. During this period T, the output of the arithmetic circuit 1 becomes "0", so by setting the reference value in the comparator 7 to a value slightly larger than "0", the output of the calculation circuit 1 becomes "0".
At this point, a reset signal consisting of a low level signal is supplied from the comparator 7 to the selection control circuit 8.

Here, if it is assumed that the selection control circuit 8 generates a switching command signal δ whose level changes as shown in FIG. The circuit 3 outputs a video format signal ε in the field order as shown in FIG. 3E. The video format signal ε outputted from the signal selection circuit 3 and the video format signal β outputted from the delay circuit 2 are a pair of signals obtained by interlacing scanning of the same frame. The output of the delay circuit 2 and the output of the signal selection circuit 3 are supplied to the double-speed conversion circuits 5 and 9, and the output of the signal selection circuit 3 and the output of the delay circuit 2 are halved from the double-speed conversion circuits 5 and 9. The signal obtained by axial compression is repeatedly output for each line. The outputs of these double speed conversion circuits 5 and 9 are changed to 1H by the changeover switch 10.
Since the signals are taken out alternately at a period of 1/2 and inter-field insertion is performed to form a non-interlaced video format signal, the scanning line structure can be converted satisfactorily.

FIG. 4 is a block diagram showing another embodiment of the present invention, which includes a delay circuit 2, a signal selection circuit 3, a delay circuit 4, double speed conversion circuits 5 and 9, a changeover switch 10,
The switching command signal generating circuit 11 is connected in the same way as the device shown in FIG. However, in this example, the delay circuit 2 and the signal selection circuit 3 include the delay circuit 1.
A video format signal delayed by 5 is provided. The delay circuit 15, like the delay circuit 4, is configured to delay the input video format signal by 263H. Further, the output of this delay circuit 15 is supplied to an arithmetic circuit 16. The arithmetic circuit 16 is also supplied with an input video format signal. This arithmetic circuit 16 calculates the difference for each pixel data between the input video format signal and the signal obtained by delaying this input video format signal by 263H by the delay circuit 15, and calculates the difference for each pixel data. The configuration is such that the maximum value of the absolute value of the difference for each pixel data is obtained, the obtained maximum values are added, and the obtained data is output. The output data of this arithmetic circuit 16 is supplied to a latch circuit 17. The latch circuit 17 is supplied with a vertical synchronization signal v separated from the video format signal by a synchronization separation circuit (not shown), and the output data of the arithmetic circuit 16 is latched by this vertical synchronization signal v. circuit 17
is stored in memory. The output of this latch circuit 17 is supplied to a comparator 18 and a latch circuit 19. A vertical synchronizing signal v is supplied to the latch circuit 19, and the output data of the latch circuit 17 is stored and held in the latch circuit 19 by this vertical synchronizing signal v. Comparator 18 compares the outputs of these latch circuits 17 and 19 and outputs a result depending on the comparison result. The output of this comparator 18 is supplied to the signal selection circuit 3 as a selection control signal.

In the above configuration, similarly to the device shown in FIG. 1, the input of the delay circuit 2 and the output of the delay circuit 4 are selectively output by the signal selection circuit 3 to the video format signal output from the delay circuit 2. An inter-field insertion is made between one of the fields. Here, the video format signal α supplied to the input terminal IN
Assuming that the three consecutive fields are x, y, and z as shown in FIG. Figures B to D
The results are shown below. The field inserted into field y of the video format signal output from delay circuit 2 becomes one of field z at the input of delay circuit 2 and field x of the video format signal output from delay circuit 4. .

At this time, the latch circuit 19 stores the difference in pixel data for each horizontal scanning line between the input and output of the delay circuit 15 two fields before the field y is output from the delay circuit 2, that is, the fields x and y. The data obtained by adding the maximum absolute value of is stored and held. Further, the latch circuit 17 records and holds data obtained by adding the maximum absolute value of the difference for each pixel data for each horizontal scanning line between fields y and z. The outputs of these latch circuits 19 and 17 are the comparator 1
8, a selection control signal is generated according to the comparison result, and is supplied to the signal selection circuit 3.

Now, if fields x and y correspond to the same frame of a movie film, the difference between each pixel data of fields x and y will be close to zero, and the output data of latch circuit 19 will be the same as that of latch circuit 17. It will be smaller than the output data. Therefore, if a high level signal is outputted from the comparator 18 at this time, the field x of the video format signal γ outputted from the delay circuit 4 is selectively outputted from the signal selection circuit 3, and the motion picture film is Video format signals obtained from the same frame are inserted between fields to form a non-interlaced video format signal. Also, if fields y and z correspond to the same frame of a movie film, then fields y and z
The difference between each pixel data of is close to zero,
The output data of the latch circuit 17 is
is smaller than the output data of Therefore, if a low level signal is outputted from the comparator 18 at this time, the field z of the video format signal ζ outputted from the delay circuit 15 is selectively outputted from the signal selection circuit 3, and the field z of the video format signal ζ outputted from the delay circuit 15 is selectively outputted from the signal selection circuit 3. Video format signals obtained from the same frame are inserted between fields to form a non-interlaced video format signal. Therefore, in this example as well, the scanning line structure is well converted as in the device of FIG. 1, and since no fixed reference value is used in the comparator 18, the conversion is Dynamic movement is possible.

FIG. 6 is a block diagram showing still another embodiment of the present invention, in which each part is the same as in FIG. It is configured similarly to the device. The field number addition circuit 21 is reset by, for example, a low-level reset signal output from the comparator 7, and is also reset by the vertical synchronization signal v.
It has a counter that counts up according to the delay circuit 2, and the output data of this counter is superimposed on a portion corresponding to a predetermined horizontal scanning line within the vertical retrace period of the video format signal output from the delay circuit 2. There is.

In the above configuration, a different code is added to each field within one period of the non-interlaced video format signal, which has a period of 5 field periods, which is derived to the output terminal OUT, making digital processing easy. A non-interlaced video format signal can be obtained.

In the above embodiment, the delay time of delay circuit 2 is 262H, and the delay times of delay circuits 4 and 15 are 263H. and 15
The delay time may be set to 262H.

Furthermore, in the above embodiment, the field number addition circuit 21 is connected between the delay circuit 2 and the double speed conversion circuit 5, but the field number addition circuit 21 is connected between the signal selection circuit 3 and the double speed conversion circuit 9. Alternatively, it may be connected both between the delay circuit 2 and the double speed conversion circuit 5 and between the signal selection circuit 3 and the double speed conversion circuit 9.

Effects of the Invention As detailed above, the signal processing device for video format signals according to the present invention includes a first signal delay unit that delays the video format signal by a first period that is different from one field period by 1/2 horizontal scanning period. and a second signal delay means for delaying the first signal delay means and the output by a second period which is smaller than the one frame period by the first period. Based on the period in which the value obtained by performing predetermined calculation processing of the difference is less than or equal to the predetermined value, the process is performed every other field period according to a rule according to the correspondence relationship between the frames of the movie film source and the field of the video format signal. The signal selection means selects one of the video format signal and the output of the second signal delay means in accordance with the control signal, and selects the output of the first signal delay means and the signal selection means. The structure is such that the time axis of the output corresponding to each horizontal scanning line is compressed to 1/2 and output alternately every 1/2 horizontal scanning period, so the video obtained from the same frame of the movie film source is By inserting the format signals between fields, a non-interlaced video format signal can be obtained, and the scanning line structure can be converted favorably.

Further, predetermined calculation processing is performed on the difference between the video format signal and the output of the second signal delaying means of two unit interval signals each consisting of a portion occurring in one field period, and the output of the first signal delaying means. By having the signal selection means select the one with the smaller value obtained from the same frame, non-interlacing can be achieved by inserting between fields of video format signals obtained from the same frame of a movie film source. A video format signal can be obtained, and the scanning line structure can be converted well.

Further, a code that sequentially changes every field period is set based on a period in which the value obtained by performing a predetermined calculation process on the difference between the video format signal and the output of the second signal delay means is equal to or less than a predetermined value. By adding this to at least one of the signal delay means and the signal selection means, a non-interlaced video format signal that is easy to digitally process can be obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a diagram showing the correspondence between frames of a movie film source and fields of a video format signal, and FIG. FIG. 4 is a timing chart showing the operation of each part of the apparatus; FIG. 5 is a timing chart showing the operation of each part of the apparatus of FIG. 4; FIG.
The figure is a block diagram showing still another embodiment of the present invention. Explanation of symbols of main parts, 1...Arithmetic circuit, 2,
4, 15...Delay circuit, 3...Signal selection circuit,
5, 6... double speed conversion circuit, 8... selection control circuit,
10... Changeover switch.

Claims (1)

[Scope of Claims] 1. A signal processing device that performs signal processing of a video format signal whose content is information obtained from a movie film source, wherein one field period is defined as 1/2 horizontal scanning. a first signal delaying means for delaying the output by a first period which is different from the period; a second signal delaying means for delaying the output of the first signal delaying means by a second period smaller than the one frame period by the first period; Frames of the movie film source are determined every other field period based on a period in which the value obtained by performing a predetermined calculation process on the difference between the video format signal and the output of the second signal delaying means is equal to or less than a predetermined value. control signal generating means for generating a control signal that changes according to a rule depending on the correspondence relationship between the video format signal and the field; and a control signal generating means for generating the video format signal and the second signal delaying means according to the control signal and a signal selection means for selecting and outputting one of the outputs, compressing the time axis of the output of the first signal delay means and the output of the signal selection means corresponding to each horizontal scanning line to 1/2. A signal processing device for a video format signal which outputs signals alternately every 1/2 horizontal scanning period. 2 A signal processing device that performs signal processing of a video format signal whose content is information obtained from a movie film source, wherein the video format signal is processed in a first period that differs from one field period by 1/2 horizontal scanning period. a first signal delaying means for delaying the output of the first signal delaying means by a second period which is smaller than one frame period by the first period; The value obtained by performing a predetermined calculation process of the difference between the output of the first signal delay means and the output of the first signal delay means among the two unit interval signals consisting of the portions generated in one field period of each of the outputs of the second signal delay means is small. a signal selection means for selecting and outputting one of the signals, and compressing the time axis of the output of the first signal delay means and the output of the signal selection means corresponding to each horizontal scanning line to 1/2. A signal processing device for video format signals that outputs signals alternately every 2 horizontal scanning periods. 3. A sign that sequentially changes every field period based on a period in which a value obtained by performing a predetermined calculation process on the difference between the video format signal and the output of the second signal delaying means is equal to or less than a predetermined value. 3. The signal processing apparatus for a video format signal according to claim 1, further comprising code adding means added to at least one of said first signal delay means and said signal selection means.