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JPH0546982B2 - - Google Patents
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JPH0546982B2 - - Google Patents

Info

Publication number
JPH0546982B2
JPH0546982B2 JP61219373A JP21937386A JPH0546982B2 JP H0546982 B2 JPH0546982 B2 JP H0546982B2 JP 61219373 A JP61219373 A JP 61219373A JP 21937386 A JP21937386 A JP 21937386A JP H0546982 B2 JPH0546982 B2 JP H0546982B2
Authority
JP
Japan
Prior art keywords
wafer
storage
wafers
carrier
carriers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP61219373A
Other languages
Japanese (ja)
Other versions
JPS6376449A (en
Inventor
Tsutomu Takahashi
Takemasa Iwasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP61219373A priority Critical patent/JPS6376449A/en
Publication of JPS6376449A publication Critical patent/JPS6376449A/en
Publication of JPH0546982B2 publication Critical patent/JPH0546982B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/10Handling or holding of wafers, substrates or devices during manufacture or treatment thereof using carriers specially adapted therefor, e.g. front opening unified pods [FOUP]
    • H10P72/19Handling or holding of wafers, substrates or devices during manufacture or treatment thereof using carriers specially adapted therefor, e.g. front opening unified pods [FOUP] closed carriers
    • H10P72/1902Handling or holding of wafers, substrates or devices during manufacture or treatment thereof using carriers specially adapted therefor, e.g. front opening unified pods [FOUP] closed carriers specially adapted for a single substrate

Landscapes

  • Packaging Frangible Articles (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体の製造工程で用いられるウエハ
形状素材の処理、搬送及び保管などに使用するウ
エハキヤリヤ治具に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a wafer carrier jig used for processing, transporting, and storing wafer-shaped materials used in semiconductor manufacturing processes.

〔従来の技術〕[Conventional technology]

従来のウエハキヤリヤ14は、例えば特開昭59
−213142号公報(第5図参照)に示すように、丸
型(又は角型)のウエハ18を格納するための溝
15を約30本程度設けた一体型の構造からなる。
The conventional wafer carrier 14 is, for example, disclosed in Japanese Patent Application Laid-open No. 59
As shown in Japanese Patent No. 213142 (see FIG. 5), it has an integrated structure with about 30 grooves 15 for storing round (or square) wafers 18.

このため、一回の処理枚数が3枚又は11枚の装
置でウエハの加工を行う場合には、約30枚のウエ
ハを格納可能なキヤリヤ14に設けた溝15にウ
エハを3枚又は11枚ごとに分けて格納し、それぞ
れ搬送して保管する方法が採用されている。した
がつて、製造工程内に滞留しているウエハ枚数に
比較してキヤリヤ個数が多くなるため、搬送、保
管及び収納の各効率が低下する恐れがあつた。
Therefore, when processing wafers with a device that processes 3 or 11 wafers at a time, 3 or 11 wafers are placed in the groove 15 provided in the carrier 14, which can store approximately 30 wafers. A method is adopted in which each item is stored separately and transported and stored separately. Therefore, the number of carriers is larger than the number of wafers remaining in the manufacturing process, and there is a risk that the efficiency of transportation, storage, and storage may be reduced.

又使用されるウエハ18の直径は次第に大口径
化し、120〜200mmのものが主流になりつつある。
しかるに、半導体製造装置側の規格及びウエハ収
納効率の向上の見地から、ウエハ格納溝15のピ
ツチ16は、ウエハ18の直径の増大にかかわら
ず、約6mm程度の極めて小さい値に限定されてい
る。このため、従来のキヤリヤに対し、大径(直
径200mm)のウエハ18を人手によるピンセツト
作業で格納溝15に整列収納することは非常に困
難であるばかりでなく、ウエハ18を取出す場合
には、格納溝15の上方の領域17のみが作業領
域である。
Furthermore, the diameter of the wafer 18 used is gradually increasing, and 120 to 200 mm is becoming mainstream.
However, in view of the standards of semiconductor manufacturing equipment and the improvement of wafer storage efficiency, the pitch 16 of the wafer storage groove 15 is limited to an extremely small value of approximately 6 mm, regardless of the increase in the diameter of the wafer 18. For this reason, with conventional carriers, it is not only very difficult to align and store large-diameter (200 mm diameter) wafers 18 in storage grooves 15 using manual tweezers, but also when taking out wafers 18, Only the area 17 above the storage groove 15 is the working area.

さらに、次世代の半導体の製造プロセスは、サ
ブミクロンの加工精度が要求されるため、ウエハ
の搬送及び保管に際し、雰囲気中の塵あいによる
汚染保護が従来以上に要求される。しかし、従来
のキヤリヤでは、ウエハを収納するための開口部
を上向きに設け、ウエハを格納して保管すると共
に、取出す必要があるので、雰囲気中の塵あいに
よる汚染の機会は極めて高いという問題がある。
Furthermore, since next-generation semiconductor manufacturing processes require submicron processing precision, protection against contamination due to dust in the atmosphere is required more than ever when transporting and storing wafers. However, in conventional carriers, the opening for accommodating the wafers faces upwards, and the wafers must be stored and removed as well, so there is an extremely high chance of contamination due to dust in the atmosphere. be.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上記従来技術では、次世代の半導体製造プロセ
スにおけるウエハの大口径化及び処理枚数がプロ
セス装置ごとに大きく変化することへの対応、又
はウエハ表面を高清浄に保つて搬送と保管するこ
とへの対応が考慮されていないため、ウエハの格
納及び取出しに際し、該作業性、工程内のウエハ
収納効率及び塵埃汚染による歩留り低下などの問
題があつた。
The above-mentioned conventional technology is designed to cope with the large diameter of wafers in next-generation semiconductor manufacturing processes and the large changes in the number of wafers processed depending on the process equipment, or to keep the wafer surface highly clean during transportation and storage. Since this is not taken into consideration, there have been problems such as workability, in-process wafer storage efficiency, and reduced yield due to dust contamination when storing and taking out wafers.

本発明は上記にかんがみ、処理枚数が異なる装
置間におけるウエハの搬送、格納及び保管のそれ
ぞれの効率と作業性を向上させると共に、該搬
送、格納及び保管時のウエハ汚染を防止すること
ができるウエハキヤリヤ治具を提供することを目
的とする。
In view of the above, the present invention provides a wafer carrier that improves the efficiency and workability of wafer transportation, storage, and storage between devices that process different numbers of wafers, and prevents wafer contamination during the transportation, storage, and storage. The purpose is to provide jigs.

〔問題点を解決するための手段〕[Means for solving problems]

上記問題は、開口部を設けると共に、該開口部
の内周壁に二つのウエハ格納溝を設けた主キヤリ
ヤと、凹部を設けると共に、該凹部の内周壁に一
つのウエハ格納溝を設けた上部及び下部副キヤリ
ヤとからなり、該両副キヤリヤと前記主キヤリヤ
を互に重合可能に構成することに解決される。
The above problem is solved by a main carrier having an opening and two wafer storage grooves on the inner peripheral wall of the opening, and an upper part having a recess and one wafer storage groove on the inner peripheral wall of the recess. and a lower sub-carrier, and the two sub-carriers and the main carrier are configured to be mutually superimposed.

〔作用〕[Effect]

主キヤリヤに設けた開口部の内周壁に二つのウ
エハ格納溝を設けると共に、該両溝間の一部に仕
切壁を設けることにより、十分に余裕のある作業
空間を確保し、収納効率及び作業性を向上させる
ことができる。
By providing two wafer storage grooves on the inner circumferential wall of the opening provided in the main carrier, and providing a partition wall between the two grooves, a sufficient working space is secured and storage efficiency is improved. can improve sex.

上記キヤリヤを任意数だけ重ね合せると共に、
該キヤリヤの上・下部に一つの格納溝を有する
上・下部副キヤリヤをそれぞれ重ね合せることに
より、ウエハの搬送及び加工処理単位を自由に設
定できると共に、キヤリヤ内のウエハを作業雰囲
気中の塵あいによる汚染から保護することが可能
である。
By overlapping an arbitrary number of the above carriers,
By stacking upper and lower sub-carriers each having one storage groove above and below the carrier, the wafer transport and processing unit can be freely set, and the wafers in the carrier can be kept free from dust in the working atmosphere. It is possible to protect against contamination by

〔実施例〕〔Example〕

以下、本発明の一実施例を図面について説明す
る。
An embodiment of the present invention will be described below with reference to the drawings.

第1図は本実施例の分解斜視図、第2,3図及
び第4図はそれぞれウエハの格納及び取り出し作
業の説明図である。
FIG. 1 is an exploded perspective view of this embodiment, and FIGS. 2, 3, and 4 are illustrations of wafer storage and removal operations, respectively.

第1図〜第4図において、開口部2Aを設けた
主キヤリヤ2には、該開口部2Aの内周壁に二つ
のウエハ格納溝5a,5bが設けられると共に、
該両溝5a,5b間の隔壁6の一部分(第1図b
では右側の1/3部分)に仕切壁6Aが設けられて いる。
In FIGS. 1 to 4, the main carrier 2 provided with an opening 2A is provided with two wafer storage grooves 5a and 5b on the inner peripheral wall of the opening 2A.
Part of the partition wall 6 between the grooves 5a and 5b (Fig. 1b)
In this case, a partition wall 6A is provided on the right side (1/3 part).

上記主キヤリヤ2の上・下部にそれぞれ重合さ
れる上・下部副キヤリヤ1,3には、第1図a及
び同図cに示すように凹部1A,3Aがそれぞれ
設けられ、かつ該凹部1A,3Aの内周壁には、
一つのウエハ格納溝4,7がそれぞれ設けられて
いる。この両副キヤリヤ1,3と主キヤリヤ2
は、互に重合することが可能なように構成されて
いる。
The upper and lower sub-carriers 1 and 3 superimposed on the upper and lower parts of the main carrier 2, respectively, are provided with recesses 1A and 3A, respectively, as shown in FIGS. 1a and 1c, and the recesses 1A, On the inner peripheral wall of 3A,
One wafer storage groove 4, 7 is provided respectively. Both secondary carriers 1 and 3 and main carrier 2
are configured such that they can be mutually polymerized.

上記主キヤリヤ2にウエハ9同志を前向きに整
列して格納する場合を第2図について説明する。
The case where the wafers 9 are stored in the main carrier 2 in a forward alignment will be described with reference to FIG.

まず、第2図Bに示すように主キヤリヤ2を上
向きに起立させた後、裏面を真空ピンセツト8で
吸着した第1ウエハ9aを第2格納5bの存在す
る領域で作業して第1格納溝5c内に格納する。
すなわち、第ウエハ9aの裏面を保持しながら、
第1ウエハ9を該裏面から表面へ向う方向へ動作
させて該1格納溝5aに格納する。
First, as shown in FIG. 2B, after the main carrier 2 is erected upward, the first wafer 9a, whose back surface is suctioned by the vacuum tweezers 8, is worked in the area where the second storage 5b exists, and is placed in the first storage groove. Store in 5c.
That is, while holding the back surface of the wafer 9a,
The first wafer 9 is moved from the back surface to the front surface and stored in the first storage groove 5a.

次に第2ウエハ(図示せず)も同様に該裏面を
真空ピンセツトにより吸着した状態で、第1格納
溝5aの存在する領域から第1ウエハ9aに接触
させずに第1格納溝5a内に格納する。すなわ
ち、第2ウエハの裏面を保持しながら、第2ウエ
ハを該裏面から第1ウエハ9aの裏面に向う方向
へ動作させて第2格納溝5b内に格納する。
Next, the second wafer (not shown) is also placed into the first storage groove 5a from the region where the first storage groove 5a exists without contacting the first wafer 9a, with its back surface being suctioned by vacuum tweezers. Store. That is, while holding the back surface of the second wafer, the second wafer is moved from the back surface toward the back surface of the first wafer 9a and stored in the second storage groove 5b.

又、上・下部副キヤリヤ1,3にも、上記に準
じてウエハう格納溝に格納する。該下部副キヤリ
ヤ3上に主キヤリヤ2及び上部副キヤリヤ1を、
第2図Aに示すように順次に積み重ねて一体とな
し、この状態で搬送及び保管が行われる。
Further, wafers are stored in the wafer storage grooves of the upper and lower sub-carriers 1 and 3 in the same manner as described above. A main carrier 2 and an upper sub-carrier 1 are placed on the lower sub-carrier 3,
As shown in FIG. 2A, they are stacked one after another to form a single body, and transported and stored in this state.

さらに、第3図A,Bに示すようにウエハ9
a,9bの表面を互に向き合せ(又は背中合せ)
にして主キヤリヤ2のの格納溝5a,5bにそれ
ぞれ格納する場合には、上記の場合に準じて互い
のウエハに接触することなく格納作業を実施する
することができる。
Furthermore, as shown in FIGS. 3A and 3B, the wafer 9
Face the surfaces of a and 9b (or back to back)
When storing the wafers in the storage grooves 5a and 5b of the main carrier 2, the storage operation can be carried out without touching each other's wafers in the same way as in the case described above.

一方、キヤリヤからウエハを取出す場合には、
第4図に示すようにキヤリヤ2の格納溝5に格納
されたウエハ9を、前記格納時と同様に真空ピン
セツト8により吸着し、相隣るウエハの表面に接
触することなく取出すことができる。
On the other hand, when removing the wafer from the carrier,
As shown in FIG. 4, the wafer 9 stored in the storage groove 5 of the carrier 2 is attracted by the vacuum tweezers 8 in the same manner as in the case of storage, and can be taken out without coming into contact with the surfaces of adjacent wafers.

上述した実施例では、主キヤリヤ2を一個だけ
使用した場合について説明したが、本発明はこれ
に限定されず、主キヤリヤ2を複数個使用しても
よいことはもちろんである。
Although the above-mentioned embodiment describes the case where only one main carrier 2 is used, the present invention is not limited to this, and it goes without saying that a plurality of main carriers 2 may be used.

本実施例によれば、主キヤリヤにおけるウエハ
の格納及び取出し作業の際に、相隣るウエハの表
面に接触することがないように作業領域を設定す
ることができる。又、上・下部副キヤリヤが上蓋
と底台をそれぞれ兼用するため、キヤリヤの格納
容器を省略することが可能である。
According to this embodiment, when storing and taking out wafers in the main carrier, the work area can be set so as not to come into contact with the surfaces of adjacent wafers. Furthermore, since the upper and lower sub-carriers serve as the upper lid and the bottom stand, respectively, it is possible to omit the storage container for the carriers.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明によれば、キヤリ
ヤに設けた各ウエハ格納溝側の領域を作業領域と
して広く利用することにより、ウエハ表面の保護
による材料歩留りの向上及び作業性の向上をはか
ることができる。又ウエハの搬送、保管及び格納
の際に、キヤリヤ内のウエハを作業雰囲気中の塵
あいによる汚染から保護し、製品の歩留りを向上
させることができる。
As explained above, according to the present invention, by widely utilizing the area on the side of each wafer storage groove provided in the carrier as a work area, it is possible to improve material yield and work efficiency by protecting the wafer surface. I can do it. Furthermore, during the transportation, storage, and storage of wafers, the wafers in the carrier can be protected from contamination due to dust in the working atmosphere, and the yield of products can be improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明のウエハキヤリヤ治具の一実施
例を示す分解斜視図、第2図、第3図及び第4図
は第1図に示すキヤリヤにおけるウエハの格納及
び取出し作業をそれぞれ説明する図、第5図A〜
Cは従来のウエハキヤリヤの平面図、正面図及び
側断面である。 符号の説明、1,3……副キヤリヤ、1A,3
A……凹部、2……主キヤリヤ、2A……開口
部、4,5,7……ウエハ格納溝、6A……仕切
壁、9,9a,9b……ウエハ。
FIG. 1 is an exploded perspective view showing one embodiment of the wafer carrier jig of the present invention, and FIGS. 2, 3, and 4 are diagrams each illustrating the wafer storage and removal operations in the carrier shown in FIG. 1. , Figure 5 A~
C is a plan view, a front view, and a side cross-section of a conventional wafer carrier. Explanation of symbols, 1, 3...Sub-carrier, 1A, 3
A... recess, 2... main carrier, 2A... opening, 4, 5, 7... wafer storage groove, 6A... partition wall, 9, 9a, 9b... wafer.

Claims (1)

【特許請求の範囲】[Claims] 1 開口部を設けると共に、該開口部の内周壁に
二つのウエハ格納溝を設けた主キヤリヤと、凹部
を設けると共に、該凹部の内周壁に一つのウエハ
格納溝を設けた上部及び下部副キヤリヤとからな
り、該両副キヤリヤと前記主キヤリヤを互に重合
可能に構成したことを特徴とするウエハキヤリヤ
治具。
1. A main carrier having an opening and two wafer storage grooves on the inner peripheral wall of the opening, and upper and lower sub-carriers having a recess and one wafer storage groove on the inner peripheral wall of the recess. A wafer carrier jig comprising: a wafer carrier jig, characterized in that both of the sub-carriers and the main carrier are configured to be superimposed on each other.
JP61219373A 1986-09-19 1986-09-19 Wafer carrier jig Granted JPS6376449A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61219373A JPS6376449A (en) 1986-09-19 1986-09-19 Wafer carrier jig

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61219373A JPS6376449A (en) 1986-09-19 1986-09-19 Wafer carrier jig

Publications (2)

Publication Number Publication Date
JPS6376449A JPS6376449A (en) 1988-04-06
JPH0546982B2 true JPH0546982B2 (en) 1993-07-15

Family

ID=16734398

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61219373A Granted JPS6376449A (en) 1986-09-19 1986-09-19 Wafer carrier jig

Country Status (1)

Country Link
JP (1) JPS6376449A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN213532672U (en) * 2021-03-19 2021-06-25 台湾积体电路制造股份有限公司 Positioning fixture

Also Published As

Publication number Publication date
JPS6376449A (en) 1988-04-06

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