JPH0546989B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a programmable semiconductor device, and particularly to a programmable semiconductor device that can monitor the manufacturing status of memory cells.

[Conventional technology]

One of the important performance characteristics that characterizes the quality of programmable semiconductor devices is the write yield, and in recent years the market has been demanding a high write yield of 99% or higher, which has become a key point in development. In the case of programmable semiconductor devices that use junction breakdown transistors as memory cells, the factors that determine the write yield are the write current value applied from the outside, the emitter area of the cell transistor, the junction depth (xje) of the cell transistor, Examples include the crystal state of the cell transistor forming region.

Among them, especially the write current and the emitter area of the cell transistor (hereinafter referred to as memory cell area)
The relationship between the two is important and there is a close correlation. Generally speaking, if a memory cell has a large area, a large write current is required for writing. What must be noted here is that the memory cell area varies within a certain range between lots or between wafers due to manufacturing variations.

In the case of the programmable semiconductor device of the present invention manufactured by the LOCOS method, the main causes of variations in memory area are variations in the etching removal of the photoresist and masked film during LOCOS oxide film pattern formation, and variations in the LOCOS oxide film thickness. etc. When these process variations overlap and the memory cell area increases to MAX,
This may lead to a decrease in write yield. This is where the need to monitor the memory cell area arises.
Currently, the method of investigating this is to directly visually observe the memory cell area inside the chip using a microscope, but the reality is that the judgment is likely to be inaccurate.

[Problem that the invention seeks to solve]

An object of the present invention has been made to solve the above-mentioned problems, and to provide an appropriate monitor pattern that can easily and accurately determine the degree of variation in memory cell area by visual inspection with a microscope. An object of the present invention is to provide a programmable semiconductor device having the following features.

[Differences between the Invention and the Prior Art] As described above, in the past, programmable semiconductor devices did not have an appropriate method for monitoring the manufacturing state of memory cells. In contrast, the present invention has an original point in that by proposing an appropriate peripheral monitor pattern, it is possible to accurately know the degree of variation in memory cell area, making manufacturing and characteristic analysis after completion convenient. Motsu.

[Means for solving problems]

In the programmable semiconductor device of the present invention, an opening of the same shape and structure as an opening for forming an emitter region of an internal memory cell is placed around a semiconductor chip in a row direction, and a width of the opening for forming an emitter region of the memory cell is equal to the width of the opening for forming an emitter region of the memory cell. The monitor pattern includes monitor patterns arranged in a matrix of m rows and n columns with respective intervals equal to the vertical width of the opening for forming the emitter region of the memory cell.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIGS. 1a and 1b are a plan view and a sectional view taken along line A-A' of a monitor pattern according to an embodiment of the present invention.
In Figures 1a and 1b, 11 is a monitor pattern transistor made in the same shape and structure as the internal memory cell transistor, 12 is an n ⁺ emitter, and 13 is a
p ⁺ base, 14 is n-type epitaxial layer, 15
is the LOCOS oxide film, 16 is the n ⁺ buried layer, and 17
represents a p-type substrate. These transistors are arranged in a matrix of 3 rows and 4 columns as shown in FIG. 1a. The sizes x and y of the emitter region openings are the same size as the emitter region openings of internal memory cell transistors, and are arranged at intervals equal to the size of the emitter region openings in both the row and column directions. In the figure, a matrix arrangement of 3 rows and 4 columns is taken as an example, but it can generally be represented by m rows and n columns.

FIG. 2 is a diagram for explaining the principle of the present invention, in which a is a plan view and b is a cross-sectional view of a monitor pattern in the present invention. The figure shows a case where they are arranged in 3 rows and 4 columns. In the figure, 21 indicates a monitor pattern transistor. The area surrounded by the dotted line represents the emitter area on the mask (size x x y, that is, when process variation is zero), and the area surrounded by the solid line represents the actual emitter area after process variation (the figure shows the oversized emitter area). case).

a represents the width of the actually completed emitter region, and b represents the spacing between the emitters. The figure shows a case where the memory cell emitter becomes oversized due to process variation, and the relationship a>b can be easily determined by visual inspection using a microscope. Further, in order to obtain the variation amount c in more detail, the dimensions may be measured by taking a photograph. The following relationship holds between each dimension.

a=x+2c...(1) b=x−2c…(2) Calculating the amount of variation c from (1) and (2), c=a-b/4 It is.

A similar relationship also holds between the dimensions in the column direction, and the amount of variation f is f=de/4.

By arranging transistors of the same size as the memory cells in a matrix at intervals equal to the emitter size of the cell transistors, it is possible to easily check the degree of variation in the memory cells using a microscope. The amount of variation can be determined by measurement and calculation. Since this peripheral monitor pattern reproduces the state of the internal memory cell, the information obtained from the monitor pattern can be directly applied to the internal memory cell.

[Embodiment 2] FIGS. 3a and 3b are a plan view and a sectional view taken along line C-C' of a monitor pattern according to a second embodiment of the present invention. In the figure, 31 is an emitter region, 32 is a common base region, 33 and 36 are insulating oxide films, 34 is an n-type epitaxial layer, 35 is an n ⁺ buried layer, and 37 is a p-type substrate. Unlike the first embodiment, this embodiment is an example of a monitor pattern when the memory cells have a non-walled emitter structure, but the arrangement is arranged in a matrix at equal intervals, which is the same as in the first embodiment. The variation in memory cells can be determined using the principle of

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to easily and accurately monitor the manufacturing state of the memory cell area, which affects the write yield, which is one of the important quality performance of programmable semiconductor devices. This is effective in realizing a programmable semiconductor device with good write yield.

[Brief explanation of drawings]

FIGS. 1a and 1b are a plan view and a sectional view taken along line A-A' of an embodiment of the present invention. Figures 2a and 2b are diagrams for explaining the principle of the present invention, and are a plan view and a
B′ cross-sectional view. Figures 3a and 3b are a plan view and a sectional view of another embodiment of the invention. 11, 21...monitor pattern transistor,
12, 22... Emitter region (n ⁺ ), 13, 23
... Base region (p ⁺ ), 14, 24 ... N-type epitaxial substrate, 15, 25 ... LOCOS oxide film,
16, 26... n ⁺ buried layer, 17, 27... p type substrate, 18, 28... p ⁺ insulating layer, x... lateral dimension of the emitter region on the mask, y... vertical dimension of the emitter region on the mask Dimensions, a... Actual emitter area horizontal dimension, b... Emitter area interval (horizontal), c... Lateral dimension variation, d... Actual emitter area vertical dimension, e... Actual emitter area interval ( Vertical), f...
...Vertical dimension variation.

Claims (1)

[Claims] 1. In a programmable semiconductor device using a junction breakdown transistor as a memory cell, a monitor pattern is provided separately from the memory cell, and the monitor pattern is a pattern having the same shape and structure as the opening for forming the emitter region of the memory cell. A programmable semiconductor device characterized in that the device is arranged in a matrix of m rows and n columns with intervals equal to the width and length of the opening in the row and column directions.