JPH0650712B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a method of manufacturing a variable capacitance diode, which facilitates management of manufacturing conditions.

(B) Prior art The conventional flower variable capacitance diode shown in FIG. 2 is an N ⁺ type semiconductor substrate having a specific resistance of 0.001 to 0.01 Ω · cm.
An N type shrimp type layer (2) is formed on one surface of (2), and then a P ⁺ type layer (3) is formed on the surface of the N type epi layer (2) by selective diffusion, and a surface oxide film (4) is formed. It is manufactured by forming an electrode (5) which makes ohmic contact with the P ⁺ type layer (3) through the contact hole.

Junction capacitance C is a main electrical characteristic of the variable capacitance diode having this configuration. This characteristic is P which forms a PN junction.
^Since there is a close relationship with the area of the ⁺ type layer (3) and the design accuracy is extremely strict, small fluctuations in the capacitance value due to process fluctuations cannot be overlooked. Therefore conventionally, P ⁺ -type layer prior one epitaxial wafer (3) formation is measured junction capacitance C in finished wafer state, P ⁺ -type layer of Rottoueha following based on the value (3) To form an appropriate joint area,
An appropriate exposure mask is selected from a plurality of P ⁺ -type layer (3) forming exposure masks having different diffusion window areas, and a lot wafer to be subsequently flown is manufactured by using the selected exposure mask. The value of the junction capacitance C was strictly controlled.

(C) Problems to be Solved by the Invention However, when a value of the junction capacitance C is out of the standard due to a suitable abnormality or the like, which one of the plural types of P ⁺ type layer (3) forming masks is selected, Whether or not the product is used has no choice but to check the record in the manufacturing process, and there is a drawback that the response when a defect occurs is delayed.

(D) Means for Solving the Problems In view of the above conventional problems, the present invention has a target pattern (1
Symbol indicating the type of P ⁺ type layer (3) exposure mask in 2)
By simultaneously exposing (13), a semiconductor device manufacturing method capable of immediately dealing with a defect occurrence is provided.

(E) Action According to the present invention, the display symbol (1
Since 3) was exposed, it is possible to immediately determine which exposure mask was used in the state of the wafer (10). Moreover, since such a display symbol is not attached to the chip pattern (11), there is no problem in appearance.

(F) Embodiment Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

The semiconductor wafer (10) shown in FIG. 1 has an N ⁺ type layer on the back surface.
The formation of (2) is completed, and the formation of the P ⁺ type layer (3) is completed on the surface by a well-known selective diffusion technique, and a large number of chip patterns (11) for forming a PN diode are drawn vertically and horizontally. At the same time, target patterns (12) for wafer alignment are drawn at two places on the left and right.

Then, the exposure mask for forming the P ⁺ -type layer (3) includes a wafer
(10) The oxide film (4) on the surface is photo-etched to serve as a selective mask for diffusion, and a pattern corresponding to the selective mask for forming the P ⁺ type layer (3) on the chip pattern (11) is drawn. And a display symbol (13) P ⁺ 1, P indicating the type of the exposure mask in the target pattern (12) area.
⁺² , P ⁺ 3 ... Are drawn.

The symbol (13) indicates P ⁺ by indicating the type of exposure mask.
It represents the size (area) of the pattern for forming the mold layer (3), and the relationship is as shown in Table 1, for example.

If a defect occurs due to the capacitance measurement in the wafer (10) state on the actual manufacturing line, the target pattern (12)
The above-mentioned display symbol (13) is used to determine the area ratio of the exposure mask currently used. And
Based on the measurement result, it is determined how much the junction capacitance C should be increased or decreased, and after selecting which mask to use, the selected type of mask may be used from the next lot. Since the junction area formed by the P ⁺ type layer (3) can be changed by changing the mask, the junction capacitance C can be controlled to a value closer to the design value for manufacture. After that, the individual chip patterns (11) are divided and each is stored in a package.

(G) Effect of the Invention As described above, according to the present invention, the target pattern
Since the display symbol (13) is exposed in the area (12), it is possible to immediately determine in the wafer (10) which type of mask is used, and thus it is possible to immediately respond to process variations.
Therefore, it can also contribute to yield improvement.

Further, since the chip pattern (11) is not provided in the main body, it is possible to solve the problem that different patterns are drawn on the chip pattern (11) in the same model.

[Brief description of drawings]

FIG. 1 is a plan view for explaining the present invention, and FIG. 2 is a sectional view showing a PN diode.

Claims (1)

[Claims] 1. A single wafer is simultaneously exposed with a large number of chip patterns and a plurality of alignment target patterns to diffuse impurities, thereby forming anode / cathode junctions of variable capacitance elements on individual chips. A plurality of types of exposure masks in which the area of the drawing pattern is changed so that the area of the anode / cathode junction can be changed are prepared, and a symbol for identifying the area of the drawing pattern is formed in the target pattern during the exposure. Then, after measuring the capacitance value of the anode / cathode junction, the mask currently used is discriminated from the symbol, and the mask having an appropriate drawing pattern is discriminated from the difference between the measured value and the target value. A method of manufacturing a semiconductor device, characterized in that a mask selected from the results is changed and the next lot is exposed.