JPH054708B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a processor unit used in a multiprocessor system in which each processor unit communicates via two or more sets of interprocessor data transfer buses. .

(Prior art) In order to improve the processing power of the system and simplify the software configuration of the processor unit,
In some cases, multiple single-task processor units are connected to each other via a data transfer bus to form a load-balanced multiprocessor system. When requesting the execution of a subtask to a unit and expecting a response as a result, or when processing an inquiry that involves a return of response information, such as when requesting the provision of unique information possessed by another processor unit. must constantly monitor the reception buffer of the interprocessor data transfer bus during task execution and determine whether the received message is another new task request or a response to an inquiry.

This is because the above processor unit can only execute a single task, so if the received message is a response to an inquiry, there is no problem, but if it is a request for another new task, the requester will indicate that the request cannot be executed. This is because the processor unit must be notified.

However, as can be easily imagined, if the above-mentioned determination and response were executed by software, the software processing time in each processor unit would increase, making it difficult to increase the processing capacity. In order to compensate for this drawback, the following inter-processor data transfer system has been proposed. This has two mutually exclusive reception states, a device busy state and a device idle state, in each processor unit, and means for setting either of them in each processor unit. It has an empty selection transmission request in which transmission permission is granted when the device is in the idle state, and a busy selection transmission request in which transmission permission is granted when the device is in the busy state, and it is possible to specify which one to use. This is a method of providing the means using hardware.

That is, when each processor unit needs to request a task to another processor unit, it transmits an empty selection transmission request to the other processor unit, and after receiving transmission permission, transmits the task request.

On the other hand, a processor unit that has received a task request from another processor unit sets its receiving state to a device busy state, and sends the request to another processor unit that responds to an inquiry from the processor unit that has been set to a device busy state. transmits response information using a busy selection transmission request. Therefore, the new task request is an empty selection send request, while the processor unit executing the task is in a busy state, so permission to send is not granted and the software judges the received information. There is no need to notify that a new task cannot be executed.

(Problems to be Solved by the Invention) However, since all of the above-mentioned conventional technologies are single-task systems, if an inquiry is made to another processor unit during the execution of a task, it will cause problems for the processor unit currently executing the task. The time spent waiting for a response to an inquiry actually occurs as a completely wasted time that has nothing to do with the processing time required to execute the task, and if the number of inquiries to other processor units increases during task execution, the task execution time for the inquiry time increases. This has the disadvantage that the advantages of multiprocessorization cannot be fully utilized.

In order to reduce the waiting time for responses to inquiries, it is necessary to adopt a multitasking system, but when trying to adopt a multitasking system in a multiprocessor system using a conventional hardware processor unit, it is difficult to use software. There was a problem that the process became complex and large-scale, resulting in a heavy burden.

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems of the prior art, an object of the present invention is to provide a processor unit that can realize a multitasking system with a software configuration in each processor unit as simple as that of a single-tasking system. This is what we are trying to provide.

(Means for Solving the Problems) The present invention has the following configuration to achieve the above object. That is, the multitask processor unit of the present invention includes: a processor; a plurality of bus interface sections provided corresponding to each system of a plurality of connected inter-processor data transfer buses; a reception buffer memory unit that stores information received by each transfer bus;
Each transfer bus is provided separately, and according to a command from the processor, when information for executing a task is not received via the transfer bus, the device is set to the empty state, and after receiving the information, the device is set to the busy state. According to the set device status, the corresponding bus interface section grants transmission permission to an empty selection transmission request that arrives when the device is in an idle state, and grants transmission permission to an idle selection transmission request that arrives when the equipment is busy. a reception control section that controls the bus interface section and controls the reception buffer memory section so as to grant transmission permission to a selective transmission request and grant transmission permission to a busy selective transmission request; a transmission buffer memory unit for accumulating information; and a transmission control unit that selects an empty or busy transmission request based on commands from the processor, controls the selection of a transmission transfer bus for the bus interface unit, and controls the transmission buffer memory unit. It is characterized by having a part and;

(Function) The processor unit of the present invention has a plurality of circuits (referred to as reception buffers) each consisting of a bus interface section, a reception control section, and a reception buffer memory, and each bus interface section has a common processor unit. The processor is connected to a different transfer bus among a plurality of interprocessor data transfer buses connected to the processor. The reception buffer is in the equipment empty state while not receiving information for task execution from another processor unit, and becomes the equipment busy state after receiving information. When a task request or inquiry empty selection transmission request (preliminary signal to transmit) is received from another processor unit when the device is idle, the bus interface section grants transmission permission and receives the transmission of information for task execution. .

On the other hand, when the device is in a busy state, the bus interface section does not grant transmission permission even if an idle selection transmission request comes, but grants transmission permission when a busy selection transmission request comes. On the other hand, for transmission, the transmission control unit sends an empty selection transmission request when requesting a task or making an inquiry to another processor unit, and a busy selection transmission request when sending a response to an inquiry. In addition, the transmission control section controls the bus interface section to select the transfer bus for transmission.

Therefore, in the processor unit of the present invention, each receiving buffer can accept one task request or inquiry, and in the end, it is possible to accept as many task requests or inquiries as the number of receiving buffers provided.

Further, even if the receiving buffer receives a task request, it can receive responses to inquiries made to other processor units in executing the task even if the device is busy.

Therefore, if a task request or inquiry is made to another processor unit while the processor is currently executing a task accepted by the 0th reception buffer, the result or response will be The execution of the task in the processor will be interrupted until the processor returns, but during that time, for example, it is possible to execute the task received in the first receiving buffer, and as long as there are accepted tasks, the processor will continue to operate. It is possible to prevent empty spaces from occurring.

As a result, when a processor unit executes its own task in sequence, the waiting time is significantly increased if it issues a task execution request or makes an inquiry to another processor unit in the middle. means to be shortened.

The software configuration in each processor unit for realizing this is comparable to the software configuration of a single-task system.

That is, in a multiprocessor system using the processor unit of the present invention, a multitask system can be realized with a software configuration in each processor unit that is as simple as a single task system.

(Embodiment) Next, an embodiment of the processor unit of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the structure of one embodiment of a processor unit according to the present invention. This embodiment shows a processor unit 100 that connects two sets of inter-processor data transfer buses, a 0th inter-processor data transfer bus 110 and a first inter-processor data transfer bus 111.

The 0th inter-processor data transfer bus 110 is connected to a bus 0 reception buffer 80 and a transmission buffer 90 via a bus 0 interface section 70, respectively. Similarly, the first inter-processor data transfer bus 111 is connected to a bus 1 reception buffer 81 and a transmission buffer 90 via a bus 1 interface section 71, respectively. On the other hand, the processor 10 uses the bus 0 via the processor interface section 20.
It is connected to a receiving buffer 80, a bus 1 receiving buffer 81, and a transmitting buffer 90.

The bus 0 reception buffer 80 includes a bus 0 reception buffer memory section 30 that stores information received via the 0th inter-processor data transfer bus 110, and a bus 0 reception buffer memory section 30 that stores information received via the 0th inter-processor data transfer bus 110, and a bus 0 reception buffer memory section 30 that stores information received via the 0th inter-processor data transfer bus 110. Bus 0 reception control unit 5 that sets one of two reception states: medium state;
0, and the bus 0 reception control section 50 controls the bus 0 interface section 70 and the bus 0 reception buffer memory section 30, respectively, according to the set reception state. Similarly, the bus 1 reception buffer 81
A bus 1 reception buffer memory unit 31 that stores information received via the first inter-processor data transfer bus 111 and a processor interface unit 2
0, the processor 10 is configured with a bus 1 reception control unit 51 that sets one of two reception states, a device empty state and a device busy state. Therefore bus 1
The interface unit 71 and the bus 1 reception buffer memory unit 31 are controlled respectively.

The transmission buffer 90 includes a transmission buffer memory section 40 that stores information to be sent to other processor units via the 0th inter-processor data transfer bus 110 or the 1st inter-processor data transfer bus 111, and the processor interface section 20. A transmission control unit that sets which of the two types of transmission requests, empty selection and busy selection, the processor 10 will use, and which of the two sets of inter-processor data transfer buses to use for transmission. The transmission control section 60 controls the bus interface section connected to the set inter-processor data transfer bus and the transmission buffer memory section 40.

FIG. 2 is a block diagram showing an embodiment of an inter-processor data transfer system constituted by processor unit 100 according to the present invention shown in FIG. 1 and processor units 101 to 103 having the same configuration. , each processor unit 100
~103 is the 0th inter-processor data transfer bus 1
10 and a first inter-processor data transfer bus 111.

In this embodiment, when each processor unit is not executing a task, the processor 10 in each processor unit communicates with the bus 0 reception control section 50 and the bus 0 through the processor interface section 20, respectively. 1 The reception control unit 51 is set to the device idle state as the reception state, and set to the device busy state when executing a task or waiting for response information to an inquiry to another processor unit. In addition, when transmitting task request information to another processor unit, the processor 10 sets empty selection in the transmission control unit 60 via the processor interface unit 20, and responds to inquiries from other processor units. When sending response information, set busy selection.

Next, the communication operation of the processor unit will be explained. When a task request to the processor unit 100 occurs in the processor unit 102, the following operations are performed inside the processor unit 102. That is, processor 10
The processor interface section 20 stores the task request for the processor unit 100 corresponding to the transmission information in the transmission buffer memory 40, sets the empty selection to the transmission control section 60, and sets the inter-processor data transfer bus used for transmission. After each specification is made, transmission execution is commanded.

Now, the 0th inter-processor data transfer bus 11 is used as the inter-processor data transfer bus used for transmission.
If 0 is specified, the transmission control unit 60 controls the bus 0 interface unit 70 to send an empty selection transmission request to the 0th inter-processor data transfer bus 110. In response to this empty selection transmission request, in the processor unit 100, since the device empty reception state is set in the bus 0 reception control section 50 corresponding to the 0th inter-processor data transfer bus 110, the bus 0 interface section 70 Then, the processor 10 determines that the received transmission request corresponds to its reception state, and immediately sends a transmission permission via the 0th inter-processor data transfer bus 110. After receiving the information, the processor 10 transfers the data to the processor interface. The device busy state is set as the reception state in the bus 0 reception control section 50 via the face section 20.

Therefore, in the processor unit 100, the 0th inter-processor data transfer bus 110
In response to an empty selection transmission request sent via the bus 0 interface section 70, the bus 0 interface unit 70 determines that the own receiving state and the transmission request do not correspond, and does not grant any transmission permission. That is, processor unit 1
00, another new task request via the 0th interprocessor data transfer bus 110 will not be accepted.

On the other hand, since the bus 1 reception control section 51 in the processor unit 100 remains set to the device idle reception state, the bus 1 reception control section 51 in the processor unit 100 does not transmit data in response to the idle selection transmission request sent via the first inter-processor data transfer bus 111. permission can be granted.

That is, it is possible to accept only one task request with the same operation as on the 0th inter-processor data transfer bus side.

On the other hand, while each processor unit is executing a task based on the aforementioned task request, there may be a need for communication such as inquiries to other processor units. Now, the processor unit 100 is connected to the 0th inter-processor data transfer bus 1.
When executing a task in response to a task request received via the processor unit 101, the processor unit 101
If it becomes necessary to make an inquiry to the processor unit 101, the inquiry information to the processor unit 101 is sent to the
The data is transmitted via the interprocessor data transfer bus 110. The processor unit 101 that has received the inquiry information sets the busy selection in the transmission control section 70 and transfers the 0th inter-processor data transfer bus 11.
The response information is transmitted via 0.

That is, bus 0 of processor unit 100
The reception control unit 50 does not grant permission to the empty selection transmission request because the device busy reception state is set for the task being executed, but it does not grant permission to the busy selection transmission request sent from the processor unit 101. Since the bus 0 interface unit 70 determines that this corresponds to the self-receiving state and grants transmission permission, it is possible to receive response information to the inquiry.

As described above, each processor unit can accept only one task corresponding to the inter-processor data transfer bus, and it is also possible to establish communication with a specific processor unit during task execution.

(Effects of the Invention) Since the processor unit of the present invention has the configuration and operation described above, it can issue one task request per receiving buffer and send requests to other processor units via the receiving buffer. Therefore, it is possible to receive as many task requests and inquiry responses as there are reception buffers provided.

Then, while a processor is executing a task accepted by one of the receiving buffers, it becomes necessary to request a task or make an inquiry to another processor.
By doing this, during the waiting time until a response arrives, tasks accepted by other receiving buffers can be executed, so as long as there are accepted tasks, the processor can be operated without idleness, and the waiting time is significantly longer than in a single-task system. It can be shortened to

The software configuration of each processor unit to achieve this is comparable to the software configuration of a single-task system, so in a multiprocessor system using the processor unit of the present invention, each processor This has the advantage that a multitasking system can be realized with a software configuration in the setter unit that is as simple as a single-tasking system.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the processor unit of the present invention, and FIG. 2 is a configuration diagram of a multiprocessor system using a plurality of processor units of the present invention shown in FIG. be. 10... Processor, 20... Processor interface section, 30... Bus 0 reception buffer memory section, 31... Bus 1 reception buffer memory section,
40...Transmission buffer memory section, 50...Bus 0
Reception control unit, 51...Bus 1 reception control unit, 60...
...Transmission control section, 70...Bus 0 interface section, 71...Bus 1 interface section, 80...
... Bus 0 reception buffer, 81 ... Bus 1 reception buffer, 90 ... Transmission buffer, 100 to 103 ...
. . . processor unit, 110 . . . 0th inter-processor data transfer bus, 111 . . . 1st inter-processor data transfer bus.

Claims (1)

[Claims] 1 a processor; a plurality of bus interface units provided corresponding to each system of a plurality of connected inter-processor data transfer buses; information received via each of the transfer buses is stored for each transfer bus; a receiving buffer memory unit provided for each transfer bus, and set to a device empty state when information for task execution is not received via the transfer bus according to a command from the processor;
After receiving the above information, the device is set to busy state,
According to the set device state, the corresponding bus interface section grants transmission permission to an empty selection transmission request that arrives when the device is in an idle state, and grants transmission permission to an empty selection transmission request that arrives when the equipment is busy. a reception control unit that controls the bus interface unit so as to grant transmission permission to the busy selection transmission request but not to the busy selection transmission request; and a reception control unit that controls the reception buffer memory unit; and a reception control unit that stores information to be transmitted. a transmission buffer memory unit for selecting an empty or busy transmission request according to a command from the processor;
A processor unit comprising: a transmission control section that controls selection of a transmission transfer bus for a bus interface section; and a transmission control section that controls the transmission buffer memory section.