JPH0548007B2 - - Google Patents

Description

[Detailed Description of the Invention] Industrial Application Field The present invention is a simplified CMOS (complementary field effect transistor) multi-input gate circuit.
The present invention relates to a counter decoder that decodes the count value of a binary counter that can be set or reset.

Conventional configuration and its problems In general, a CMOS multi-input gate circuit requires a minimum number of elements of 2n for the number of inputs n. For this reason, it is undeniable that the chip area increases when integrated circuits (ICs) are implemented, making it extremely unsuitable for use as a counter decoder that simply detects the count value of a binary counter. In order to eliminate such drawbacks, the applicant of the present invention proposed a CMOS multi-input gate circuit in which the number of constituent elements can be increased to (n+2) in Japanese Patent Application No. 57-59537.

FIG. 1 illustrates one circuit configuration thereof.

In Figure 1, A is a NAND gate circuit, B
is a NOR gate circuit.

The NAND gate circuit A consists of n series-connected enhancement type N-channel MOS transistors (N-type transistors) MN ₁ , MN ₂ , ..., MN _o corresponding to the number of inputs n, and one enhancement type P Channel MOS transistor (P-type transistor) MP ₁ and load element
Consisting of a total of (n+2) elements of ML ₁ , one end of a group of N-type transistors connected in series is connected to the output terminal b, the other end is connected to the first power supply V _SS , and the gates of each are connected to the input terminal a. ₁ , a ₂ , a ₃ , ..., a _o . One end of the P-type transistor _MP1 is connected to the second power supply _VDD , the other end is connected to the output terminal b, and the gate is connected to the gate of the N-type transistor _MN1 . Load element ML ₁ is connected to the second power supply V _DD and output terminal b
is connected between.

On the other hand, n series-connected P-type transistors
The sum of MP ₁ , MP ₂ , ..., MP _o , one N-type transistor MN ₁ and load element ML ₁ (n+2)
One end of a group of P-type transistors connected in series is connected to output terminal b, and the other end is connected to the first power supply.
V _DD and connect each gate to the input terminal
a ₁ , a ₂ , a ₃ , ..., a _o . One end of the N-type transistor _MN1 is connected to the second power supply V _SS , the other end is connected to the output terminal b, and the gate is connected to the P-type transistor.
Connected to the gate of MP ₁ . Load element ML ₁
is connected between the second power supply V _SS and the output terminal b.

That is, circuit A and circuit B are exactly symmetrical circuits, and at least one of the inputs has a complementary configuration.

The CMOS multi-input gate circuit explained above can be integrated into an IC.
, there is a stray capacitance at each connection point as shown in Figure 2.
C ₁ , C ₂ , C ₃ , ..., _Co is attached. If this is used as a counter decoder for decoding the count value of a binary counter that can be set or reset as shown in FIG. 3, a malfunction will occur during the set or reset operation. FIG. 4 is a waveform diagram showing this situation.

Hereinafter, the circuit operation of the conventional example will be explained with reference to FIGS. 2 to 4.

Figure 3 is a specific circuit example of a digital pulse width modulation circuit (PWM circuit) whose pulse width changes in proportion to the input digital information _D1 to _D4.This circuit can also be used as a phase modulation circuit or a delay circuit. can also be used, and in this case, the pulse width becomes the phase modulation amount and the delay amount. 1 to 4 are flip-flops with set (SET) and reset (RESET) functions (FF with RS)
A 4-bit down counter 5 is formed which counts down the Q outputs of the previous stage as clock inputs (CK). A counter decoder 6 decodes the count value "0" of the counter 5. 7 is the clock gate, and the counter 5
Give prohibition clock S ₂ to the 1st Bit (LSB). This clock gate 7 controls the passage of _the clock pulse S1 at the output _S4 of the counter decoder 6, and when the counter 5 reaches the count value ``0'', the clock pulse ₁ to _{4 is} output.
are all "H", the output _S4 of the counter decoder 6 becomes "L", the clock gate 7 is closed, and the counter 5 is stopped at the count value "0". 8-11 are inverters for obtaining inverted outputs _1-4 of _the input information _D1 - _D4 , 12-15 and 16-19 are set inputs () and reset inputs () have control pulses (preset pulses) _S3. 8 to 19 form a preset circuit 20. Here, the clock pulse
_S1 is a pulse for causing the binary counter 5 to perform a counting operation, and control pulse _S3 is a pulse for presetting the binary counter 5 to an initial counting value.

As is clear from the above configuration, the preset circuit 20 inverts the control pulse _S3 to the set input () when the input information _D1 to _D4 is "H", and to the reset input () when it is "L". give a pulse,
Performs a preset operation by setting or resetting. Therefore, input information D ₁ to _{D 4} is converted to FF1 with RS.
~4, just set the counting initial value (preset value) NP
It can be preset as . If this preset value NP is other than the count value "0" (NP≠0), the output _S4 of the counter decoder 6 becomes "H", the clock pulse _S1 is input to the counter 5, and the count value becomes "0". ” Count down until you reach ”. Thereafter, this operation is repeated every time the control pulse _S3 is input, and a pulse width modulated output (PWM output) _S4 can be obtained from the counter decoder 6.

Here, the counter decoder 6 in FIG.
The operation when the CMOS multi-input decoder circuit shown in the figure is applied will be explained with reference to the waveform diagram of FIG. 4.

The input terminals a ₁ to a ₄ of the gate circuit in Fig.
Input the outputs ₁ to ₄ of the counter 5 shown in the figure, respectively. That is, the LSB output ₁ of the counter 5 is input to the input _a1 of the complementary transistor. Then, the PWM output _S4 is obtained from the output terminal b and is input to the clock gate 7.

In the above configuration, when the counter 5 has a count value of "0", all of ₁ to ₄ are "H", and N
The P-type transistors _MN1 to _MN4 are all turned on, the P-type transistor _MP1 is turned off, and the output _S4 becomes "L". However, at this time, the "L" level is V _L ,
It will be higher than the level of V _SS . The size of V _L is MN ₁
Since it is determined by the voltage division ratio between the combined ON resistance of ~ _MN4 and the resistance of load element _ML1 , it is set to a level that will not cause the subsequent circuit, for example, clock gate 7, to malfunction. When all MN ₁ to MN ₄ are turned on, stray capacitance C ₁ to
The charge of C ₄ is discharged and the potential of each connection point is "0"
(actually in the range V _L ~ 0).

Next, consider the preset operation when the control pulse _S3 arrives and the preset values NP at that time are "6" and "5".

First, when NP=6, counter 5 has MSB
~LSB is preset to “0110” and the output becomes “1001”. Therefore, MN ₁ and MN ₄ are
ON, MN ₂ and MN ₃ are OFF, MP ₁ is ON, and capacitors C ₁ and C ₂ are attached to output terminal b.
Therefore, the output _S4 is held at the "L" level by the charges of the capacitors _C1 and _C2 , and does not become the "H" level at the same time as the preset, but must wait for charging by the load element _ML1 . The load element ML ₁ has a high resistance and draws a charging curve determined by the time constant with the capacitance (C ₁ +C ₂ ), and the clock gate 7 remains closed.

When the capacitors C ₁ and C ₂ are charged to a level at which the clock gate 7 is opened, the clock pulse S ₁ is passed and the clock pulse S ₂ is input to the counter 5 so that it can be counted. At the first count "5", the LSB output is inverted from "1" to "0", MN ₁ is OFF, MP ₁ is ON, and C ₁ is
Rapid charging is performed by MP ₁ , and output S ₄ is "H"
level. Thereafter, the count is down in the order of 4→3→2→1→0, and the output _S4 becomes "L" again, and the counting operation of the counter 5 is stopped. obtained at this time
The pulse width of the PWM output S ₄ is T ₆ ′, which includes the charging period Ta for C ₁ and C ₂ by the load element ML ₁ , and is larger than the pulse width T ₆ during normal operation, which can prevent malfunction. wake up

Next, when NP=5, counter 5 is preset to "0101" and its output is "1010".
becomes. Therefore, MN ₂ and MN ₄ are ON, MN ₁ ,
MN ₃ is turned OFF, MP ₁ is turned ON, C ₁ is attached to output terminal b, rapid charging is performed by MP ₁ , output S ₄ becomes "H", clock gate 7 is opened at the same time as presetting, and after presetting is completed. is 4→3→
Performs normal counting operation as 2 → 1 → 0. The pulse width T ₅ ' of the PWM output S ₄ obtained at this time is equal to the pulse width T ₅ during normal operation, and normal operation is possible.

From the above, _one output is "L" in the preset.
In this case (when the preset value NP is an odd number), normal operation as a counter decoder is possible, but when ₁ is "H" (when NP is an even number), it is necessary to wait for charging by the load element _ML1 . Not necessarily,
There was a problem that normal operation was not possible.

OBJECTS OF THE INVENTION The present invention solves the problems of the prior art, and aims to prevent malfunctions of the counter decoder that occur when presetting a binary counter.

Structure of the Invention The present invention includes a group of series-connected MOS transistors of the same polarity, the number of which is equal to the number of inputs, connected between an output terminal and a first power supply,
A second MOS transistor of opposite polarity is connected between the power supply and has a complementary configuration with the MOS transistor connected to the output terminal of the transistor group.
1MOS transistor, the output terminal and the second
a load element connected between the output terminal and the second power source; and a load element connected between the output terminal and the second power source;
a second MOS transistor having the same polarity as the first MOS transistor; and a second MOS transistor connected between a connection point on the first power supply side of the MOS transistor connected to the output terminal of the transistor group and the second power supply;
and a binary counter that includes a third MOS transistor whose input is commonly connected to the input of the first MOS transistor and has the same polarity as the first MOS transistor, whose initial counting value is preset by a control pulse, and which counts clock pulses. and decode the count value of the control pulse.
The counter decoder is configured as an input of 2 MOS transistors, and the present invention also includes a group of MOS transistors of the same polarity connected in series equal to the number of inputs, connected between an output terminal and a first power supply, and the output terminal and Second
a first MOS transistor of opposite polarity connected between the power source and having a complementary configuration with the transistor connected to the output terminal of the transistor group; and a first MOS transistor connected between the output terminal and the second power source. A load element is connected between the first power supply side connection point of the MOS transistor connected to the output terminal of the transistor group and the second power supply, and has an input common to the first MOS transistor. A third MOS transistor connected to the circuit and having the same polarity as the first MOS transistor, and an AND gate that provides input to the complementary configured MOS transistor, whose initial counting value is preset by a control pulse, and which counts clock pulses. While decoding the count value of the advance counter, the control pulse is
The counter that was used as another input of the AND gate
Let it be a decoder.

DESCRIPTION OF EMBODIMENTS FIG. 5 shows the basic configuration of the present invention, FIG. 6 is an operation waveform diagram of FIG. 5, and FIG. 7 shows another embodiment of the present invention.

FIG. 5 is shown corresponding to the conventional example shown in FIG. 1A, and the difference from the conventional example is that the second P for charging is
type transistor MP ₂ with output terminal B and second power supply V _DD
The inverted _{signal 3} of the control pulse S3 is input to the control pulse input terminal c, and the third P-type transistor _MP3 is connected to the output terminal of the transistor group. It is connected between the first power supply side connection point of the MOS transistor MN ₁ and the second power supply, and its input is commonly connected to the first MOS transistor MP ₁ .

If a multi-input gate circuit having such a configuration is used as the counter decoder 6 shown in FIG. 3, as shown in FIG. 6, the P-type transistor MP ₂ is made conductive (ON) by the control pulse S ₃ at the time of presetting, and the capacitance C ₁ is turned on. ~
Since C _o is forcibly charged, the output terminal b attains the "H" level at least within the preset period, thereby preventing the above-mentioned malfunction at the even value preset.
Note that the connection end of the P-type transistor MP ₂ to the output terminal b may be connected to the connection point between the N-type transistors MN ₁ and MN ₂ . Since MN ₁ is ON during the even value preset, it is possible to charge the capacitor C ₁ through MN ₁ , and also charge the capacitors C ₂ to _Co.

FIG. 7 shows the second P-type transistor of FIG.
This is an example in which AND gate _G1 is used instead of _MP2 . That is, the control pulse ₃ from the input terminal c and the input a ₁ are input to the AND gate G ₁ , and the logical output thereof is input to the complementary transistors MN ₁ and MP ₁ . In this way, when the control pulse ₃ is "L", the logic output becomes "L", and the first P-type transistor
By turning on MP ₁ , forced charging to capacity C ₁ becomes possible. Furthermore, a second P-type transistor _MP2 is also added.
It can be turned ON, charging the capacitors C ₂ to _{C o} can be performed, and the operation at the time of presetting can be made more reliable.

The above is an explanation when the present invention is applied to the conventional example of FIG. 1A, and it goes without saying that the present invention can be similarly applied to FIG. 1B. Furthermore, the counter decoder of the present invention is not limited to PWM circuits.

Effects of the Invention As explained above, according to the present invention, malfunctions when setting count values are solved by an extremely simple configuration that only adds one charging transistor to a multi-input CMOS gate circuit with a small number of constituent elements. Furthermore, by adding a transistor to prevent malfunctions due to charge distribution, it is possible to realize a counter decoder that can solve malfunctions during the counting period and prevent the effects of stray capacitances _C1 to _C0 .
Compared to a complete CMOS multi-input gate circuit with 2n elements, the chip size can be smaller when integrated circuit (IC), its dynamic characteristics are the same, and the current consumption can be relatively small. There is.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing the configuration of a conventional multi-input CMOS gate circuit, Figure 2 is a circuit diagram showing the configuration of a conventional 4-input NAND gate circuit that takes stray capacitance into consideration, and Figure 3 is a circuit diagram showing the configuration of a conventional multi-input CMOS gate circuit. (PWM) A circuit diagram showing a specific configuration of the circuit, FIG. 4 is an operation waveform diagram of the circuit in FIG. 3, and FIG. 6 is an operation waveform diagram when the means of the present invention is applied to the circuit of FIG. 3, and FIG. 7 is a circuit diagram of the second embodiment of the present invention.
FIG. 2 is a circuit diagram showing the configuration of a counter decoder according to an embodiment of the means. a ₁ , a ₂ , a ₃ and a ₄ ...input end, MN ₁ , MN ₂ ,
MN ₃ and MN ₄ ... Group of MOS transistors connected in series, MP ₁ ... First MOS transistor, MP ₂ ...
...Second MOS transistor, MP ₃ ...Third MOS transistor, ML ₁ ...Load element, V _SS ...First power supply, V _DD ...Second power supply, b ... Output terminal, c ...
Control pulse input terminal.

Claims (1)

[Claims] 1. MOSs of the same polarity connected in series, equal to the number of inputs, connected between the output terminal and the first power supply.
a first MOS transistor of opposite polarity connected between the output terminal and the second power supply and having a complementary configuration with the MOS transistor connected to the output terminal of the transistor group; a load element connected between the second power source and the output terminal and the second power source;
a second MOS transistor connected between a power source and having the same polarity as the first MOS transistor; and a second MOS transistor connected to the output terminal of the transistor group.
A first MOS transistor connected between a connection point on the first power supply side of the MOS transistor and the second power supply, whose input is commonly connected to the input of the first MOS transistor, and whose polarity is the same as that of the first MOS transistor.
3 MOS transistors, whose initial counting value is preset by a control pulse, which decodes the count value of a binary counter that counts clock pulses, and which uses the control pulse as an input to the second MOS transistor. 2. A group of MOS transistors of the same polarity connected in series equal to the number of inputs, connected between the output terminal and the first power source, and a group of MOS transistors of the same polarity connected between the output terminal and the second power source, of the transistor group a first MOS transistor of opposite polarity having a complementary configuration with the transistor connected to the output terminal; a load element connected between the output terminal and the second power supply; and a first MOS transistor connected to the output terminal of the transistor group. The first of the connected MOS transistors
connected between a power supply side connection point and the second power supply,
and providing an input to a third MOS transistor whose input is commonly connected to the first MOS transistor and has the same polarity as the first MOS transistor, and the complementary configured MOS transistor.
The counter is equipped with an AND gate, whose initial counting value is preset by a control pulse, and which decodes the count value of a binary counter that counts clock pulses, and which uses the control pulse as another input of the AND gate. decoder.