JPH054819B2 - - Google Patents
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- Publication number
- JPH054819B2 JPH054819B2 JP32832087A JP32832087A JPH054819B2 JP H054819 B2 JPH054819 B2 JP H054819B2 JP 32832087 A JP32832087 A JP 32832087A JP 32832087 A JP32832087 A JP 32832087A JP H054819 B2 JPH054819 B2 JP H054819B2
- Authority
- JP
- Japan
- Prior art keywords
- cracks
- ceramic substrate
- convex portion
- substrates
- ceramic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Description
(産業上の利用分野)
本発明はセラミツク基板に関し、特に半導体集
積回路素子を載置し、収納するためのパツケージ
用基板等に好適に用いられる回路素子搭載、収納
用セラミツクス基板に関するものである。
(従来の技術及び発明が解決しようとする問題
点)
従来周知のように、セラミツクは絶縁性、耐摩
耗性に優れ、化学的に安定、高硬度、熱膨張率が
小さい等の特性により、とりわけ半導体集積回路
素子を収納するためのパツケージ用基板の材料と
して極めて優れたものであり多用されている。
しかしながら、セラミツクは耐衝撃性に弱いと
いう欠点があるため、例えば第4図イに示すセラ
ミツク基板のようにして、平面視して、外側面が
一直線でかつ第4図ロに示すように端面1′が一
平面を成している場合、半導体パツケージ製造ラ
インにおいてセラミツク基板1同志が衝突した際
に、端面1′同志或は一方の基板の端面1′と他の
基板のコーナー部Rとが衝突することによつて、
これらセラミツク基板1にひび、割れ、欠けなど
を生ずることが極めて多い。
特に、半導体集積回路素子をセラミツク基板1
上に取付けたり、ワイヤーボンデイングしたりす
る多くの作業を含む半導体素子の実装工程を自動
化した組立ラインで行うような場合、セラミツク
基板1をライン上で順次、移動させる際に、傾斜
面を自重落下させたり、或は圧縮空気を吹き付け
て強制移動させるために、該セラミツク基板1同
志が激しく衝突をくり返し、これらセラミツク基
板1にひび、割れ等が多発し、その結果、製品の
歩留りや信頼性を低下させる等大きな支障を来し
ていた。
このようなセラミツク基板同志の衝突による割
れや欠けが発生する原因としては、(1)プレス成形
による場合では上下の圧縮比の相違、(2)焼成時の
温度条件、(3)外表面粗さ、(4)原料の粒径や配合比
等多くの要素が絡んでいるが、本発明者は種々実
験した結果、セラミツク基板1の端面1′同志が
正面衝突しても割れや欠けの発生は少ないが、傾
斜状に衝突した場合、即ち前方で静止しているセ
ラミツク基板の端面1′に後続のセラミツク基板
のコーナー部Rが衝突した時に、該コーナー部R
及び各稜線部にひび、割れ、欠けが頻発すること
が判明し、この結果からセラミツク基板外端面形
状を調整することによつて、ひび、割れ、欠けの
発生を有効に防止することを知見した。
(問題点を解決するための手段)
本発明者は研究の結果、回路素子搭載、収納用
セラミツクより成る方形状基板の衝突による衝撃
を受けやすい外側端面に、該基板を平面視して、
円弧状の凸状部を形成すると共に、該凸状部の基
端をなすコーナー部に丸味を形成し、かつ前記凸
状部の高さを0.05mmないし1.0mmとなるように設
定することによつて、基板同志の衝突時の衝撃に
よる基板相互の、割れ、欠け等の発生を顕著に削
減できることを知見した。
従つて、本発明の目的は上記の知見に基づき、
ひび、割れ、欠けの発生を最大限に防止するよう
に成した回路素子搭載、収納用セラミツク基板を
提供することにある。
本発明は、半導体集積回路素子を上面に搭載す
るようにした平面状のセラミツク基板、中央部に
素子搭載用の凹部を形成するように成形されたセ
ラミツク基板又は複数枚の生セラミツクシートを
積層して焼結一体化されたセラミツク基板等のよ
うに基板のひび、割れ、欠けが製品の信頼性の面
で致命的欠陥となるものに対して特に有効に適用
される。
(実施例)
以下、本発明を添付図面に示す実施例に基づき
詳細に説明する。
第1図のセラミツク基板は半導体集積回路素子
を上面に搭載するためのセラミツク基板の例を平
面図で示したものであり、セラミツク基板2にお
ける外側端面に、該端面全面に円弧状の凸部3を
形成する。
第1図における円弧状の凸状部3の膨出部は、
外側端面の中央に位置し、凸状高Dは、通常、約
0.05mm以上、好ましくは0.1mm以上が適当である。
このような凸状部を外側端面に形成した基板2
が互いに衝突する場合には、例えば第2図に示す
ように基板2,2′の外周端面の円弧状の凸状部
3,3′同志が衝突し、割れ、欠け等が起こり易
い基板のコーナー部及び各辺稜線部に衝撃力が加
わるを回避することができる。
さらに、多少傾斜状に衝突しても円弧状の凸状
部3,3′の存在により、割れ、欠けの原因とな
る直角のコーナー部が衝突することを防止でき
る。
そして仮にコーナー部が衝突するとしても、凸
部3,3′により、その衝撃力を緩和することが
でき、セラミツク基板2,2′のひび、割れ、欠
けが有効に防止される。
なお、第2図に示すように、凸状部3,3′の
基端をなすコーナー部Raを丸味形状にすると、
この効果は一層増大される。
一例として第1図にその方面図を示したような
外側形状を有する24.0mm×24.0mmの方形状で、厚
みT=1.52mm、コーナー部をRaの曲率半径0.381
mmとしたセラミツク基板の衝突を受けやすい外側
端面に、円弧状の凸状高D=0.1mm(実施例)と
D=0.02mm(比較例)の円弧状凸状部3を形成し
たセラミツク基板と、端面が一直線状の第4図図
示のごとき従来例のセラミツク基板についての衝
突テストを行い、その結果を表1に示した。
この衝突テストの条件としては、長さ100cm、
傾斜70°のトレイの上部50cm区間にテストグルー
プとして1グループ20個の各基板を平面状に連接
して並べ、自重でもつてトレイの下端に設置した
ナイロンストツパーに向けて滑降(落下)させ
る。このような滑降を10回繰り返すが、9回まで
の滑降時にひび、割れ、欠けの発生したものは滑
降させた回ごとに新規の基板と入れ換え、A乃至
Iのテストグループ10回の滑降後における初期の
基板20個についてのひび、割れ、欠けの発生した
個数を集計した。
(Industrial Application Field) The present invention relates to a ceramic substrate, and more particularly to a ceramic substrate for mounting and storing circuit elements, which is suitably used as a package substrate for mounting and housing semiconductor integrated circuit elements. (Problems to be Solved by the Prior Art and the Invention) As is well known in the art, ceramics have excellent insulation properties, wear resistance, chemical stability, high hardness, and low coefficient of thermal expansion. It is extremely excellent and widely used as a material for package substrates for housing semiconductor integrated circuit elements. However, ceramic has the disadvantage of being weak in impact resistance, so for example, when viewed from the top, the ceramic substrate shown in FIG. ′ forms one plane, when ceramic substrates 1 collide with each other in a semiconductor package manufacturing line, the end surfaces 1 ′ or the end surfaces 1 ′ of one substrate collide with the corner R of the other substrate. By doing,
Cracks, cracks, chips, etc. often occur in these ceramic substrates 1. In particular, semiconductor integrated circuit elements are mounted on a ceramic substrate 1.
When the semiconductor device mounting process, which includes many operations such as mounting on top and wire bonding, is carried out on an automated assembly line, when the ceramic substrate 1 is moved sequentially on the line, it may fall under its own weight on an inclined surface. In order to force the ceramic substrates 1 to move or move them by blowing compressed air, the ceramic substrates 1 repeatedly collide violently with each other, resulting in frequent cracks and cracks in the ceramic substrates 1, resulting in reduced product yield and reliability. This was causing major problems such as lowering the performance. The causes of cracks and chips caused by collisions between ceramic substrates include (1) differences in the compression ratio between the upper and lower parts in the case of press forming, (2) temperature conditions during firing, and (3) outer surface roughness. , (4) Although many factors are involved, such as the particle size and compounding ratio of the raw materials, the inventor has conducted various experiments and found that even if the end surfaces 1' of the ceramic substrates 1 collide head-on, no cracking or chipping will occur. Although it is rare, in the case of an inclined collision, that is, when the corner portion R of the following ceramic substrate collides with the end face 1' of the ceramic substrate stationary in front, the corner portion R
It was also found that cracks, cracks, and chips frequently occur at each ridgeline, and based on these results, it was discovered that the occurrence of cracks, breaks, and chips can be effectively prevented by adjusting the shape of the outer end surface of the ceramic substrate. . (Means for Solving the Problems) As a result of research, the inventor of the present invention found that the outer end face of a rectangular substrate made of ceramic for mounting and storing circuit elements is susceptible to impact from collision, when viewed from above,
In addition to forming an arc-shaped convex portion, a corner portion forming the base end of the convex portion is rounded, and the height of the convex portion is set to be 0.05 mm to 1.0 mm. Therefore, it has been found that the occurrence of cracks, chips, etc. between the substrates due to impact when the substrates collide with each other can be significantly reduced. Therefore, the purpose of the present invention is based on the above findings,
To provide a ceramic substrate for mounting and storing circuit elements, which is designed to prevent the occurrence of cracks, cracks, and chips to the maximum extent possible. The present invention comprises a planar ceramic substrate on which a semiconductor integrated circuit element is mounted, a ceramic substrate shaped to form a recess for mounting the element in the center, or a plurality of raw ceramic sheets stacked together. This method is particularly effectively applied to ceramic substrates that are sintered and integrated, where cracks, breaks, and chips in the substrate can be a fatal defect in terms of product reliability. (Examples) Hereinafter, the present invention will be described in detail based on examples shown in the accompanying drawings. The ceramic substrate shown in FIG. 1 is a plan view showing an example of a ceramic substrate for mounting a semiconductor integrated circuit element on the top surface.A ceramic substrate 2 has an arc-shaped convex portion 3 on the entire outer end surface of the ceramic substrate 2. form. The bulge of the arc-shaped convex portion 3 in FIG.
Located in the center of the outer end surface, the convex height D is usually about
A suitable value is 0.05 mm or more, preferably 0.1 mm or more. A substrate 2 with such a convex portion formed on the outer end surface
If these collide with each other, for example, as shown in FIG. 2, the arc-shaped convex portions 3, 3' on the outer peripheral end surfaces of the substrates 2, 2' will collide with each other, and the corners of the substrate where cracks, chips, etc. are likely to occur will be affected. It is possible to avoid applying an impact force to the portion and each side ridgeline portion. Furthermore, even if there is a collision in a somewhat inclined manner, the presence of the arcuate convex portions 3, 3' prevents the right-angled corner portions from colliding, which could cause cracks or chips. Even if the corner portions collide, the convex portions 3, 3' can alleviate the impact force, effectively preventing cracks, breaks, and chips in the ceramic substrates 2, 2'. In addition, as shown in FIG. 2, if the corner portions Ra forming the base ends of the convex portions 3 and 3' are rounded,
This effect is further enhanced. As an example, it is a rectangular shape of 24.0 mm x 24.0 mm with an outer shape as shown in Fig. 1, the thickness T = 1.52 mm, and the radius of curvature of Ra at the corner part is 0.381.
A ceramic substrate having an arcuate convex height D=0.1 mm (example) and a convex arcuate portion 3 having a height D=0.02 mm (comparative example) is formed on the outer end surface of the ceramic substrate, which is susceptible to collisions. A collision test was conducted on a conventional ceramic substrate as shown in FIG. 4 having a straight end face, and the results are shown in Table 1. The conditions for this collision test are: length 100cm;
A test group of 20 test boards were arranged in a flat 50cm section at the top of a tray with an inclination of 70°, and were allowed to slide down (fall) using their own weight toward a nylon stopper installed at the bottom of the tray. This kind of downhill skiing is repeated 10 times, and if any cracks, cracks, or chips occur during up to 9 downhill runs, they are replaced with new boards after each downhill run. The number of cracks, cracks, and chips that occurred on the 20 initial boards was counted.
【表】
上記テスト結果から明らかなように、通常のセ
ラミツク基板の場合、基板外側端面に円弧状の凸
状部をD=0.1mmの凸状高を形成しておくことに
よつて基板同志の衝突によるひび、割れ、欠け等
の発生を、従来の基板の場合に比して大幅に低減
することが可能となる。なお、凸上部Dの高さを
0.1mmよりも大きくした場合にあつても基板同志
の衝突によるひび、割れ、欠け等の発生は大幅に
低減されることを確認している。
そして、円弧状凸状高Dとしては0.05mm以上で
あれば、実験の結果トータル不良率が10%以下に
なることも確認した。
特に、0.1mm以上になるとひび、割れ、欠け等
を防止する効果は、表1記載から明らかなごと
く、一桁の不良率であつてきわめて優良である。
しかし、凸状高Dが大きくなるにつれて基板の
形状、特に外側端面形状が回路素子の搭載、収納
用セラミツク基板本来の方形状を保持し得ない状
態までに形成し、すなわち約1.0mm程度を越える
と変形が顕著となり、基板の成形が面倒になる。
よつて、円形凸状高Dは0.05mmないし1.0mmの
範囲が好ましい。
このようなセラミツクより成る基板の成形法と
しては粉体プレス法、ドクターブレード法による
グリーン(生)シートからの打ち抜き法その他押
出法で成形した後、円形刃で切断したり、或は焼
結後に研磨加工して凸状部を成形するなど、それ
ぞれに最も適した方法を用いればよい。
以上のように、本発明の回路素子搭載、収納用
セラミツク基板によれば、衝突による衝撃を受け
やすい外側端面に平面視して円弧状の凸状部を形
成すると共に、該凸状部の基端部をなすコーナー
部に丸味を形成し、かつ前記凸状部の高さを0.5
mmないし1.0mmとなるように設定したことにより、
各セラミツク基板同志が衝突した場合でも、ひ
び、割れ、欠け等の発性を大幅に低減させるとが
可能となり、自動化された組立ラインによる組立
工程等苛酷な条件下においても歩留まりを顕著に
向上させることができ、合わせて品質、信頼性を
向上させることができるため、半導体装置等に好
適に使用される。
その他として、本発明にいて、すなち回路素子
搭載、収納用セラミツク基板の衝突による衝撃を
受けやすい外側端面に平面視して円弧状の凸状部
を形成すると共に、該凸状部の基端部をなすコー
ナー部に丸味を形成し、かつ前記凸状部の高さを
0.05mmないし1.0mmとなるように設定したものに
おいて、加えて第3図図示のごとくセラミツク基
板2における厚み方向端面全面に、円弧状の丸み
を帯びた凸状部31を形成することは、実験の結
果からみて、各セラミツク基板同志が衝突した場
合でも、ひび、割れ、欠け等の発生を大幅に低減
する効果を発揮するのでより好適である。
第3図における円弧状の凸状部31の先端は厚
み方向端面中央に位置するものであるが、凸状高
dは基板2の厚Tとも関連し、厚さT=1.52mmの
場合、凸状高d=0.05〜0.1mm程度でd/T≒
0.032〜0.066が適当であることが実験上判明して
いる。
このような凸状部を厚み方向端面に形成した基
板2が互いに衝突する場合、例えば基板2,2′
の外周端面の凸状部31,31同志が衝突するこ
とにより、割れ、欠け等が起こり易いコーナー部
及び各辺稜線部に衝撃力が加わることを回避する
ことができる。さらに、多少傾斜状に衝突して
も、凸状部31の存在により、割れ、欠けの原因
となる直角のコーナー部が衝突することを防止す
ることができる。そして仮に衝突するとしても凸
状部31により、その衝撃力を緩和することがで
き、セラミツク基板2,2′のひび、割れ、欠け
が有効に防止される。
(発明の効果)
以上のように、本発明の回路素子搭載、収容用
セラミツク基板によれば、各セラミツク基板同志
が衝突した場合でも、ひび、割れ、欠け等の発生
を大幅に低減させることが可能となる。
したがつて、自動化された組立ラインによる組
立工程等苛酷な条件下においても歩留まりを顕著
に向上させることができ、合わせて品質、信頼性
を向上させることができるため、半導体装置等に
好適に使用される。[Table] As is clear from the above test results, in the case of ordinary ceramic substrates, by forming an arc-shaped convex portion with a convex height of D = 0.1 mm on the outer end surface of the substrate, it is possible to improve the distance between the substrates. The occurrence of cracks, cracks, chips, etc. due to collisions can be significantly reduced compared to the case of conventional substrates. In addition, the height of the convex upper part D is
It has been confirmed that even when the thickness is larger than 0.1 mm, the occurrence of cracks, breaks, chips, etc. caused by collisions between boards is significantly reduced. It was also confirmed through experiments that if the height D of the arcuate convexity was 0.05 mm or more, the total defective rate would be 10% or less. In particular, when the thickness is 0.1 mm or more, the effect of preventing cracks, cracks, chips, etc. is extremely excellent, as is clear from Table 1, with a single-digit defective rate. However, as the convex height D increases, the shape of the board, especially the shape of the outer end surface, becomes such that it cannot maintain the original rectangular shape of the ceramic board for mounting and storing circuit elements, that is, it exceeds about 1.0 mm. The deformation becomes noticeable and the molding of the substrate becomes troublesome. Therefore, the height D of the circular convex shape is preferably in the range of 0.05 mm to 1.0 mm. Forming methods for such ceramic substrates include powder pressing, punching from a green sheet using a doctor blade method, or other extrusion methods, followed by cutting with a circular blade, or after sintering. The most suitable method may be used for each method, such as polishing to form a convex portion. As described above, according to the ceramic substrate for mounting and accommodating circuit elements of the present invention, an arcuate convex portion is formed in plan view on the outer end surface which is susceptible to impact from a collision, and the base of the convex portion is formed. The corners forming the ends are rounded, and the height of the convex portion is set to 0.5.
By setting it to be mm or 1.0 mm,
Even if ceramic substrates collide with each other, it is possible to significantly reduce the occurrence of cracks, cracks, chips, etc., and significantly improve yields even under harsh conditions such as assembly processes using automated assembly lines. It is also possible to improve quality and reliability, so it is suitably used for semiconductor devices and the like. In addition, in the present invention, an arc-shaped convex portion is formed in a plan view on the outer end surface which is susceptible to impact due to a collision of a ceramic substrate for mounting and storing circuit elements, and a base of the convex portion is formed. The corner portion forming the end portion is rounded, and the height of the convex portion is
As shown in FIG. 3, it was experimentally possible to form an arcuate rounded convex portion 31 on the entire thickness direction end face of the ceramic substrate 2 in the case where the thickness was set to be 0.05 mm to 1.0 mm. In view of the above results, even if the ceramic substrates collide with each other, it is more preferable because it exhibits the effect of significantly reducing the occurrence of cracks, cracks, chips, etc. The tip of the arc-shaped convex portion 31 in Fig. 3 is located at the center of the end surface in the thickness direction, but the convex height d is also related to the thickness T of the substrate 2, and when the thickness T = 1.52 mm, the convex At height d=0.05~0.1mm, d/T≒
It has been experimentally found that 0.032 to 0.066 is appropriate. When the substrates 2 having such convex portions formed on the end faces in the thickness direction collide with each other, for example, the substrates 2, 2'
Collision between the convex portions 31 and 31 on the outer circumferential end surface can prevent impact force from being applied to corner portions and ridgeline portions of each side where cracking, chipping, etc. are likely to occur. Furthermore, even if a collision occurs in a somewhat inclined manner, the presence of the convex portion 31 can prevent collision at a right-angled corner, which could cause cracking or chipping. Even if there is a collision, the impact force can be alleviated by the convex portion 31, and cracks, breaks, and chips in the ceramic substrates 2, 2' can be effectively prevented. (Effects of the Invention) As described above, according to the ceramic substrate for mounting and accommodating circuit elements of the present invention, even if the ceramic substrates collide with each other, the occurrence of cracks, cracks, chips, etc. can be significantly reduced. It becomes possible. Therefore, it is possible to significantly improve yield even under harsh conditions such as assembly processes using automated assembly lines, and at the same time improve quality and reliability, making it suitable for use in semiconductor devices, etc. be done.
第1図は本発明実施例のセラミツク基板の平面
図、第2図は同セラミツク基板同志の衝突態様例
を説明するための図、第3図は本発明の他の実施
例のセラミツク基板の端部断面図、第4図イは従
来のセラミツク基板の平面図、第4図ロは同側面
図である。
1:従来例のセラミツク基板、1′:端面、2,
2′:本発明実施例のセラミツク基板、3,3′:
平面視円弧状の凸状部、31:断面円弧状の凸状
部、R,Ra:コーナー部。
FIG. 1 is a plan view of a ceramic substrate according to an embodiment of the present invention, FIG. 2 is a diagram illustrating an example of how the ceramic substrates collide with each other, and FIG. 3 is an end view of a ceramic substrate according to another embodiment of the present invention. 4A is a plan view of a conventional ceramic substrate, and FIG. 4B is a side view of the same. 1: Conventional ceramic substrate, 1': End surface, 2,
2': Ceramic substrate of the embodiment of the present invention, 3, 3':
Convex portion having an arc shape in plan view, 31: Convex portion having an arc shape in cross section, R, Ra: Corner portion.
Claims (1)
衝撃を受けやすい外側端面に、該基板を平面視し
て、円弧状の凸状部を形成すると共に、該凸状部
の基端をなすコーナー部に丸味を形成し、かつ前
記凸状部の高さを0.05mmないし1.0mmとなるよう
に設定し、基板同志の衝突時の衝撃による基板相
互の割れ、欠けの発生を防止するようにしたこと
を特徴とする回路素子の搭載、収納用セラミツク
ス基板。1. An arcuate convex portion is formed on the outer end surface of the rectangular ceramic substrate, which is susceptible to shocks caused by collision, when the substrate is viewed from above, and a corner portion forming the base end of the convex portion is rounded. and the height of the convex portion is set to 0.05 mm to 1.0 mm to prevent mutual cracking or chipping of the substrates due to impact when the substrates collide with each other. A ceramic substrate for mounting and storing circuit elements.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32832087A JPS6413747A (en) | 1987-12-26 | 1987-12-26 | Ceramic board for installing and containing circuit element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32832087A JPS6413747A (en) | 1987-12-26 | 1987-12-26 | Ceramic board for installing and containing circuit element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6413747A JPS6413747A (en) | 1989-01-18 |
| JPH054819B2 true JPH054819B2 (en) | 1993-01-20 |
Family
ID=18208922
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP32832087A Granted JPS6413747A (en) | 1987-12-26 | 1987-12-26 | Ceramic board for installing and containing circuit element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6413747A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2581629Y2 (en) * | 1991-07-31 | 1998-09-24 | 京セラ株式会社 | Ceramic substrate |
| JPH05299702A (en) * | 1992-04-17 | 1993-11-12 | Stanley Electric Co Ltd | Led array |
-
1987
- 1987-12-26 JP JP32832087A patent/JPS6413747A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6413747A (en) | 1989-01-18 |
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