JPH0551188B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which a high-power, high-speed, high-frequency switching element is monolithically realized.

[Prior Art] Several types of high-power, high-speed, high-frequency switching elements with low on-resistance have been used in the past, such as the one shown in FIG. 3.

FIG. 3 is a sectional view showing the structure of a conventional monolithically conduction modulated metal oxide semiconductor field effect transistor (hereinafter referred to as a CAT device). First, the configuration of this CAT element will be explained. In the figure, the configuration of the CAT element is that of a conventional double-diffused metal oxide semiconductor field effect transistor (hereinafter referred to as MOSFET), the n ⁺ type drain substrate is replaced with a p ⁺ type drain/collector layer. . More specifically, a drain drift layer 6 made of, for example, an n-type epitaxial layer is formed on one surface of the p ⁺ -type drain/collector layer 7 . A plurality of p-type base regions 5 are formed at intervals on the surface of the drain drift layer 6, and two n ⁺ -type source/emitter regions 4 are formed at intervals on the surface of the p-type base region 5. are formed separately. An oxide film 3 made of silicon dioxide, for example, is formed on the surface of the drain drift layer 6 between the p-type base regions 5, the surface of the peripheral part of the p-type base region 5, and a part of the surface of the n ⁺ type source/emitter region 4. ing. A gate electrode 2 made of metal is formed inside the oxide film 3, and this gate electrode extends up to above the n ⁺ type source/emitter region 4. Further, a source/emitter electrode 1 is formed on the central surface of the p-type base region 5, another part of the surface of the n ⁺ type source/emitter region 4, and the surface of the oxide film 3. here,
The n ⁺ type source/emitter region 4, the p type base region 5, and the drain drift layer 6 constitute an npn transistor parasitic to the MOSFET, and the p type base region 5, the drain drift layer 6, and the p ⁺ type drain/collector layer 7 constitutes a pnp transistor that is parasitic to the MOSFET. A drain/collector electrode 8 is formed on the other surface of the p ⁺ type drain collector layer 7 . In addition, G is the gate electrode terminal, S/
E is a source/emitter electrode terminal, and D/C is a drain/collector electrode terminal.

FIG. 4 is a diagram showing an equivalent circuit of the CAT element shown in FIG. 3. Considering the ideal current flow, the equivalent circuit of this CAT element should be a series connection of a MOSFET and a pin diode _D2 , but in reality it consists of a MOSFET and a parasitic npn diode.
It is a combination of a transistor and a thyristor made up of a PNP transistor.

Next, the operation of this CAT element will be explained.
When the gate electrode terminal G and the source/emitter electrode terminal S/E are short-circuited and a reverse bias voltage is applied between the drain/collector electrode terminal D/C and the source/emitter electrode terminal S/E, the pin diode D ₂ reverses. This becomes a bias and reverse bias blocking characteristics appear.
Furthermore, when a forward bias voltage is applied between the drain/collector electrode terminal D/C and the source/emitter electrode terminal S/E, the diode _D1 becomes reverse biased and a forward bias blocking characteristic appears. In this state,
When a voltage higher than the threshold voltage of the MOSFET is applied between the gate electrode terminal G and the source/emitter electrode terminal S/E, a channel is formed in the p-type base region 5 and the MOSFET becomes operational, and at the same time the pin diode D ₂ causes a pin diode dynamic phenomenon, holes are injected from the p ⁺ type drain/collector layer 7 to the drain drift layer 6, the conductivity of this drain drift layer increases, and the CAT element turns on with low on-resistance. . Also, CAT
To turn off the device, short-circuit gate electrode terminal G and source/emitter electrode terminal S/E to reduce the voltage applied between these terminals.
The voltage is lowered to below the threshold voltage of the MOSFET, thereby returning the inverted region on the surface of the p-type base region 5 under the gate electrode 2 to its original state and stopping the supply of electrons to the drain drift layer 6. At the start of turn-off, a large amount of electrons injected into the drain drift layer 6 are concentrated, but these electrons
A current due to holes is injected into the p ⁺ type drain/collector layer 7 and a corresponding amount of current flows into the p type base region 5.
flows to If this state continues, the concentration of electrons in the drain drift layer 6 will decrease, but in order for the CAT element to turn off, the remaining hole and electron plasma must cancel each other out through recombination.

The above is the case when the thyristor region parasitic to the MOSFET does not latch at turn-on.
Explaining the operation of CAT devices, the biggest problem with CAT devices is that the thyristor region causes a latching phenomenon at low current levels, and when the thyristor region latches, the CAT device loses its gate control ability. becomes difficult to turn off. The cause of the latching phenomenon is that the NPN in the thyristor region at high current density during turn-on.
This is because the transistor and the pnp transistor have a mutual feedback effect. The conditions for the thyristor region to latch when turned on are:
The sum of the DC current amplification factors h _FE of each of the npn transistor and pnp transistor is >1,
The voltage drop V _S at the resistance R _S of the p-type base region 5 of the npn transistor due to the Hall current is 0.4 to 300〓.
This is the case when the voltage exceeds 0.8V.

FIG. 5 is a sectional view showing the structure of another CAT element that has solved the above problems to a certain level. In the figure, a p ⁺ type base center region 50 with a high impurity concentration is formed in the center of the p type base region 5 , and an n ⁺ type buffer layer 9 is formed between the drain drift layer 6 and the p + type drain ^/ collector layer 7 . is inserted. Further, the equivalent circuit of this CAT element is the same as the circuit shown in FIG. The p ⁺ -type base center region 50 lowers the direct current amplification factor h _FE of the parasitic npn transistor, and the n ⁺ -type buffer layer 9 suppresses the injection of holes from the p ⁺ -type drain/collector layer 7 to the drain drift layer 6 parasitic
By lowering the DC current amplification factor _hFE of the pnp transistor, the CAT element is made less likely to latch when turned on. That is, the latching current level is increased compared to the CAT element shown in FIG.

[Problems to be solved by the invention] In conventional CAT devices used as high-power, high-speed, high-frequency switching devices, the current level at which the thyristor region parasitic to the MOSFET latches is low, making it difficult for the CAT device to operate normally. It is necessary to use these at a current level below the latching level, and the problem is that the gate control range is narrow.

This invention was made to solve the above-mentioned problems, and its purpose is to obtain a semiconductor device that can widen the gate control range by increasing the latching current level of the thyristor region parasitic to the MOSFET. .

[Means for Solving the Problems] A semiconductor device according to the present invention includes a first conductivity type semiconductor substrate having a first main surface and a second main surface and having a high impurity concentration and serving as a drain layer; A first main surface with a low impurity concentration that becomes a drain layer and has a first main surface that is in contact with the first main surface of the first conductivity type semiconductor substrate and a second main surface that is opposite to the first main surface. a conductivity type semiconductor layer formed in an island shape with an exposed surface in a predetermined region of the second main surface of the first conductivity type semiconductor layer, and an end portion with a low impurity concentration and a region formed deeper than this end portion. a base region made of at least two second conductivity type semiconductors, having a central portion with a high impurity concentration and a bottom surface with a high impurity concentration; a source region made of a first conductivity type semiconductor with a high impurity concentration and arranged to include an interface between the first conductivity type semiconductor layer and the central part; and an exposed surface on a second main surface of the first conductivity type semiconductor layer. An insulating film is formed on the exposed surfaces of the drain layer, the base region, and the source region, spanning the drain layer and the base region and source region, which are arranged adjacent to each other and facing each other through the drain layer. a gate electrode disposed through the semiconductor substrate, an exposed surface on the second main surface of the first conductivity type semiconductor substrate, and a bottom surface within the first conductivity type semiconductor substrate, and the bottom surface correctly faces the source region. the bottom surface is substantially equal to the width of the opposing source region, and the bottom surface is close to the first main surface of the first conductivity type semiconductor layer; The second conductivity type semiconductor region has a high impurity concentration and is connected to the same potential as the drain layer of the first conductivity type semiconductor substrate.

[Function] In the present invention, the second conductivity type semiconductor region having a high impurity concentration has an exposed surface on the second main surface of the first conductivity type semiconductor substrate and a bottom surface within the first conductivity type semiconductor substrate. , the bottom surface is arranged in an island shape so as to correctly face the source region, the width of the bottom surface is substantially equal to the width of the opposing source region, and the bottom surface is arranged in the first conductivity type semiconductor layer. Since it is close to the main surface and is connected to the same potential as the drain layer of the first conductivity type semiconductor substrate, injection of carriers from the second conductivity type semiconductor region to the first conductivity type drain semiconductor layer is suppressed. The DC current amplification factor h _FE of the transistor parasitic on the transistor decreases. In addition, the injected carrier is in the first region directly under the gate electrode.
The flow is divided into a small portion flowing to the conductive semiconductor layer and a large portion flowing toward the center of the base region. In this way, carriers are efficiently injected from the second conductivity type semiconductor region into the first conductivity type drain semiconductor layer, so that the conductivity of the first conductivity type drain semiconductor layer is modulated to the same degree as in the prior art.

[Example] Hereinafter, an example of the present invention will be described with reference to the drawings. In the description of this embodiment, the description of parts that overlap with the description of the conventional technology will be omitted as appropriate.

FIG. 1 is a sectional view showing the structure of a monolithically constructed CAT element according to an embodiment of the present invention. The configuration of this embodiment is as follows except for the following points.
The configuration is the same as the one shown in the figure. That is, an n ⁺ type drain/collector layer 10 is formed on the surface of the drain/collector electrode 8 instead of the p ⁺ type drain/collector layer 7, and a drain drift layer 6 is formed on one surface of this n ⁺ type drain/collector layer. It is formed. Further, a p ⁺ type drain/collector region 70 is partially formed on the other surface of the n ⁺ type drain/collector layer 10 directly below each n ⁺ type source/emitter region 4, and this p ⁺ type drain/collector region The bottom of the drain drift layer 6 is spaced apart from the surface of the drain drift layer 6, and this space is the n ⁺ type buffer layer 100.
is formed. Further, as in FIG. 5, a p ⁺ -type base center region 50 is formed in the center of the p-type base region 5 . n ⁺ type source/emitter region 4
and p type base region 5, p ⁺ type base central region 50
, the drain drift layer 6, the n ⁺ type drain/collector layer 10 constitute an npn transistor parasitic to the MOSFET, and the p type base region 5, the p ⁺ type base central region 50, the drain drift layer 6, the n ⁺ type drain/collector layer The collector layer 10 and the p ⁺ type drain/collector region 70 constitute a pnp transistor parasitic to the MOSFET, and both transistors constitute a parasitic thyristor region.

FIG. 2 is a diagram showing an equivalent circuit of the CAT element shown in FIG. 1. In the figure, the equivalent circuit of this CAT element is an n-channel MOSFET in which a pin diode _D2 is parasitic between the gate electrode terminal G and the drain/collector electrode terminal D/C terminal.

Next, the operation of this CAT element will be explained.
A p ⁺ -type drain/collector region 70 is partially formed on the other surface of the n ⁺ -type drain/collector layer 10 directly below each n ⁺ -type source/emitter region ⁴ , and Since the n ⁺ type buffer layer 100 is formed on the bottom surface, the p ⁺ type drain/collector region 70 (pnp
Holes are partially injected from the p ⁺ emitter of the transistor into the drain drift layer 6 , and this injection is suppressed by the n ⁺ type buffer layer 100 . For this reason, the transport efficiency of the base region of the parasitic pnp transistor is reduced, and its direct current amplification factor h _FE is significantly lower than that of a conventional CAT element.
Further, the holes from the p ⁺ type drain/collector region 70 flow straight upwards while being squeezed through the drain drift layer 6, and most of the holes are located in the peripheral area of the p type base region 5 and a portion thereof. is p ⁺
It reaches the central region 50 of the shaped base and exits to the n ⁺ type source/emitter electrode 1. Therefore, the voltage drop V _S in the base region R _S due to the Hall current is
Smaller than CAT elements. In this way, in this CAT element, the DC current amplification factor h _FE of the parasitic pnp transistor decreases, and the voltage drop V _S in the p-type base region and p ⁺ type base central region 50 of the parasitic npn transistor decreases. Traditional
At current levels that cause latching in the CAT device, the parasitic thyristor region no longer latches. In other words, the latching current level is higher than that of conventional CAT elements. For this reason,
Turn-off of the CAT element becomes easier, and high-speed high-frequency switching characteristics are improved. Also, this
With CAT devices, the latching current level increases as described above, so the gate control range is wider than with conventional CAT devices, and the CAT
It becomes possible to increase the current density of the device, and by reducing the chip size, it is possible to reduce the size and cost of the CAT device. In addition, the drain drift layer 6
It is effective to generate the conductivity modulation directly under the n ⁺ type source/emitter region 4, and the conductivity modulation directly under the p ⁺ type base central region 50 is unnecessary. For this reason, p ⁺ type drain/
The collector region 70 is partially formed only directly under the n ⁺ type source/emitter region 4, and the drain drift layer 6 is formed from the p ⁺ type drain/collector region 70.
Holes are efficiently injected into the CAT element, thereby achieving the same conductivity modulation effect as conventional CAT elements and lowering the on-state voltage. Furthermore, in the conventional CAT element, the p ⁺ -type drain/collector layer 7 is formed over the entire area of the drain drift layer 6, so that the holes accumulated in the drain drift layer 6 at the time of turn-off are p ⁺ However, in this CAT element, the holes are blocked by the p ⁺
It is blocked only in a narrow area at the bottom of the type drain/collector region 70 and can easily penetrate into the surrounding n ⁺ type drain/collector layer 10.
This also facilitates the turn-off operation of the CAT element and improves high-speed high-frequency switching characteristics.

In the above embodiment, the CAT element is of n-type, but the present invention is applicable to each layer in FIG.
Needless to say, the present invention can also be applied to a p-type CAT element in which the conductivity types of each region are reversed.

[Effects of the Invention] As described above, according to the invention, the second conductivity type semiconductor region having a high impurity concentration is formed on the second main surface of the first conductivity type semiconductor substrate so as to correctly face the first conductivity type source semiconductor region. Formed in an island shape, the width of the bottom surface of the second conductivity type semiconductor region is substantially equal to the width of the opposing source region and is close to the first main surface of the first conductivity type drain semiconductor layer. It is possible to obtain a semiconductor device that can widen the gate control range by increasing the latching current level of the thyristor region parasitic to the MOSFET.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing the structure of a monolithically constructed CAT element according to an embodiment of the present invention. FIG. 2 is a diagram showing an equivalent circuit of the CAT element shown in FIG. 1. FIG. 3 is a cross-sectional view showing the structure of a conventional monolithically constructed CAT element. FIG. 4 is a diagram showing an equivalent circuit of a conventional CAT element. FIG. 5 is a sectional view showing the structure of another conventional monolithically constructed CAT element. In the figure, 1 is a source/emitter electrode, 2 is a gate electrode, 3 is an oxide film, 4 is an n ⁺ type source/emitter region, 5 is a p type base region, 50 is a p ⁺ type base center region, and 6 is a drain drift. layer, 70
is a p ⁺ type drain/collector region, 8 is a drain/collector electrode, 10 is an n ⁺ type drain/collector layer, and 100 is an n ⁺ type buffer layer. In addition,
The same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A first conductivity type semiconductor substrate having a first principal surface and a second principal surface and having a high impurity concentration and serving as a drain layer; a first conductivity type semiconductor layer with a low impurity concentration and serving as a drain layer, the first conductivity type semiconductor layer having a first principal surface in contact with the principal surface and a second principal surface mutually opposing the first principal surface; A central portion with a high impurity concentration, which is formed in an island shape with an exposed surface in a predetermined region of the second main surface of the semiconductor layer, and has an end portion with a low impurity concentration and a bottom surface formed deeper than the end portion. a base region made of at least two second conductivity type semiconductors, and each base region has an exposed surface in a predetermined region in an island shape and includes a boundary surface between the end portion and the center portion. a source region made of a first conductivity type semiconductor having a high impurity concentration; and a drain layer having an exposed surface on the second main surface of the first conductivity type semiconductor layer, each facing the drain layer through the drain layer. a gate electrode disposed via an insulating film on the exposed surfaces of the drain layer, the base region, and the source region, spanning the base region and the source region disposed adjacent to each other in sequence on the side of the base region; The first conductivity type semiconductor substrate has an exposed surface on the second main surface and a bottom surface within the first conductivity type semiconductor substrate, and the bottom surface is disposed in an island shape so as to correctly face the source region, and the bottom surface is substantially equal to the width of the opposing source region, and the bottom surface is substantially equal to the width of the opposing source region.
A semiconductor device comprising: a second conductive type semiconductor region having a high impurity concentration and close to a first main surface of the conductive type semiconductor layer and further connected to the same potential as the drain layer of the first conductive type semiconductor substrate.