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JPH055166B2 - - Google Patents
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JPH055166B2 - - Google Patents

Info

Publication number
JPH055166B2
JPH055166B2 JP60027330A JP2733085A JPH055166B2 JP H055166 B2 JPH055166 B2 JP H055166B2 JP 60027330 A JP60027330 A JP 60027330A JP 2733085 A JP2733085 A JP 2733085A JP H055166 B2 JPH055166 B2 JP H055166B2
Authority
JP
Japan
Prior art keywords
thin film
positive resist
wet etching
electrode
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP60027330A
Other languages
Japanese (ja)
Other versions
JPS61185924A (en
Inventor
Ikuo Yamamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP60027330A priority Critical patent/JPS61185924A/en
Publication of JPS61185924A publication Critical patent/JPS61185924A/en
Publication of JPH055166B2 publication Critical patent/JPH055166B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/01Manufacture or treatment
    • H10D64/011Manufacture or treatment of electrodes ohmically coupled to a semiconductor

Landscapes

  • Weting (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Electrodes Of Semiconductors (AREA)

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は半導体装置の製造方法に関し、さらに
詳しくは、ポジ型レジストのパターニング後、湿
式エツチングを行うことにより電極および配線パ
ターンを形成する方法に関し、MOS−LSI半導
体装置に利用される。
Detailed Description of the Invention (Field of Industrial Application) The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming electrodes and wiring patterns by performing wet etching after patterning a positive resist. , used in MOS-LSI semiconductor devices.

(従来の技術) 従来の半導体装置は、電極および配線材料とし
てAl,Al−Si合金、多結晶Si等反射率の高い材
料を使用し、ネガ型レジストを使用したホトリソ
グラフイ行程で電極および配線パターンを形成し
ていた。
(Prior art) Conventional semiconductor devices use materials with high reflectivity such as Al, Al-Si alloy, and polycrystalline silicon as electrode and wiring materials, and the electrodes and wiring are formed in a photolithography process using a negative resist. It was forming a pattern.

ところが、微細な電極および配線パターンを形
成するためには、下地の反射の影響を受けにくい
ポジ型レジストを使用したホトリソグラフイ行程
を行わなければならない。
However, in order to form fine electrodes and wiring patterns, it is necessary to perform a photolithography process using a positive resist that is less susceptible to the effects of reflection from the underlying layer.

(発明が解決しようとする問題点) 上記した方法では、ポジ型レジストの成分が光
反応もしくは熱分解して発生するガスの突出跡
が、下地の電極材料とポジ型レジストとの間に無
数の空〓として残る。そのため、湿式エツチング
ではこの空〓にエツチヤントがしみ込むため、電
極および配線パターンaが第3図に示すような形
状となり、微細な直線的な電極、配線加工が行え
ないという問題があつた。図において、bは配線
部、cは電極部、dはコンタクト部である。一
方、湿式エツチングのかわりに乾式エツチング
(例えばプラズマエツチング)を用いれば微細で
直線的な電極、配線加工を行えるが、乾式エツチ
ングは高額であるため製造コストが高くなるとい
う問題があつた。
(Problems to be Solved by the Invention) In the above method, there are countless protruding traces of gas generated by photoreaction or thermal decomposition of components of the positive resist between the underlying electrode material and the positive resist. It remains empty. Therefore, in wet etching, the etchant penetrates into this void, resulting in the electrode and wiring pattern a having a shape as shown in FIG. 3, which poses a problem in that fine linear electrode and wiring processing cannot be performed. In the figure, b is a wiring part, c is an electrode part, and d is a contact part. On the other hand, if dry etching (for example, plasma etching) is used instead of wet etching, fine and linear electrodes and wiring can be processed, but dry etching is expensive, resulting in an increase in manufacturing costs.

(問題点を解決するための手段) 本発明にかかる半導体装置の製造方法は、半導
体基板に形成された絶縁膜上に電極および配線パ
ターンとなる薄膜を、ポジ型レジストのパターニ
ング後、湿式エツチングを行うことにより形成す
る方法において、前記ポジ型レジストのパターニ
ング後、湿式エツチングを行う前に、半導体基板
を有機溶剤に浸すか又はその雰囲気中にさらし、
さらに熱乾燥を行うものである。
(Means for Solving the Problems) A method for manufacturing a semiconductor device according to the present invention involves forming a thin film that will become an electrode and a wiring pattern on an insulating film formed on a semiconductor substrate by wet etching after patterning a positive resist. After patterning the positive resist and before performing wet etching, the semiconductor substrate is immersed in an organic solvent or exposed to an atmosphere thereof;
Furthermore, heat drying is performed.

(作用) 半導体基板を有機溶剤を浸すか又はその雰囲気
中にさらした後、熱乾燥を施すことで、ポジ型レ
ジストと下地の薄膜との間に生じる空隙が埋めら
れる。
(Function) By immersing the semiconductor substrate in an organic solvent or exposing it to its atmosphere, and then thermally drying it, the gap created between the positive resist and the underlying thin film is filled.

(実施例) 本発明にかかる半導体装置の製造方法を、第1
図a〜cの製造行程を参照して説明する。
(Example) The method for manufacturing a semiconductor device according to the present invention is described in the first example.
This will be explained with reference to the manufacturing process shown in Figures a to c.

(a) 半導体基板1上に形成されたSiO2等の絶縁
膜2上に、薄膜3が形成される。薄膜3の材料
としてはAl,Al−Si合金、多結晶Si等の反射
率の高い材料が用いられる。この薄膜3上に、
ポジ型レジストを塗布し、マスク合せ、露光、
現像等の一連のホトリソグラフイ行程を経てポ
ジ型のレジストパターン4が形成される。この
とき、レジストパターン4と薄膜3との間に
は、レジストパターン4の成分が光反応もしく
は熱分解して発生したガスの突出跡が無数の空
〓5,5…として残つている〔第1図a参照〕。
(a) A thin film 3 is formed on an insulating film 2 such as SiO 2 formed on a semiconductor substrate 1. As the material for the thin film 3, a material with high reflectance such as Al, Al-Si alloy, polycrystalline Si, etc. is used. On this thin film 3,
Apply positive resist, mask alignment, exposure,
A positive resist pattern 4 is formed through a series of photolithography steps such as development. At this time, between the resist pattern 4 and the thin film 3, protruding traces of gas generated by photoreaction or thermal decomposition of the components of the resist pattern 4 remain as countless voids 5, 5... See Figure a].

(b) 次に、このレジストパターン4が形成された
半導体基板1を、有機溶剤に浸すかその雰囲気
中にさらす等の処理を行う。有機溶剤として
は、キシレンや酢酸N−ブチルが使用可能であ
り、レジストを熱だれさせ得るような(一部溶
解させ得るような)性質のものであればよい。
これによつて、レジストパターン4の周囲を覆
つている熱的に安定な物質を除去もくしは変質
させる。この後熱乾燥を行い、このときの温度
でレジストパターン4を十分に変型させ、空〓
5,5…を埋め込む。〔第1図b参照〕。この熱
乾燥は、薄膜3とレジストパターン4との密着
性を良くするための従来の熱乾燥行程によつて
行われる。
(b) Next, the semiconductor substrate 1 on which the resist pattern 4 is formed is subjected to a treatment such as immersing it in an organic solvent or exposing it to its atmosphere. As the organic solvent, xylene or N-butyl acetate can be used, as long as it can cause the resist to sag (or partially dissolve it).
As a result, the thermally stable material surrounding the resist pattern 4 is removed or altered. After that, heat drying is carried out, and the resist pattern 4 is sufficiently deformed at this temperature, and the air is dried.
Embed 5, 5... [See Figure 1b]. This thermal drying is performed by a conventional thermal drying process for improving the adhesion between the thin film 3 and the resist pattern 4.

(c) 次に、湿式エツチングによつて薄膜3をエツ
チングし、電極および配線パターン6を形成す
る〔第1図c参照〕。
(c) Next, the thin film 3 is etched by wet etching to form electrodes and wiring patterns 6 [see FIG. 1c].

このようにして形成された電極および配線パタ
ーン6は、第2図に示すように直線的になる。
The electrode and wiring pattern 6 thus formed are linear as shown in FIG.

(発明の効果) 以上説明したように、本発明にかかる半導体装
置の製造方法によれば、乾式エツチングでなけれ
ば不可能とされていた微細な電極、配線加工を、
生産性が良好で低コストの湿式エツチングで行う
ことができ、また歩留りの向上に有効である。
(Effects of the Invention) As explained above, according to the method for manufacturing a semiconductor device according to the present invention, fine electrode and wiring processing, which was considered impossible except by dry etching, can be performed.
It can be performed by wet etching, which has good productivity and low cost, and is effective in improving yield.

【図面の簡単な説明】[Brief explanation of drawings]

第1図a〜cは本発明にかかる半導体装置の製
造方法を説明する工程図、第2図は第1図a〜c
の製造工程によつて形成された電極および配線パ
ターンの平面図、第3図は従来の電極および配線
パターンの平面図である。 1……半導体基板、2……絶縁膜、3……薄
膜、4……レジストパターン、5……空隙、6…
…電極および配線パターン。
1a to 1c are process diagrams illustrating the method for manufacturing a semiconductor device according to the present invention, and FIG.
FIG. 3 is a plan view of a conventional electrode and wiring pattern. DESCRIPTION OF SYMBOLS 1...Semiconductor substrate, 2...Insulating film, 3...Thin film, 4...Resist pattern, 5...Void, 6...
...electrodes and wiring patterns.

Claims (1)

【特許請求の範囲】 1 半導体基板に形成された絶縁膜上に電極およ
び配線パターンとなる薄膜を、ポジ型レジストの
パターニング後、湿式エツチングを行うことによ
り形成する方法において、 前記ポジ型レジストのパターニング後、湿式エ
ツチングを行う前に、半導体基板を有機溶剤に浸
すか又はその雰囲気中にさらし、さらに熱乾燥を
行うことを特徴とする半導体装置の製造方法。 2 薄膜が、Al,Al−Si合金、又は多結晶Siで
ある特許請求の範囲第1項記載の半導体装置の製
造方法。
[Scope of Claims] 1. A method for forming a thin film serving as an electrode and wiring pattern on an insulating film formed on a semiconductor substrate by patterning a positive resist and then performing wet etching, comprising: patterning the positive resist; After that, before performing wet etching, the semiconductor substrate is immersed in an organic solvent or exposed to its atmosphere, and further heat-dried. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the thin film is Al, Al-Si alloy, or polycrystalline Si.
JP60027330A 1985-02-13 1985-02-13 Manufacture of semiconductor device Granted JPS61185924A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60027330A JPS61185924A (en) 1985-02-13 1985-02-13 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60027330A JPS61185924A (en) 1985-02-13 1985-02-13 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS61185924A JPS61185924A (en) 1986-08-19
JPH055166B2 true JPH055166B2 (en) 1993-01-21

Family

ID=12218057

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60027330A Granted JPS61185924A (en) 1985-02-13 1985-02-13 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS61185924A (en)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5712981A (en) * 1980-06-30 1982-01-22 Nisshin Oil Mills Ltd:The Instant gratinlike food

Also Published As

Publication number Publication date
JPS61185924A (en) 1986-08-19

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