JPH0552057B2 - - Google Patents

Description

[Detailed description of the invention] (Industrial application field) The present invention relates to a method for forming wiring.

(Prior Art) For example, in the case of wiring in a semiconductor device, a conductor film is deposited on a base insulating film having a fine contact hole portion.

However, since contact holes in LSIs have steep sides and large steps, an aluminum film (conductor film) 5 is deposited on a silicon substrate 1 having a steep contact hole 3 using a conventional parallel plate sputtering method or vapor deposition method. As shown in FIG. 4, the shadow effect of the conductive film 5 itself, which is deposited in large amounts on the shoulder of the step of the contact hole 3, deteriorates the step coverage, making the wiring easy to break or become thin, which leads to problems with the LSI. Manufacturing yield and reliability will be significantly reduced. In order to prevent these drawbacks, recently, a bias sputtering method is used to deposit a conductor film in the contact hole, which allows the conductor film to be more densely filled in the contact hole and to flatten the surface of the deposited conductor film. At the 16th International Conference on Solid State Devices and Materials, Mogami et al.
Conference on Solid State Devices and
It is reported on pages 43-46 of Extend Abstract of Materials.

(Problem to be solved by the invention) However, when using the bias sputtering method, the stress of the deposited film depends on the bias voltage, and especially under high bias voltage conditions, a large compressive stress of about 10 ¹⁰ dynes/cm ² is generated. The formation of a film that contains metallurgical
Transactions) Volume 2, pp. 699-709. When a thin film having such a large stress is used as a wiring, it is likely to peel off during heat treatment, and the manufacturing yield and reliability of LSI will be significantly reduced.

An object of the present invention is to solve the problems of the conventional wiring formation method using the bias sputtering method, as described above, by forming a film with low stress by the bias sputtering method, thereby forming highly reliable wiring. The object of the present invention is to provide a forming method.

(Means for Solving the Problems) The present invention includes a first step of forming an insulating film on a substrate and then forming a contact hole in the insulating film, and a target having a composition of 2.0 to 3.0 molybdenum silicide. A second method of filling the hole to a part of the height of the hole under sputtering conditions that does not cause microcracks in the deposited silicide film and do not create grooves along the bottom of the hole side wall in the underlying substrate by a bias sputtering method using The composition of the unfilled portion of the hole is 3.5 to 3.5.
4.5 A method for forming interconnects, which comprises a third step of embedding in a deposited silicide film by a bias sputtering method using TARDET, which is molybdenum silicide, under sputtering conditions that do not cause microcracks.

(Operation) The present invention is based on detailed experiments conducted by the inventors on the high frequency bias sputtering method. The inventors have continued to experiment with the high frequency bias sputtering method using molybdenum silicide as a wiring material and molybdenum silicide having various compositions as targets, and have come to know the following facts. The composition ratio of the molybdenum silicide target is MoSi ₂ , MoSi _2.7 , MoSi ₄ 3
FIG. 3 shows the bias voltage dependence of the stress of thin films deposited by bias sputtering using different types of targets. The stress of thin films formed using targets with compositions of MoSi ₂ or MoSi _2.7 increases as the negative bias voltage increases, and
In this case, it becomes 10 ¹⁰ dyne/cm ² or more. On the contrary, the stress of thin films formed using targets of MoSi ₄ composition decreases as the negative bias voltage increases.

Therefore, when forming a film under high bias voltage conditions,
By using a target with a MoSi ₄ composition, low-pressure interconnects can be formed.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

1A to 1D are schematic cross-sectional views of a first embodiment of the present invention, and FIGS. 2A to 2D are schematic cross-sectional views showing the steps of a second embodiment of the present invention, respectively.

Figure 1a shows a silicon oxide film 2 with a thickness of about 1 μm on a single crystal silicon substrate 1 with a flat surface.
After being deposited using the CVD method, it is processed through a normal photoresist process and anisotropic dry etching process to form a 1μ diameter film.
This shows a state in which contact holes 3 of m are formed.

Next, as shown in FIG. 1b, the molybdenum silicide film is deposited within the contact hole without microcracks, and the sputtering conditions (argon Gas pressure 3mTorr, distance between electrodes 95mm, target side power density 5.7W/cm ² ,
A molybdenum silicide film 4 was formed using a high frequency bias sputtering method using a target with a composition of 2.7 molybdenum silicide and a substrate bias voltage of −100 V).
When the bias voltage is later set to -500V, the film is deposited to a thickness (approximately 0.1 μm) that does not cause a groove along the lateral side of the step in the hole portion on the underlying silicon substrate.

Next, as shown in FIG. 1c, the film deposition rate of the molybdenum silicide film deposited on the flat surface inside the contact hole portion is approximately twice the film deposition rate of the molybdenum silicide film deposited on the flat surface above the step of the contact hole portion. Sputtering conditions (argon gas pressure 3mTorr, distance between electrodes 95mm, target side power density 5.7W/cm ² , substrate bias voltage -500V)
A molybdenum silicide film 4 of about 0.9 μm is deposited on the flat surface on the step of the hole portion by high frequency bias sputtering using a target having a molybdenum tetrasilicide composition. Under these conditions, a molybdenum silicide film of approximately 1.8 μm is deposited inside the hole, a molybdenum silicide film of approximately 1 μm is deposited on the flat surface on the step of the hole, and a molybdenum silicide film of approximately 1 μm is deposited on the silicon oxide film having the contact hole. The molybdenum silicide film becomes almost flat. Furthermore, the stress of the deposited molybdenum silicide film is 10 ⁹ dyne/cm ²
It was low, below the table. After this, heat treatment at 900°C was performed, but no peeling of the film occurred. 3D IC
In the manufacturing process, for example, the first layer (lowest layer),
After forming device layers up to the second layer thereon, it may be desired to form a first layer via hole from the second layer and bury a conductor film therein for electrical connection. In this case, the aspect ratio becomes quite large and it is difficult to make the surface completely flat, so the only option is to fill in the step with good coverage, but the present invention can also be applied in this case.

Furthermore, FIGS. 2a and 2b show the same steps as FIGS. 1a and 1b. Next, as shown in Fig. 2c, the sputtering conditions (argon gas pressure of 3 mTorr, interelectrode distance of 95 mm, target side power density of 5.7 W/cm ² , substrate bias) were used to deposit the molybdenum silicide film deposited in the contact hole portion with good step coverage. Voltage -
A molybdenum silicide film 4 is deposited to a thickness of about 0.4 .mu.m by high frequency bias sputtering using a target having a composition of molybdenum tetrasilicide. Under these conditions, the molybdenum silicide film is deposited in the contact hole portion with good step coverage. Furthermore, as in the case of FIG. 1, the stress of the deposited molybdenum silicide film was low, on the order of 10 ⁹ dyne/cm ² or less. This was followed by heat treatment at 900°C, but no peeling occurred.

In the embodiments described above, the bias voltage was used as a parameter, but there is no need to limit it to this, and other sputtering conditions such as the target side power density and the distance between electrodes may be used as parameters. Reducing the power density on the target side has the same effect as increasing the bias voltage, and increasing the distance between the electrodes has the same effect as increasing the bias voltage.

(Effects of the Invention) As explained above, by using the method of the present invention, a contact hole with a steep side surface can be filled with a silicide film without causing a shadow effect and without producing microcracks in the deposited silicide film. Alternatively, a low-stress silicide film can be formed under bias sputtering conditions that allow deposition of a silicide film with good step coverage. As a result, the possibility of peeling during heat treatment after wiring formation can be significantly reduced, and when used in LSI,
Reliability and yield can be significantly improved.

[Brief explanation of the drawing]

1A to 1C are schematic sectional views sequentially showing a first embodiment of the present invention step by step, and FIGS. 2A to 2C are schematic sectional views showing a second embodiment of the present invention step by step. The schematic cross-sectional view in Figure 3 shows MoSi ₂ , MoSi _2.7 ,
A diagram to explain the bias voltage dependence of the stress of a molybdenum silicide film deposited by high-frequency bias sputtering using three types of targets with MoSi ₄ composition. FIG. 3 is a schematic cross-sectional view of a contact hole portion when deposited on a substrate in which a contact hole having a steep side surface is formed. 1...Silicon substrate, 2...Silicon oxide film,
3...Contact hole, 4...Molybdenum silicide film, 5...Aluminum film.

Claims (1)

[Claims] 1 After forming an insulating film on a substrate, a first step of forming a contact hole in the insulating film and a step of forming a contact hole in the insulating film, and
The holes are sputtered using a bias sputtering method using a target of 2.0-3.0 molybdenum silicide under sputtering conditions that do not cause microcracks in the deposited silicide film and do not create grooves along the bottom of the hole sidewalls in the underlying substrate. A second step of filling up to a part of the height and a bias sputtering method using a target having a composition of 3.5 to 4.5 molybdenum silicide to fill the unfilled portion of the hole will prevent microcracks from occurring in the deposited silicide film. A method for forming a wiring, comprising a third step of embedding according to sputtering conditions.